Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T1	1		T21	1		T13	1
class_index[0x1]	69	1			T38	1		T77	1		T81	1
class_index[0x2]	49	1			T13	1		T14	2		T76	1
class_index[0x3]	69	1			T1	1		T21	1		T22	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	114	1			T21	1		T14	5		T70	1
intr_timeout_cnt[1]	49	1			T21	1		T13	1		T22	1
intr_timeout_cnt[2]	24	1			T13	1		T82	1		T83	1
intr_timeout_cnt[3]	14	1			T22	1		T75	1		T38	1
intr_timeout_cnt[4]	15	1			T1	1		T38	1		T239	1
intr_timeout_cnt[5]	9	1			T29	1		T111	1		T274	1
intr_timeout_cnt[6]	4	1			T1	1		T275	1		T272	1
intr_timeout_cnt[7]	9	1			T55	1		T32	1		T239	1
intr_timeout_cnt[8]	13	1			T38	2		T56	1		T85	1
intr_timeout_cnt[9]	6	1			T123	2		T276	1		T95	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	31	1			T21	1		T14	3		T81	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T13	1		T81	1		T277	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T82	1		T239	1		T278	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T22	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	6	1			T38	1		T279	1		T250	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T280	1		T182	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T1	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T55	1		T58	1		T281	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T85	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T123	1		T95	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	32	1			T77	1		T81	1		T29	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T38	1		T56	1		T96	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T83	1		T96	1		T282	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T86	1		T283	2		T284	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T239	1		T242	1		T285	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T29	1		T274	1		T286	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T32	1		T287	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	5	1			T58	1		T288	1		T241	2
class_index[0x1]	intr_timeout_cnt[9]	1	1			T242	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T14	2		T76	1		T129	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T41	1		T53	1		T80	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T13	1		T96	1		T289	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T38	1		T274	1		T290	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T291	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T280	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T292	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T239	1		T117	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T56	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T123	1		T276	1		T293	1
class_index[0x3]	intr_timeout_cnt[0]	29	1			T70	1		T28	1		T32	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T21	1		T22	1		T73	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T96	2		T287	1		T282	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T75	1		T256	1		T294	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T1	1		T59	1		T274	2
class_index[0x3]	intr_timeout_cnt[5]	2	1			T111	1		T291	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T275	1		T272	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T274	1		T295	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	6	1			T38	2		T123	1		T278	1