Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341533	1			T1	62		T2	1521		T3	1851
all_values[1]	341533	1			T1	62		T2	1521		T3	1851
all_values[2]	341533	1			T1	62		T2	1521		T3	1851
all_values[3]	341533	1			T1	62		T2	1521		T3	1851

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679339

1

T1

132

T2

2991

T3

3753

auto[1]

686793

1

T1

116

T2

3093

T3

3651

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

811990

1

T1

113

T2

3076

T3

3747

auto[1]

554142

1

T1

135

T2

3008

T3

3657

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99161	1			T1	18		T2	359		T3	455
all_values[0]	auto[0]	auto[1]	70935	1			T1	17		T2	359		T3	451
all_values[0]	auto[1]	auto[0]	100563	1			T1	10		T2	402		T3	473
all_values[0]	auto[1]	auto[1]	70874	1			T1	17		T2	401		T3	472
all_values[1]	auto[0]	auto[0]	102564	1			T1	17		T2	374		T3	486
all_values[1]	auto[0]	auto[1]	67125	1			T1	20		T2	373		T3	485
all_values[1]	auto[1]	auto[0]	104144	1			T1	12		T2	391		T3	441
all_values[1]	auto[1]	auto[1]	67700	1			T1	13		T2	383		T3	439
all_values[2]	auto[0]	auto[0]	100023	1			T1	14		T2	394		T3	478
all_values[2]	auto[0]	auto[1]	69575	1			T1	18		T2	384		T3	478
all_values[2]	auto[1]	auto[0]	101849	1			T1	14		T2	374		T3	448
all_values[2]	auto[1]	auto[1]	70086	1			T1	16		T2	369		T3	447
all_values[3]	auto[0]	auto[0]	101277	1			T1	12		T2	384		T3	486
all_values[3]	auto[0]	auto[1]	68679	1			T1	16		T2	364		T3	434
all_values[3]	auto[1]	auto[0]	102409	1			T1	16		T2	398		T3	480
all_values[3]	auto[1]	auto[1]	69168	1			T1	18		T2	375		T3	451