Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341533	1			T1	62		T2	1521		T3	1851
all_pins[1]	341533	1			T1	62		T2	1521		T3	1851
all_pins[2]	341533	1			T1	62		T2	1521		T3	1851
all_pins[3]	341533	1			T1	62		T2	1521		T3	1851

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1088304	1			T1	184		T2	4556		T3	5595
values[0x1]	277828	1			T1	64		T2	1528		T3	1809
transitions[0x0=>0x1]	183474	1			T1	40		T2	949		T3	1154
transitions[0x1=>0x0]	183700	1			T1	40		T2	949		T3	1155

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270659	1			T1	45		T2	1120		T3	1379
all_pins[0]	values[0x1]	70874	1			T1	17		T2	401		T3	472
all_pins[0]	transitions[0x0=>0x1]	70250	1			T1	14		T2	401		T3	471
all_pins[0]	transitions[0x1=>0x0]	68770	1			T1	15		T2	375		T3	451
all_pins[1]	values[0x0]	273833	1			T1	49		T2	1138		T3	1412
all_pins[1]	values[0x1]	67700	1			T1	13		T2	383		T3	439
all_pins[1]	transitions[0x0=>0x1]	36900	1			T1	9		T2	180		T3	213
all_pins[1]	transitions[0x1=>0x0]	40074	1			T1	13		T2	198		T3	246
all_pins[2]	values[0x0]	271447	1			T1	46		T2	1152		T3	1404
all_pins[2]	values[0x1]	70086	1			T1	16		T2	369		T3	447
all_pins[2]	transitions[0x0=>0x1]	39014	1			T1	10		T2	180		T3	247
all_pins[2]	transitions[0x1=>0x0]	36628	1			T1	7		T2	194		T3	239
all_pins[3]	values[0x0]	272365	1			T1	44		T2	1146		T3	1400
all_pins[3]	values[0x1]	69168	1			T1	18		T2	375		T3	451
all_pins[3]	transitions[0x0=>0x1]	37310	1			T1	7		T2	188		T3	223
all_pins[3]	transitions[0x1=>0x0]	38228	1			T1	5		T2	182		T3	219