Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87373	1			T2	512		T3	1659		T4	1
accum_cnt_1000	233823	1			T2	480		T3	1782		T4	459
accum_cnt_100	27992	1			T1	3		T2	28		T3	106
accum_cnt_50	66327	1			T1	72		T2	16		T3	87
accum_cnt_10	165231	1			T1	114		T2	1134		T3	33
accum_cnt_0	385935	1			T1	43		T2	2238		T3	1422

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	252081	1			T1	58		T2	1119		T3	1407
class_index[0x1]	252081	1			T1	58		T2	1119		T3	1407
class_index[0x2]	252081	1			T1	58		T2	1119		T3	1407
class_index[0x3]	252081	1			T1	58		T2	1119		T3	1407

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21041	1			T3	569		T4	1		T33	181
class_index[0x0]	accum_cnt_1000	61014	1			T3	529		T4	51		T13	23
class_index[0x0]	accum_cnt_100	8609	1			T3	31		T4	21		T13	27
class_index[0x0]	accum_cnt_50	16759	1			T1	7		T3	23		T4	42
class_index[0x0]	accum_cnt_10	45664	1			T1	43		T2	2		T3	10
class_index[0x0]	accum_cnt_0	89073	1			T1	8		T2	1117		T3	5
class_index[0x1]	accum_cnt_2000	24641	1			T3	561		T14	566		T68	362
class_index[0x1]	accum_cnt_1000	57432	1			T3	480		T4	351		T22	27
class_index[0x1]	accum_cnt_100	7303	1			T3	27		T4	90		T22	34
class_index[0x1]	accum_cnt_50	12500	1			T1	9		T3	24		T4	71
class_index[0x1]	accum_cnt_10	41523	1			T1	28		T2	1117		T3	11
class_index[0x1]	accum_cnt_0	95524	1			T1	21		T2	2		T3	5
class_index[0x2]	accum_cnt_2000	17783	1			T2	512		T15	612		T68	536
class_index[0x2]	accum_cnt_1000	52720	1			T2	480		T22	5		T14	58
class_index[0x2]	accum_cnt_100	5164	1			T1	3		T2	28		T22	42
class_index[0x2]	accum_cnt_50	17335	1			T1	33		T2	16		T21	16
class_index[0x2]	accum_cnt_10	42315	1			T1	15		T2	13		T3	1
class_index[0x2]	accum_cnt_0	106559	1			T1	7		T2	2		T3	1406
class_index[0x3]	accum_cnt_2000	23908	1			T3	529		T5	390		T14	521
class_index[0x3]	accum_cnt_1000	62657	1			T3	773		T4	57		T22	29
class_index[0x3]	accum_cnt_100	6916	1			T3	48		T4	14		T13	28
class_index[0x3]	accum_cnt_50	19733	1			T1	23		T3	40		T4	41
class_index[0x3]	accum_cnt_10	35729	1			T1	28		T2	2		T3	11
class_index[0x3]	accum_cnt_0	94779	1			T1	7		T2	1117		T3	6