Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5685	1			T1	33		T4	21		T15	389
alert[0x1]	4089	1			T13	169		T15	236		T46	169
alert[0x2]	5458	1			T4	6		T15	34		T46	153
alert[0x3]	6800	1			T72	529		T94	12		T296	12
alert[0x4]	8531	1			T15	19		T46	8		T72	29
alert[0x5]	4368	1			T22	6		T72	11		T92	1
alert[0x6]	9223	1			T46	13		T72	41		T38	18
alert[0x7]	8204	1			T13	13		T15	127		T6	2
alert[0x8]	8661	1			T46	1113		T231	1		T102	3
alert[0x9]	8797	1			T15	47		T46	23		T297	1
alert[0xa]	9943	1			T1	1		T13	1		T46	1025
alert[0xb]	14528	1			T13	1		T15	148		T47	153
alert[0xc]	7044	1			T13	5		T15	428		T46	84
alert[0xd]	6471	1			T14	1		T46	106		T72	133
alert[0xe]	11996	1			T15	69		T8	1		T72	877
alert[0xf]	5883	1			T46	130		T7	1		T72	3
alert[0x10]	11300	1			T1	10		T13	3		T14	1
alert[0x11]	5581	1			T33	293		T296	1		T38	62
alert[0x12]	9184	1			T14	8		T46	252		T72	9
alert[0x13]	7722	1			T4	20		T14	7		T15	198
alert[0x14]	7972	1			T14	4		T72	12		T76	2
alert[0x15]	5042	1			T46	213		T72	17		T33	278
alert[0x16]	6940	1			T14	3		T15	35		T46	376
alert[0x17]	7273	1			T15	116		T8	1		T72	53
alert[0x18]	4034	1			T13	1		T15	1		T46	288
alert[0x19]	7120	1			T1	4		T15	431		T33	88
alert[0x1a]	12072	1			T4	52		T8	1		T72	3320
alert[0x1b]	9250	1			T15	15		T8	1		T47	181
alert[0x1c]	14517	1			T1	1		T15	31		T46	757
alert[0x1d]	6332	1			T13	1		T14	1		T46	58
alert[0x1e]	7473	1			T14	1		T15	48		T46	109
alert[0x1f]	6287	1			T14	10		T15	720		T46	32
alert[0x20]	4676	1			T7	1		T47	102		T74	1
alert[0x21]	5399	1			T13	2		T46	108		T7	1
alert[0x22]	7098	1			T15	1889		T33	26		T43	9
alert[0x23]	5666	1			T13	2		T15	15		T46	19
alert[0x24]	3811	1			T1	10		T13	1		T22	1
alert[0x25]	7637	1			T46	33		T33	78		T76	12
alert[0x26]	4601	1			T46	26		T8	2		T72	535
alert[0x27]	3440	1			T46	205		T7	1		T47	36
alert[0x28]	13379	1			T1	3		T13	6		T14	2
alert[0x29]	5577	1			T13	31		T15	183		T47	694
alert[0x2a]	11851	1			T72	43		T296	1		T87	12
alert[0x2b]	6212	1			T13	34		T33	185		T92	1
alert[0x2c]	7627	1			T13	1		T14	7		T46	1
alert[0x2d]	4594	1			T1	4		T4	25		T46	17
alert[0x2e]	6847	1			T46	536		T7	1		T8	1
alert[0x2f]	6432	1			T13	1		T15	3286		T46	457
alert[0x30]	8335	1			T13	3		T15	38		T46	87
alert[0x31]	7834	1			T1	4		T13	100		T72	2
alert[0x32]	5282	1			T8	1		T72	25		T296	2
alert[0x33]	11786	1			T13	11		T14	1		T15	88
alert[0x34]	13922	1			T22	1		T46	4278		T8	1
alert[0x35]	4345	1			T14	24		T15	43		T46	2
alert[0x36]	7574	1			T1	21		T4	64		T14	2
alert[0x37]	10470	1			T13	6		T14	25		T15	14
alert[0x38]	12941	1			T15	7525		T46	18		T9	2
alert[0x39]	4557	1			T22	1		T15	401		T8	1
alert[0x3a]	7765	1			T14	12		T15	37		T46	59
alert[0x3b]	5309	1			T14	3		T15	62		T46	42
alert[0x3c]	5086	1			T13	2		T46	149		T47	260
alert[0x3d]	8459	1			T13	6		T15	245		T46	2988
alert[0x3e]	6040	1			T46	21		T47	67		T33	1341
alert[0x3f]	3986	1			T13	1		T22	1		T14	1
alert[0x40]	17394	1			T14	1		T47	121		T38	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	119058	1			T4	6		T13	49		T22	10
class_i[0x1]	128968	1			T13	4		T14	11		T46	14774
class_i[0x2]	155336	1			T1	91		T13	11		T14	48
class_i[0x3]	96350	1			T4	182		T13	337		T14	55

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

499091

1

T1

91

T4

188

T13

401

alert_ping_fail

621

1

T6

2

T7

9

T8

18

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5677	1			T1	33		T4	21		T15	389
alert_integrity_fail	alert[0x1]	4080	1			T13	169		T15	236		T46	169
alert_integrity_fail	alert[0x2]	5453	1			T4	6		T15	34		T46	153
alert_integrity_fail	alert[0x3]	6785	1			T72	529		T94	12		T296	12
alert_integrity_fail	alert[0x4]	8527	1			T15	19		T46	8		T72	29
alert_integrity_fail	alert[0x5]	4358	1			T22	6		T72	11		T87	1
alert_integrity_fail	alert[0x6]	9210	1			T46	13		T72	41		T38	18
alert_integrity_fail	alert[0x7]	8196	1			T13	13		T15	127		T72	608
alert_integrity_fail	alert[0x8]	8650	1			T46	1113		T102	3		T43	14
alert_integrity_fail	alert[0x9]	8792	1			T15	47		T46	23		T76	4
alert_integrity_fail	alert[0xa]	9932	1			T1	1		T13	1		T46	1025
alert_integrity_fail	alert[0xb]	14524	1			T13	1		T15	148		T47	153
alert_integrity_fail	alert[0xc]	7036	1			T13	5		T15	428		T46	84
alert_integrity_fail	alert[0xd]	6460	1			T14	1		T46	106		T72	133
alert_integrity_fail	alert[0xe]	11989	1			T15	69		T72	877		T296	37
alert_integrity_fail	alert[0xf]	5875	1			T46	130		T72	3		T75	4
alert_integrity_fail	alert[0x10]	11294	1			T1	10		T13	3		T14	1
alert_integrity_fail	alert[0x11]	5577	1			T33	293		T296	1		T38	62
alert_integrity_fail	alert[0x12]	9176	1			T14	8		T46	252		T72	9
alert_integrity_fail	alert[0x13]	7717	1			T4	20		T14	7		T15	198
alert_integrity_fail	alert[0x14]	7963	1			T14	4		T72	12		T76	2
alert_integrity_fail	alert[0x15]	5030	1			T46	213		T72	17		T33	278
alert_integrity_fail	alert[0x16]	6928	1			T14	3		T15	35		T46	376
alert_integrity_fail	alert[0x17]	7255	1			T15	116		T72	53		T75	6
alert_integrity_fail	alert[0x18]	4022	1			T13	1		T15	1		T46	288
alert_integrity_fail	alert[0x19]	7111	1			T1	4		T15	431		T33	88
alert_integrity_fail	alert[0x1a]	12062	1			T4	52		T72	3320		T94	3
alert_integrity_fail	alert[0x1b]	9238	1			T15	15		T47	181		T33	15
alert_integrity_fail	alert[0x1c]	14503	1			T1	1		T15	31		T46	757
alert_integrity_fail	alert[0x1d]	6321	1			T13	1		T14	1		T46	58
alert_integrity_fail	alert[0x1e]	7467	1			T14	1		T15	48		T46	109
alert_integrity_fail	alert[0x1f]	6274	1			T14	10		T15	720		T46	32
alert_integrity_fail	alert[0x20]	4660	1			T47	102		T33	145		T296	38
alert_integrity_fail	alert[0x21]	5388	1			T13	2		T46	108		T72	311
alert_integrity_fail	alert[0x22]	7087	1			T15	1889		T33	26		T43	9
alert_integrity_fail	alert[0x23]	5657	1			T13	2		T15	15		T46	19
alert_integrity_fail	alert[0x24]	3802	1			T1	10		T13	1		T22	1
alert_integrity_fail	alert[0x25]	7632	1			T46	33		T33	78		T76	12
alert_integrity_fail	alert[0x26]	4586	1			T46	26		T72	535		T75	1
alert_integrity_fail	alert[0x27]	3435	1			T46	205		T47	36		T75	1
alert_integrity_fail	alert[0x28]	13374	1			T1	3		T13	6		T14	2
alert_integrity_fail	alert[0x29]	5569	1			T13	31		T15	183		T47	694
alert_integrity_fail	alert[0x2a]	11841	1			T72	43		T296	1		T87	12
alert_integrity_fail	alert[0x2b]	6199	1			T13	34		T33	185		T50	22
alert_integrity_fail	alert[0x2c]	7607	1			T13	1		T14	7		T46	1
alert_integrity_fail	alert[0x2d]	4583	1			T1	4		T4	25		T46	17
alert_integrity_fail	alert[0x2e]	6833	1			T46	536		T72	587		T94	6
alert_integrity_fail	alert[0x2f]	6426	1			T13	1		T15	3286		T46	457
alert_integrity_fail	alert[0x30]	8325	1			T13	3		T15	38		T46	87
alert_integrity_fail	alert[0x31]	7820	1			T1	4		T13	100		T72	2
alert_integrity_fail	alert[0x32]	5275	1			T72	25		T296	2		T43	96
alert_integrity_fail	alert[0x33]	11775	1			T13	11		T14	1		T15	88
alert_integrity_fail	alert[0x34]	13914	1			T22	1		T46	4278		T94	1
alert_integrity_fail	alert[0x35]	4334	1			T14	24		T15	43		T46	2
alert_integrity_fail	alert[0x36]	7563	1			T1	21		T4	64		T14	2
alert_integrity_fail	alert[0x37]	10454	1			T13	6		T14	25		T15	14
alert_integrity_fail	alert[0x38]	12934	1			T15	7525		T46	18		T33	327
alert_integrity_fail	alert[0x39]	4552	1			T22	1		T15	401		T72	7
alert_integrity_fail	alert[0x3a]	7753	1			T14	12		T15	37		T46	59
alert_integrity_fail	alert[0x3b]	5297	1			T14	3		T15	62		T46	42
alert_integrity_fail	alert[0x3c]	5074	1			T13	2		T46	149		T47	260
alert_integrity_fail	alert[0x3d]	8449	1			T13	6		T15	245		T46	2988
alert_integrity_fail	alert[0x3e]	6035	1			T46	21		T47	67		T33	1341
alert_integrity_fail	alert[0x3f]	3984	1			T13	1		T22	1		T14	1
alert_integrity_fail	alert[0x40]	17392	1			T14	1		T47	121		T38	33
alert_ping_fail	alert[0x0]	8	1			T247	2		T298	1		T299	1
alert_ping_fail	alert[0x1]	9	1			T231	2		T298	1		T300	1
alert_ping_fail	alert[0x2]	5	1			T92	1		T301	1		T302	1
alert_ping_fail	alert[0x3]	15	1			T231	2		T303	1		T247	1
alert_ping_fail	alert[0x4]	4	1			T92	1		T304	1		T305	1
alert_ping_fail	alert[0x5]	10	1			T92	1		T231	1		T268	1
alert_ping_fail	alert[0x6]	13	1			T259	1		T263	1		T306	1
alert_ping_fail	alert[0x7]	8	1			T6	2		T298	1		T307	1
alert_ping_fail	alert[0x8]	11	1			T231	1		T308	1		T247	1
alert_ping_fail	alert[0x9]	5	1			T297	1		T231	1		T304	1
alert_ping_fail	alert[0xa]	11	1			T8	1		T309	1		T310	1
alert_ping_fail	alert[0xb]	4	1			T231	2		T303	1		T305	1
alert_ping_fail	alert[0xc]	8	1			T9	1		T311	1		T312	1
alert_ping_fail	alert[0xd]	11	1			T313	1		T302	1		T314	3
alert_ping_fail	alert[0xe]	7	1			T8	1		T311	1		T309	1
alert_ping_fail	alert[0xf]	8	1			T7	1		T314	1		T315	1
alert_ping_fail	alert[0x10]	6	1			T7	1		T92	1		T259	1
alert_ping_fail	alert[0x11]	4	1			T313	1		T300	1		T316	1
alert_ping_fail	alert[0x12]	8	1			T297	1		T231	1		T311	1
alert_ping_fail	alert[0x13]	5	1			T247	1		T306	1		T317	1
alert_ping_fail	alert[0x14]	9	1			T303	1		T318	1		T248	2
alert_ping_fail	alert[0x15]	12	1			T297	1		T230	1		T319	1
alert_ping_fail	alert[0x16]	12	1			T247	1		T313	2		T302	1
alert_ping_fail	alert[0x17]	18	1			T8	1		T230	1		T311	1
alert_ping_fail	alert[0x18]	12	1			T297	1		T231	1		T259	1
alert_ping_fail	alert[0x19]	9	1			T320	1		T313	1		T314	1
alert_ping_fail	alert[0x1a]	10	1			T8	1		T297	1		T92	1
alert_ping_fail	alert[0x1b]	12	1			T8	1		T259	1		T303	1
alert_ping_fail	alert[0x1c]	14	1			T259	1		T311	1		T313	1
alert_ping_fail	alert[0x1d]	11	1			T92	2		T259	1		T303	1
alert_ping_fail	alert[0x1e]	6	1			T231	1		T259	1		T321	1
alert_ping_fail	alert[0x1f]	13	1			T8	1		T303	1		T313	1
alert_ping_fail	alert[0x20]	16	1			T7	1		T74	1		T230	1
alert_ping_fail	alert[0x21]	11	1			T7	1		T322	1		T259	1
alert_ping_fail	alert[0x22]	11	1			T247	2		T312	1		T300	1
alert_ping_fail	alert[0x23]	9	1			T303	2		T247	1		T248	1
alert_ping_fail	alert[0x24]	9	1			T9	1		T297	1		T303	1
alert_ping_fail	alert[0x25]	5	1			T321	1		T323	1		T324	1
alert_ping_fail	alert[0x26]	15	1			T8	2		T230	1		T231	1
alert_ping_fail	alert[0x27]	5	1			T7	1		T302	1		T325	1
alert_ping_fail	alert[0x28]	5	1			T311	1		T302	1		T326	1
alert_ping_fail	alert[0x29]	8	1			T297	1		T231	2		T259	1
alert_ping_fail	alert[0x2a]	10	1			T320	1		T259	2		T327	1
alert_ping_fail	alert[0x2b]	13	1			T92	1		T259	1		T301	1
alert_ping_fail	alert[0x2c]	20	1			T74	1		T230	1		T37	1
alert_ping_fail	alert[0x2d]	11	1			T7	1		T8	1		T9	1
alert_ping_fail	alert[0x2e]	14	1			T7	1		T8	1		T231	1
alert_ping_fail	alert[0x2f]	6	1			T8	2		T259	1		T302	1
alert_ping_fail	alert[0x30]	10	1			T328	1		T313	1		T302	1
alert_ping_fail	alert[0x31]	14	1			T230	1		T303	1		T301	1
alert_ping_fail	alert[0x32]	7	1			T8	1		T231	1		T247	1
alert_ping_fail	alert[0x33]	11	1			T297	1		T329	1		T330	1
alert_ping_fail	alert[0x34]	8	1			T8	1		T303	1		T318	1
alert_ping_fail	alert[0x35]	11	1			T8	1		T297	1		T231	1
alert_ping_fail	alert[0x36]	11	1			T9	1		T297	2		T259	1
alert_ping_fail	alert[0x37]	16	1			T7	2		T8	1		T92	1
alert_ping_fail	alert[0x38]	7	1			T9	2		T301	1		T331	1
alert_ping_fail	alert[0x39]	5	1			T8	1		T231	1		T332	1
alert_ping_fail	alert[0x3a]	12	1			T230	1		T259	1		T318	1
alert_ping_fail	alert[0x3b]	12	1			T92	1		T231	2		T329	1
alert_ping_fail	alert[0x3c]	12	1			T303	1		T313	1		T248	1
alert_ping_fail	alert[0x3d]	10	1			T9	1		T230	1		T259	1
alert_ping_fail	alert[0x3e]	5	1			T231	1		T301	1		T314	1
alert_ping_fail	alert[0x3f]	2	1			T8	1		T329	1		-	-
alert_ping_fail	alert[0x40]	2	1			T320	1		T314	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	118925	1			T4	6		T13	49		T22	10
alert_integrity_fail	class_i[0x1]	128794	1			T13	4		T14	11		T46	14774
alert_integrity_fail	class_i[0x2]	155236	1			T1	91		T13	11		T14	48
alert_integrity_fail	class_i[0x3]	96136	1			T4	182		T13	337		T14	55
alert_ping_fail	class_i[0x0]	133	1			T6	2		T7	6		T297	1
alert_ping_fail	class_i[0x1]	174	1			T7	2		T8	16		T74	2
alert_ping_fail	class_i[0x2]	100	1			T7	1		T8	1		T9	7
alert_ping_fail	class_i[0x3]	214	1			T8	1		T297	8		T92	1