Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.67 100.00 100.00 100.00 99.38 99.60


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T768 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1961597789 Jun 24 06:40:02 PM PDT 24 Jun 24 06:40:05 PM PDT 24 14944287 ps
T769 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1025174079 Jun 24 06:39:58 PM PDT 24 Jun 24 06:40:01 PM PDT 24 15321372 ps
T770 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3679416595 Jun 24 06:39:10 PM PDT 24 Jun 24 06:40:28 PM PDT 24 537269640 ps
T176 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2260734263 Jun 24 06:39:39 PM PDT 24 Jun 24 06:39:46 PM PDT 24 39438463 ps
T771 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2255467749 Jun 24 06:39:36 PM PDT 24 Jun 24 06:39:48 PM PDT 24 510764093 ps
T772 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2270961032 Jun 24 06:39:59 PM PDT 24 Jun 24 06:40:03 PM PDT 24 11715667 ps
T151 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3406416031 Jun 24 06:39:10 PM PDT 24 Jun 24 06:53:43 PM PDT 24 71489098988 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.76393335 Jun 24 06:39:35 PM PDT 24 Jun 24 06:39:45 PM PDT 24 97125778 ps
T159 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2022266779 Jun 24 06:39:45 PM PDT 24 Jun 24 06:42:44 PM PDT 24 2637888161 ps
T171 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3930997491 Jun 24 06:39:23 PM PDT 24 Jun 24 06:39:28 PM PDT 24 71136499 ps
T774 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1398164264 Jun 24 06:39:44 PM PDT 24 Jun 24 06:39:54 PM PDT 24 402329969 ps
T775 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.612711656 Jun 24 06:39:31 PM PDT 24 Jun 24 06:39:34 PM PDT 24 133861427 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2399551140 Jun 24 06:39:33 PM PDT 24 Jun 24 06:39:40 PM PDT 24 120976315 ps
T777 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2726945801 Jun 24 06:39:48 PM PDT 24 Jun 24 06:40:12 PM PDT 24 951449448 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2047881136 Jun 24 06:39:42 PM PDT 24 Jun 24 06:45:25 PM PDT 24 2415391843 ps
T778 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.63860317 Jun 24 06:39:29 PM PDT 24 Jun 24 06:39:31 PM PDT 24 14104916 ps
T779 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1816985793 Jun 24 06:40:04 PM PDT 24 Jun 24 06:40:08 PM PDT 24 11703345 ps
T780 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2200704753 Jun 24 06:40:03 PM PDT 24 Jun 24 06:40:06 PM PDT 24 26904576 ps
T168 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.71456874 Jun 24 06:39:36 PM PDT 24 Jun 24 06:39:44 PM PDT 24 54729113 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3288964842 Jun 24 06:39:13 PM PDT 24 Jun 24 06:39:31 PM PDT 24 469070848 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.110797804 Jun 24 06:39:36 PM PDT 24 Jun 24 06:39:43 PM PDT 24 67866847 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.514565955 Jun 24 06:39:11 PM PDT 24 Jun 24 06:39:21 PM PDT 24 115910531 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2995712416 Jun 24 06:39:43 PM PDT 24 Jun 24 06:39:46 PM PDT 24 9355378 ps
T785 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.140860320 Jun 24 06:39:48 PM PDT 24 Jun 24 06:39:55 PM PDT 24 314974453 ps
T786 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2158183705 Jun 24 06:39:41 PM PDT 24 Jun 24 06:39:48 PM PDT 24 51689280 ps
T787 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.59564671 Jun 24 06:39:50 PM PDT 24 Jun 24 06:39:53 PM PDT 24 11945402 ps
T366 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1931568450 Jun 24 06:39:38 PM PDT 24 Jun 24 06:51:26 PM PDT 24 9196931893 ps
T788 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2856439084 Jun 24 06:40:03 PM PDT 24 Jun 24 06:40:07 PM PDT 24 23803505 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3180255206 Jun 24 06:39:46 PM PDT 24 Jun 24 06:40:26 PM PDT 24 504999199 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3506116776 Jun 24 06:39:12 PM PDT 24 Jun 24 06:39:24 PM PDT 24 36635482 ps
T173 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4029209323 Jun 24 06:39:49 PM PDT 24 Jun 24 06:40:32 PM PDT 24 2254859781 ps
T791 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4257590022 Jun 24 06:39:47 PM PDT 24 Jun 24 06:39:57 PM PDT 24 52681602 ps
T792 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2599287877 Jun 24 06:39:45 PM PDT 24 Jun 24 06:39:49 PM PDT 24 6476748 ps
T793 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3918979333 Jun 24 06:39:45 PM PDT 24 Jun 24 06:40:10 PM PDT 24 1941576833 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4201104565 Jun 24 06:39:12 PM PDT 24 Jun 24 06:39:27 PM PDT 24 125748375 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.36568257 Jun 24 06:39:41 PM PDT 24 Jun 24 06:39:54 PM PDT 24 88487185 ps
T796 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3312167607 Jun 24 06:39:43 PM PDT 24 Jun 24 06:39:48 PM PDT 24 100034095 ps
T797 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.231394915 Jun 24 06:39:43 PM PDT 24 Jun 24 06:40:22 PM PDT 24 2053603505 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.609618651 Jun 24 06:39:42 PM PDT 24 Jun 24 06:39:55 PM PDT 24 499086972 ps
T799 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.725079373 Jun 24 06:40:05 PM PDT 24 Jun 24 06:40:09 PM PDT 24 14114697 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1435743057 Jun 24 06:39:50 PM PDT 24 Jun 24 06:39:53 PM PDT 24 16025369 ps
T801 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2396513189 Jun 24 06:39:57 PM PDT 24 Jun 24 06:40:01 PM PDT 24 17437597 ps
T802 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1940011075 Jun 24 06:39:15 PM PDT 24 Jun 24 06:40:02 PM PDT 24 3150193639 ps
T803 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1956272349 Jun 24 06:39:45 PM PDT 24 Jun 24 06:39:59 PM PDT 24 87692172 ps
T804 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1589963479 Jun 24 06:39:58 PM PDT 24 Jun 24 06:40:01 PM PDT 24 7710918 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1111746270 Jun 24 06:39:12 PM PDT 24 Jun 24 06:39:21 PM PDT 24 53300346 ps
T371 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1546336623 Jun 24 06:39:32 PM PDT 24 Jun 24 06:48:31 PM PDT 24 8170968429 ps
T806 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1781378729 Jun 24 06:39:46 PM PDT 24 Jun 24 06:39:57 PM PDT 24 198499208 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3158058245 Jun 24 06:39:58 PM PDT 24 Jun 24 06:40:46 PM PDT 24 2788098174 ps
T808 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4179170904 Jun 24 06:39:58 PM PDT 24 Jun 24 06:40:04 PM PDT 24 68744759 ps
T152 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1872471607 Jun 24 06:39:15 PM PDT 24 Jun 24 06:45:35 PM PDT 24 18559575885 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.837547627 Jun 24 06:39:41 PM PDT 24 Jun 24 06:39:56 PM PDT 24 83884875 ps
T172 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3165280025 Jun 24 06:39:44 PM PDT 24 Jun 24 06:40:28 PM PDT 24 358264156 ps
T810 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3704377695 Jun 24 06:40:06 PM PDT 24 Jun 24 06:40:10 PM PDT 24 9563266 ps
T811 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.410653561 Jun 24 06:39:41 PM PDT 24 Jun 24 06:39:55 PM PDT 24 159540211 ps
T367 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1737199470 Jun 24 06:39:50 PM PDT 24 Jun 24 06:53:02 PM PDT 24 5011232475 ps
T812 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1579181713 Jun 24 06:39:28 PM PDT 24 Jun 24 06:39:37 PM PDT 24 454503294 ps
T155 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3035711904 Jun 24 06:39:44 PM PDT 24 Jun 24 06:45:53 PM PDT 24 6042932349 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.281730349 Jun 24 06:39:11 PM PDT 24 Jun 24 06:43:04 PM PDT 24 1669694387 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3700565315 Jun 24 06:39:33 PM PDT 24 Jun 24 06:42:38 PM PDT 24 2973794376 ps
T370 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2369436349 Jun 24 06:39:36 PM PDT 24 Jun 24 06:56:42 PM PDT 24 16755207663 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3040899332 Jun 24 06:39:46 PM PDT 24 Jun 24 06:39:56 PM PDT 24 371237256 ps
T816 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.569708446 Jun 24 06:39:41 PM PDT 24 Jun 24 06:39:59 PM PDT 24 949194970 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.247871525 Jun 24 06:39:48 PM PDT 24 Jun 24 06:39:51 PM PDT 24 15339669 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.424660470 Jun 24 06:39:09 PM PDT 24 Jun 24 06:39:16 PM PDT 24 28425739 ps
T819 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2930266020 Jun 24 06:39:42 PM PDT 24 Jun 24 06:41:49 PM PDT 24 3662246791 ps
T820 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.357637910 Jun 24 06:39:48 PM PDT 24 Jun 24 06:40:04 PM PDT 24 85236600 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1102288872 Jun 24 06:39:35 PM PDT 24 Jun 24 06:40:16 PM PDT 24 636268093 ps
T822 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3338396044 Jun 24 06:39:34 PM PDT 24 Jun 24 06:44:53 PM PDT 24 8889121645 ps
T245 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2695267224 Jun 24 06:39:42 PM PDT 24 Jun 24 06:39:49 PM PDT 24 66508831 ps
T368 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1777358792 Jun 24 06:39:24 PM PDT 24 Jun 24 06:47:04 PM PDT 24 14140196542 ps
T823 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.844857587 Jun 24 06:39:56 PM PDT 24 Jun 24 06:39:59 PM PDT 24 9125176 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2672628303 Jun 24 06:39:45 PM PDT 24 Jun 24 06:39:50 PM PDT 24 103170702 ps
T825 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1066395720 Jun 24 06:39:23 PM PDT 24 Jun 24 06:42:06 PM PDT 24 3041680320 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3946549847 Jun 24 06:39:45 PM PDT 24 Jun 24 06:39:51 PM PDT 24 76684992 ps
T827 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1816333254 Jun 24 06:40:06 PM PDT 24 Jun 24 06:40:10 PM PDT 24 10305517 ps
T828 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2991231426 Jun 24 06:39:57 PM PDT 24 Jun 24 06:39:59 PM PDT 24 12583197 ps
T829 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.511981010 Jun 24 06:40:03 PM PDT 24 Jun 24 06:40:06 PM PDT 24 14931061 ps
T830 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2983984628 Jun 24 06:39:45 PM PDT 24 Jun 24 06:39:49 PM PDT 24 7958187 ps
T160 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3994676081 Jun 24 06:39:30 PM PDT 24 Jun 24 06:42:40 PM PDT 24 6658226868 ps

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.455126462
Short name T13
Test name
Test status
Simulation time 21225738669 ps
CPU time 1264.8 seconds
Started Jun 24 06:41:13 PM PDT 24
Finished Jun 24 07:02:25 PM PDT 24
Peak memory 268932 kb
Host smart-abf3a709-10d8-4a6f-960f-ef3abc2a82bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455126462 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.455126462
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1336180055
Short name T14
Test name
Test status
Simulation time 234405191943 ps
CPU time 2927.61 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 07:29:52 PM PDT 24
Peak memory 288408 kb
Host smart-95e77044-8ed6-4154-9cbf-9842a34d71de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336180055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1336180055
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2950829507
Short name T10
Test name
Test status
Simulation time 635594859 ps
CPU time 12.06 seconds
Started Jun 24 06:40:22 PM PDT 24
Finished Jun 24 06:40:35 PM PDT 24
Peak memory 270860 kb
Host smart-c93afc4a-b76d-4888-8534-07de59982273
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2950829507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2950829507
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3100707382
Short name T161
Test name
Test status
Simulation time 2120252977 ps
CPU time 37.68 seconds
Started Jun 24 06:39:47 PM PDT 24
Finished Jun 24 06:40:27 PM PDT 24
Peak memory 245560 kb
Host smart-c547c965-ace4-4ba5-84e1-16854e6c2eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3100707382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3100707382
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.579544491
Short name T38
Test name
Test status
Simulation time 470584679159 ps
CPU time 3614.44 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 07:43:54 PM PDT 24
Peak memory 289644 kb
Host smart-b67ca3b2-1c56-4d60-a0bd-40887c883258
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579544491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.579544491
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3480545635
Short name T256
Test name
Test status
Simulation time 75224687762 ps
CPU time 5271.31 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 08:10:43 PM PDT 24
Peak memory 316932 kb
Host smart-2952b7fb-8fff-4265-af2d-2189e73dee86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480545635 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3480545635
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4262338962
Short name T96
Test name
Test status
Simulation time 133714877718 ps
CPU time 4180.53 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 07:50:08 PM PDT 24
Peak memory 288920 kb
Host smart-68f464c7-b507-4d72-8856-c194c71785e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262338962 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4262338962
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2656902222
Short name T145
Test name
Test status
Simulation time 72990867245 ps
CPU time 325.57 seconds
Started Jun 24 06:39:43 PM PDT 24
Finished Jun 24 06:45:10 PM PDT 24
Peak memory 271828 kb
Host smart-3b031c78-5c9f-46f4-8e90-b8bd0286ff7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2656902222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2656902222
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2576497387
Short name T17
Test name
Test status
Simulation time 78847008917 ps
CPU time 2170.83 seconds
Started Jun 24 06:40:40 PM PDT 24
Finished Jun 24 07:16:52 PM PDT 24
Peak memory 271972 kb
Host smart-594233e8-3c60-455a-b791-964e706c1a8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576497387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2576497387
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1040520595
Short name T3
Test name
Test status
Simulation time 635164319730 ps
CPU time 2419.92 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 07:24:55 PM PDT 24
Peak memory 289816 kb
Host smart-72371cda-0975-42cf-8884-eb430bc39aa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040520595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1040520595
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.933320164
Short name T104
Test name
Test status
Simulation time 63407020399 ps
CPU time 5321.03 seconds
Started Jun 24 06:43:30 PM PDT 24
Finished Jun 24 08:12:33 PM PDT 24
Peak memory 338592 kb
Host smart-f1c5f5b3-9161-4376-8740-0ecf4680541f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933320164 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.933320164
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2475806522
Short name T150
Test name
Test status
Simulation time 45310050426 ps
CPU time 897.47 seconds
Started Jun 24 06:39:49 PM PDT 24
Finished Jun 24 06:54:49 PM PDT 24
Peak memory 265652 kb
Host smart-e18dd84c-da87-48b7-b3e2-b0ab7fb1dd59
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475806522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2475806522
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3262731338
Short name T47
Test name
Test status
Simulation time 130561636925 ps
CPU time 1919.23 seconds
Started Jun 24 06:44:00 PM PDT 24
Finished Jun 24 07:16:24 PM PDT 24
Peak memory 289468 kb
Host smart-3fe62f11-d6f0-4cc7-bc68-2a68a8455476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262731338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3262731338
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.737353753
Short name T153
Test name
Test status
Simulation time 6067746455 ps
CPU time 256.67 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:44:00 PM PDT 24
Peak memory 273184 kb
Host smart-4ac695da-2873-473b-be1a-9c5be7ed1614
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=737353753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.737353753
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1773552679
Short name T24
Test name
Test status
Simulation time 14402556066 ps
CPU time 1324.88 seconds
Started Jun 24 06:44:17 PM PDT 24
Finished Jun 24 07:06:34 PM PDT 24
Peak memory 289496 kb
Host smart-f40b708a-d0be-4ba5-8aff-9c33cc9a485e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773552679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1773552679
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1406934274
Short name T37
Test name
Test status
Simulation time 244571169337 ps
CPU time 3490.99 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 07:40:35 PM PDT 24
Peak memory 289792 kb
Host smart-17fff4e1-8b10-4eb2-a79f-5f37ba7b8da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406934274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1406934274
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.411145544
Short name T139
Test name
Test status
Simulation time 25264101560 ps
CPU time 639.46 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:50:23 PM PDT 24
Peak memory 273816 kb
Host smart-1af60bd4-cc9f-423f-967d-7b37575140e6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411145544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.411145544
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1776381491
Short name T231
Test name
Test status
Simulation time 56376380628 ps
CPU time 655.46 seconds
Started Jun 24 06:43:44 PM PDT 24
Finished Jun 24 06:55:13 PM PDT 24
Peak memory 255408 kb
Host smart-9fc880e4-b123-404e-9284-b83be3cc1e23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776381491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1776381491
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2422963445
Short name T356
Test name
Test status
Simulation time 21853280 ps
CPU time 1.51 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:42 PM PDT 24
Peak memory 236436 kb
Host smart-4d04801e-ee44-41e8-aad3-3bc4be4e5d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2422963445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2422963445
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1371895423
Short name T136
Test name
Test status
Simulation time 4049725738 ps
CPU time 278.93 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:44:27 PM PDT 24
Peak memory 271444 kb
Host smart-e6fee64f-e1b9-4a51-b2ab-5a97ffbd0fb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1371895423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1371895423
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2403036235
Short name T33
Test name
Test status
Simulation time 13319327209 ps
CPU time 1081.28 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 07:00:09 PM PDT 24
Peak memory 283232 kb
Host smart-f2de0ba1-085d-442d-b91b-a88c493bbe1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403036235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2403036235
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3406416031
Short name T151
Test name
Test status
Simulation time 71489098988 ps
CPU time 868.47 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:53:43 PM PDT 24
Peak memory 265612 kb
Host smart-e5683bd7-9c06-411b-8e79-4a03822d8e6e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406416031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3406416031
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3148633539
Short name T34
Test name
Test status
Simulation time 1652388616 ps
CPU time 25 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 06:40:41 PM PDT 24
Peak memory 271612 kb
Host smart-d4110ea7-982d-4470-9fac-54ed544cf9a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3148633539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3148633539
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3161958463
Short name T259
Test name
Test status
Simulation time 11426916517 ps
CPU time 423.56 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:48:19 PM PDT 24
Peak memory 247584 kb
Host smart-40428027-7e08-4500-a557-340f65cd9e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161958463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3161958463
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3226453786
Short name T263
Test name
Test status
Simulation time 150120985255 ps
CPU time 2638.86 seconds
Started Jun 24 06:44:30 PM PDT 24
Finished Jun 24 07:28:33 PM PDT 24
Peak memory 281928 kb
Host smart-8a46f328-812c-498f-af1e-588f49617507
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226453786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3226453786
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2161944077
Short name T141
Test name
Test status
Simulation time 17580340302 ps
CPU time 1262.77 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 07:00:55 PM PDT 24
Peak memory 265812 kb
Host smart-a9bd0c80-5287-4a17-b0f9-17772ba98d7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161944077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2161944077
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1528084817
Short name T302
Test name
Test status
Simulation time 45126209201 ps
CPU time 478.92 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 06:50:49 PM PDT 24
Peak memory 248384 kb
Host smart-a978cdb1-e070-4431-a989-644655438a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528084817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1528084817
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3632231924
Short name T72
Test name
Test status
Simulation time 33672611472 ps
CPU time 2074.76 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 07:17:00 PM PDT 24
Peak memory 286516 kb
Host smart-3e4fc931-6b47-4f13-8d0e-ba5f1794425c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632231924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3632231924
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.240649427
Short name T158
Test name
Test status
Simulation time 2738534658 ps
CPU time 171.5 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:42:40 PM PDT 24
Peak memory 257464 kb
Host smart-6ed519c8-9bca-45e7-8180-23cc9ba711f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=240649427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.240649427
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4050937032
Short name T310
Test name
Test status
Simulation time 217211446766 ps
CPU time 2855.5 seconds
Started Jun 24 06:44:18 PM PDT 24
Finished Jun 24 07:32:05 PM PDT 24
Peak memory 289456 kb
Host smart-b547d8d9-1e47-4b01-9f91-2297921846ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050937032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4050937032
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.891238227
Short name T319
Test name
Test status
Simulation time 16090537874 ps
CPU time 1452.95 seconds
Started Jun 24 06:42:07 PM PDT 24
Finished Jun 24 07:06:22 PM PDT 24
Peak memory 281936 kb
Host smart-155c132c-dbae-49a6-ae70-331f4dddad76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891238227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.891238227
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1401903485
Short name T239
Test name
Test status
Simulation time 288794122949 ps
CPU time 4647.7 seconds
Started Jun 24 06:41:03 PM PDT 24
Finished Jun 24 07:58:41 PM PDT 24
Peak memory 306536 kb
Host smart-a4897132-8a6e-4626-ae42-2a09527bae62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401903485 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1401903485
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2501113056
Short name T312
Test name
Test status
Simulation time 8863940567 ps
CPU time 379.46 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 06:50:34 PM PDT 24
Peak memory 247584 kb
Host smart-6c867112-eec6-406a-95b4-625ab822d53d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501113056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2501113056
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3782626911
Short name T154
Test name
Test status
Simulation time 8728812351 ps
CPU time 543.61 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:48:52 PM PDT 24
Peak memory 265756 kb
Host smart-52bf9553-dfe8-482f-bca7-cc355f15ca7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782626911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3782626911
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3641904632
Short name T56
Test name
Test status
Simulation time 109049973056 ps
CPU time 2044.84 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 07:18:40 PM PDT 24
Peak memory 286080 kb
Host smart-771b3a46-526f-454c-86f0-f71d50001abb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641904632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3641904632
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1396506182
Short name T131
Test name
Test status
Simulation time 6095151084 ps
CPU time 510.78 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:48:14 PM PDT 24
Peak memory 265632 kb
Host smart-d5c3beda-ce12-4040-afd9-6ba6b7e71d00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396506182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1396506182
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3909836969
Short name T58
Test name
Test status
Simulation time 199521567754 ps
CPU time 3229.93 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 07:35:02 PM PDT 24
Peak memory 304336 kb
Host smart-b9c15076-dae8-48b0-8e10-f66e5e125801
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909836969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3909836969
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4224185476
Short name T144
Test name
Test status
Simulation time 9099558914 ps
CPU time 696.43 seconds
Started Jun 24 06:39:09 PM PDT 24
Finished Jun 24 06:50:50 PM PDT 24
Peak memory 265592 kb
Host smart-d017a6d6-ec88-4d07-99ff-55c5bcfdea7d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224185476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4224185476
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3891278720
Short name T351
Test name
Test status
Simulation time 15482754 ps
CPU time 1.6 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:39:54 PM PDT 24
Peak memory 237372 kb
Host smart-0af670c1-1eb4-4b07-8344-aa249916a7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3891278720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3891278720
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1680682873
Short name T323
Test name
Test status
Simulation time 9294789763 ps
CPU time 356.99 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:48:50 PM PDT 24
Peak memory 248836 kb
Host smart-63837642-6844-4c4c-aa94-8b8e92492aa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680682873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1680682873
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2788878517
Short name T258
Test name
Test status
Simulation time 61896195671 ps
CPU time 1714.94 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 07:11:01 PM PDT 24
Peak memory 290116 kb
Host smart-5eca05d7-bc28-41dc-b446-9d801d4ffd7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788878517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2788878517
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.552422405
Short name T1
Test name
Test status
Simulation time 1562671619 ps
CPU time 119.85 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:44:27 PM PDT 24
Peak memory 257304 kb
Host smart-c2e072cb-5614-42dd-a044-07f0d744769a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552422405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.552422405
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.300360166
Short name T15
Test name
Test status
Simulation time 158816017633 ps
CPU time 2387.77 seconds
Started Jun 24 06:41:17 PM PDT 24
Finished Jun 24 07:21:09 PM PDT 24
Peak memory 290040 kb
Host smart-904f4ae5-8067-4517-ab14-86e914764685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300360166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.300360166
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3974163137
Short name T304
Test name
Test status
Simulation time 21987129219 ps
CPU time 448.91 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:48:33 PM PDT 24
Peak memory 248468 kb
Host smart-1b83f0a8-5c97-4364-b494-b120d699e423
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974163137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3974163137
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.19443065
Short name T291
Test name
Test status
Simulation time 1373568702 ps
CPU time 47.23 seconds
Started Jun 24 06:42:28 PM PDT 24
Finished Jun 24 06:43:17 PM PDT 24
Peak memory 249392 kb
Host smart-e7ef5daa-dda8-42a2-8f73-278b0da49922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.19443065
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.715097637
Short name T157
Test name
Test status
Simulation time 3275694383 ps
CPU time 104.48 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:41:34 PM PDT 24
Peak memory 265656 kb
Host smart-63428be6-f01f-475f-9375-a471b8f62722
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=715097637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.715097637
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4156773233
Short name T169
Test name
Test status
Simulation time 58072094 ps
CPU time 4.51 seconds
Started Jun 24 06:39:09 PM PDT 24
Finished Jun 24 06:39:18 PM PDT 24
Peak memory 237436 kb
Host smart-553146a6-cc8c-4a2f-ba23-28e598c63c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4156773233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4156773233
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.795901849
Short name T342
Test name
Test status
Simulation time 101595471198 ps
CPU time 2940.75 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 07:29:17 PM PDT 24
Peak memory 289916 kb
Host smart-f85203dc-1abd-4a43-a3fc-e72b562104bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795901849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.795901849
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1657953991
Short name T123
Test name
Test status
Simulation time 538826405623 ps
CPU time 7604.64 seconds
Started Jun 24 06:41:21 PM PDT 24
Finished Jun 24 08:48:08 PM PDT 24
Peak memory 322988 kb
Host smart-8bdf30e8-6489-43a6-b7d6-c6fe5c55197f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657953991 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1657953991
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2367367292
Short name T307
Test name
Test status
Simulation time 33590310602 ps
CPU time 1818.16 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 07:14:32 PM PDT 24
Peak memory 273716 kb
Host smart-ae461003-9127-4ad5-81bf-29986797f7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367367292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2367367292
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2000554350
Short name T179
Test name
Test status
Simulation time 2506537332 ps
CPU time 43.48 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:40:24 PM PDT 24
Peak memory 237652 kb
Host smart-852d33f4-0e94-4ee0-9bf5-84a510edb6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2000554350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2000554350
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1777358792
Short name T368
Test name
Test status
Simulation time 14140196542 ps
CPU time 458.93 seconds
Started Jun 24 06:39:24 PM PDT 24
Finished Jun 24 06:47:04 PM PDT 24
Peak memory 265644 kb
Host smart-e3e103c6-cc9c-421e-bc1a-f410d8a00a7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777358792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1777358792
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2123983282
Short name T214
Test name
Test status
Simulation time 62274154 ps
CPU time 3.27 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:40:15 PM PDT 24
Peak memory 249276 kb
Host smart-d39cbfa3-1952-468f-aee3-2911d656e233
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2123983282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2123983282
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2641054559
Short name T212
Test name
Test status
Simulation time 60301900 ps
CPU time 3.42 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:04 PM PDT 24
Peak memory 249276 kb
Host smart-4dc120cb-9b0e-4e7d-8c4c-52fa54347da5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2641054559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2641054559
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1863281953
Short name T218
Test name
Test status
Simulation time 517978206 ps
CPU time 4.07 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:10 PM PDT 24
Peak memory 249276 kb
Host smart-6c00daef-7630-4544-a744-89eab028f058
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1863281953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1863281953
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.528898668
Short name T215
Test name
Test status
Simulation time 66976526 ps
CPU time 2.87 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:12 PM PDT 24
Peak memory 249180 kb
Host smart-7be4f5a0-c33b-422c-b414-9c248be4bc26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=528898668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.528898668
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3216546719
Short name T734
Test name
Test status
Simulation time 11850908 ps
CPU time 1.38 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 237352 kb
Host smart-94b741ab-52aa-4e2e-a9b2-371c4362f396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216546719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3216546719
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.482286992
Short name T313
Test name
Test status
Simulation time 38482992948 ps
CPU time 444.33 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 06:47:40 PM PDT 24
Peak memory 248836 kb
Host smart-22b44f3f-50e1-46f3-aff7-5a2ca270970d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482286992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.482286992
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.742743445
Short name T266
Test name
Test status
Simulation time 50140322379 ps
CPU time 1553.68 seconds
Started Jun 24 06:40:55 PM PDT 24
Finished Jun 24 07:06:57 PM PDT 24
Peak memory 272844 kb
Host smart-e8f1fd64-5e7b-4967-ab61-9c30ce9926a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742743445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.742743445
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4106035178
Short name T84
Test name
Test status
Simulation time 135591266 ps
CPU time 9.87 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:19 PM PDT 24
Peak memory 249124 kb
Host smart-52fb0ea8-568c-4495-86ec-c91752366191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41060
35178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4106035178
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1136107553
Short name T344
Test name
Test status
Simulation time 108975633688 ps
CPU time 1114.25 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:59:53 PM PDT 24
Peak memory 281936 kb
Host smart-73fd7386-500f-4fe0-9533-7980c7d8a30c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136107553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1136107553
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1298185380
Short name T280
Test name
Test status
Simulation time 724212760 ps
CPU time 45.51 seconds
Started Jun 24 06:41:44 PM PDT 24
Finished Jun 24 06:42:30 PM PDT 24
Peak memory 249096 kb
Host smart-7574a0f1-1682-4de3-8e9d-eeef0df1a394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
85380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1298185380
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.910105754
Short name T73
Test name
Test status
Simulation time 47929133700 ps
CPU time 1189.36 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 07:02:14 PM PDT 24
Peak memory 286632 kb
Host smart-e4bdb10c-beed-4ed2-81b9-e9517f22af52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910105754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.910105754
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3399066660
Short name T148
Test name
Test status
Simulation time 4041112342 ps
CPU time 309.92 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:44:59 PM PDT 24
Peak memory 271896 kb
Host smart-0a3309f5-81b6-4b05-9ed3-e6b54e325d67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3399066660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3399066660
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1872471607
Short name T152
Test name
Test status
Simulation time 18559575885 ps
CPU time 372.46 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:45:35 PM PDT 24
Peak memory 265680 kb
Host smart-eadb1296-f675-42b2-953f-ec49d09a0368
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1872471607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1872471607
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2996712320
Short name T177
Test name
Test status
Simulation time 4738091113 ps
CPU time 77.8 seconds
Started Jun 24 06:39:14 PM PDT 24
Finished Jun 24 06:40:39 PM PDT 24
Peak memory 240108 kb
Host smart-ab37d632-692f-49f4-8f13-af4faef9ca08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2996712320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2996712320
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3783520859
Short name T27
Test name
Test status
Simulation time 113545017933 ps
CPU time 2809.49 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 07:28:01 PM PDT 24
Peak memory 322388 kb
Host smart-f4cf44ec-caf2-4035-ba1f-4df175c337a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783520859 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3783520859
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2662876361
Short name T314
Test name
Test status
Simulation time 6950113567 ps
CPU time 271.88 seconds
Started Jun 24 06:39:59 PM PDT 24
Finished Jun 24 06:44:33 PM PDT 24
Peak memory 248728 kb
Host smart-2376c93c-a06b-4885-b829-30453ae99883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662876361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2662876361
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.211367864
Short name T292
Test name
Test status
Simulation time 113253530851 ps
CPU time 2059 seconds
Started Jun 24 06:39:55 PM PDT 24
Finished Jun 24 07:14:15 PM PDT 24
Peak memory 289948 kb
Host smart-ea6d3dfb-114b-4a6d-b782-f0ac3a98432c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211367864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.211367864
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.261590191
Short name T336
Test name
Test status
Simulation time 201576628161 ps
CPU time 1590.68 seconds
Started Jun 24 06:40:55 PM PDT 24
Finished Jun 24 07:07:31 PM PDT 24
Peak memory 273752 kb
Host smart-a07b2f10-31f6-44a6-a757-c2e82b5899bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261590191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.261590191
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.861969131
Short name T107
Test name
Test status
Simulation time 442206884 ps
CPU time 28.11 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:36 PM PDT 24
Peak memory 257280 kb
Host smart-cb0a5989-7671-404a-aa16-48404251897c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86196
9131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.861969131
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1368574013
Short name T32
Test name
Test status
Simulation time 77619732553 ps
CPU time 2515.42 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:23:10 PM PDT 24
Peak memory 289428 kb
Host smart-7cbb19e6-bb49-45b0-aa33-1f36fbcc2b31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368574013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1368574013
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2575832699
Short name T97
Test name
Test status
Simulation time 209367785885 ps
CPU time 3318.21 seconds
Started Jun 24 06:41:21 PM PDT 24
Finished Jun 24 07:36:41 PM PDT 24
Peak memory 303452 kb
Host smart-6437b980-53d0-4e8a-b490-641c0f30645a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575832699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2575832699
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1586414858
Short name T274
Test name
Test status
Simulation time 31063889268 ps
CPU time 1650.44 seconds
Started Jun 24 06:41:45 PM PDT 24
Finished Jun 24 07:09:17 PM PDT 24
Peak memory 303048 kb
Host smart-b1a42b27-74d3-4b8a-8abd-9f18a8ee7f94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586414858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1586414858
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2510912317
Short name T242
Test name
Test status
Simulation time 113967679096 ps
CPU time 1972.71 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 07:14:40 PM PDT 24
Peak memory 289632 kb
Host smart-3d269d44-f934-4787-a79f-d77ebd41edaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510912317 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2510912317
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3454260832
Short name T283
Test name
Test status
Simulation time 248008344 ps
CPU time 26.59 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:35 PM PDT 24
Peak memory 256048 kb
Host smart-32bc763f-4185-43d2-8f11-c1ce1cf8df1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34542
60832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3454260832
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1857060010
Short name T269
Test name
Test status
Simulation time 132447543723 ps
CPU time 2109.64 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 07:17:37 PM PDT 24
Peak memory 281956 kb
Host smart-97b59075-c66b-4461-86f6-9eeb43222260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857060010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1857060010
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3657707712
Short name T329
Test name
Test status
Simulation time 7461342480 ps
CPU time 159.34 seconds
Started Jun 24 06:42:29 PM PDT 24
Finished Jun 24 06:45:10 PM PDT 24
Peak memory 248400 kb
Host smart-210e79c2-921b-4958-9593-79cee8ae40a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657707712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3657707712
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3437371991
Short name T257
Test name
Test status
Simulation time 256720709 ps
CPU time 19.35 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 06:42:48 PM PDT 24
Peak memory 248160 kb
Host smart-673f89c7-31ef-4ed2-8228-bf1cfdaa541e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
71991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3437371991
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.720955088
Short name T22
Test name
Test status
Simulation time 46103699099 ps
CPU time 649.41 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 06:53:15 PM PDT 24
Peak memory 257436 kb
Host smart-6dcc75e7-156a-45de-8913-a1b52dba31ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720955088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.720955088
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.404569709
Short name T275
Test name
Test status
Simulation time 1691321963 ps
CPU time 28.9 seconds
Started Jun 24 06:42:29 PM PDT 24
Finished Jun 24 06:42:59 PM PDT 24
Peak memory 255900 kb
Host smart-df688e10-753a-42b7-85ea-9c8fb2fb03f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
9709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.404569709
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.892573274
Short name T85
Test name
Test status
Simulation time 1849415268 ps
CPU time 47.3 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:40 PM PDT 24
Peak memory 255336 kb
Host smart-6dbbaf6b-b9b7-4b6d-acca-ede44dddf17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89257
3274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.892573274
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1911155963
Short name T350
Test name
Test status
Simulation time 9893186721 ps
CPU time 722.92 seconds
Started Jun 24 06:44:53 PM PDT 24
Finished Jun 24 06:57:00 PM PDT 24
Peak memory 273664 kb
Host smart-0d38fe9c-c8a5-4435-b74a-f5a5b25fd999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911155963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1911155963
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.354998384
Short name T29
Test name
Test status
Simulation time 22074295085 ps
CPU time 377.84 seconds
Started Jun 24 06:45:09 PM PDT 24
Finished Jun 24 06:51:31 PM PDT 24
Peak memory 254940 kb
Host smart-d8cec176-16c4-4e75-91bd-ae8c734556ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354998384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.354998384
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2769753126
Short name T265
Test name
Test status
Simulation time 36705203311 ps
CPU time 1791.89 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 07:10:57 PM PDT 24
Peak memory 285676 kb
Host smart-97aafc57-cec3-4954-bcf2-79c43909ce46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769753126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2769753126
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1931673356
Short name T162
Test name
Test status
Simulation time 52719595 ps
CPU time 4.04 seconds
Started Jun 24 06:39:47 PM PDT 24
Finished Jun 24 06:39:53 PM PDT 24
Peak memory 237260 kb
Host smart-951fb657-f250-42dc-b13e-4267104e13bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1931673356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1931673356
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.799815569
Short name T132
Test name
Test status
Simulation time 7943206317 ps
CPU time 595.83 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:49:18 PM PDT 24
Peak memory 265696 kb
Host smart-7bbbdf52-b0ab-4604-bf74-15b84557ffc9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799815569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.799815569
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.71456874
Short name T168
Test name
Test status
Simulation time 54729113 ps
CPU time 4.03 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:39:44 PM PDT 24
Peak memory 237504 kb
Host smart-151d5cd3-05ad-4b95-83cc-d91519f37a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=71456874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.71456874
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3165280025
Short name T172
Test name
Test status
Simulation time 358264156 ps
CPU time 42.97 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:40:28 PM PDT 24
Peak memory 237376 kb
Host smart-c3d9cfd5-5e4e-475c-aba5-c703ecc43b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3165280025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3165280025
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2319528705
Short name T137
Test name
Test status
Simulation time 1690231140 ps
CPU time 195.41 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:42:56 PM PDT 24
Peak memory 273676 kb
Host smart-5e7d5c82-660d-44ad-bcd6-1f4126310957
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2319528705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2319528705
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1788766823
Short name T140
Test name
Test status
Simulation time 31351999403 ps
CPU time 380.49 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:45:43 PM PDT 24
Peak memory 265684 kb
Host smart-836dce69-92e6-4dd7-ad5d-cdc6c902cb00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1788766823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1788766823
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3930997491
Short name T171
Test name
Test status
Simulation time 71136499 ps
CPU time 2.85 seconds
Started Jun 24 06:39:23 PM PDT 24
Finished Jun 24 06:39:28 PM PDT 24
Peak memory 237180 kb
Host smart-61d15575-ee96-42ea-9d23-ed2824df80f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3930997491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3930997491
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2651077093
Short name T175
Test name
Test status
Simulation time 1718986119 ps
CPU time 33.39 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:40:14 PM PDT 24
Peak memory 237468 kb
Host smart-ea14859d-9f0d-4c60-92f1-2f24ef31bc82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2651077093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2651077093
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1303331616
Short name T174
Test name
Test status
Simulation time 2095440852 ps
CPU time 36.09 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:40:16 PM PDT 24
Peak memory 248976 kb
Host smart-d104ba1d-5060-4cef-ba55-78a5d0dd8204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1303331616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1303331616
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.367465923
Short name T170
Test name
Test status
Simulation time 2372700160 ps
CPU time 38.54 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:40:26 PM PDT 24
Peak memory 249036 kb
Host smart-e1771247-0ad7-452e-96c7-e6742beaad0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=367465923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.367465923
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4029209323
Short name T173
Test name
Test status
Simulation time 2254859781 ps
CPU time 41.69 seconds
Started Jun 24 06:39:49 PM PDT 24
Finished Jun 24 06:40:32 PM PDT 24
Peak memory 240812 kb
Host smart-7e0ca89a-41d4-43f1-a169-9d3987badb80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4029209323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4029209323
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2940438519
Short name T23
Test name
Test status
Simulation time 3722651273 ps
CPU time 182.13 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:43:28 PM PDT 24
Peak memory 257352 kb
Host smart-d3debca5-4c67-454d-9640-edd0a9334e63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940438519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2940438519
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3679416595
Short name T770
Test name
Test status
Simulation time 537269640 ps
CPU time 73.84 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:40:28 PM PDT 24
Peak memory 237276 kb
Host smart-5574460b-4ba5-4144-88fd-11eb31d062a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3679416595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3679416595
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.281730349
Short name T813
Test name
Test status
Simulation time 1669694387 ps
CPU time 227.49 seconds
Started Jun 24 06:39:11 PM PDT 24
Finished Jun 24 06:43:04 PM PDT 24
Peak memory 237280 kb
Host smart-999ab7b8-f907-45a3-8a91-3ace14efca67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=281730349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.281730349
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.993592664
Short name T753
Test name
Test status
Simulation time 202515068 ps
CPU time 9.74 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:39:25 PM PDT 24
Peak memory 240696 kb
Host smart-1bef7160-54b7-4763-a851-9d5c5f5d3357
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993592664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.993592664
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3506116776
Short name T790
Test name
Test status
Simulation time 36635482 ps
CPU time 5.07 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:24 PM PDT 24
Peak memory 256156 kb
Host smart-27db6fcb-3625-4b97-bf14-f6f4353c4b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506116776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3506116776
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2655313642
Short name T361
Test name
Test status
Simulation time 249191054 ps
CPU time 5.14 seconds
Started Jun 24 06:39:11 PM PDT 24
Finished Jun 24 06:39:23 PM PDT 24
Peak memory 237296 kb
Host smart-83ecb6f5-84ee-4f1e-8135-d3e170dec8eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2655313642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2655313642
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.424660470
Short name T818
Test name
Test status
Simulation time 28425739 ps
CPU time 2.34 seconds
Started Jun 24 06:39:09 PM PDT 24
Finished Jun 24 06:39:16 PM PDT 24
Peak memory 237360 kb
Host smart-bdb59105-c593-4740-bc2b-2066accfb482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=424660470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.424660470
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1884478206
Short name T756
Test name
Test status
Simulation time 326434580 ps
CPU time 23.15 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:39:39 PM PDT 24
Peak memory 245536 kb
Host smart-d65b5d91-e784-4a32-8ece-f7486f9064f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884478206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1884478206
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2958878723
Short name T766
Test name
Test status
Simulation time 2133628599 ps
CPU time 146.16 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:41:40 PM PDT 24
Peak memory 265820 kb
Host smart-e4c17eb1-2feb-4a9c-b4d8-a461f0b34732
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2958878723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2958878723
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3902784059
Short name T715
Test name
Test status
Simulation time 268161198 ps
CPU time 8.03 seconds
Started Jun 24 06:39:11 PM PDT 24
Finished Jun 24 06:39:24 PM PDT 24
Peak memory 248596 kb
Host smart-726182a5-1233-4c39-a742-6c50991a3260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902784059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3902784059
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1541744607
Short name T195
Test name
Test status
Simulation time 1682478144 ps
CPU time 100.08 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:40:55 PM PDT 24
Peak memory 237352 kb
Host smart-4c339508-2ee4-4de1-b2ad-7d5801df780d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1541744607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1541744607
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2305909487
Short name T733
Test name
Test status
Simulation time 17438272486 ps
CPU time 516.93 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:47:59 PM PDT 24
Peak memory 237288 kb
Host smart-3b0edd3f-c57b-46ba-9409-24aeb246a9ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2305909487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2305909487
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.993408494
Short name T740
Test name
Test status
Simulation time 119146795 ps
CPU time 5.03 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:24 PM PDT 24
Peak memory 240708 kb
Host smart-18a172d9-f405-43bd-a8f4-ff5fe9684ddb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993408494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.993408494
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1599151770
Short name T759
Test name
Test status
Simulation time 32993820 ps
CPU time 4.75 seconds
Started Jun 24 06:39:14 PM PDT 24
Finished Jun 24 06:39:26 PM PDT 24
Peak memory 240056 kb
Host smart-4d7653b5-e15d-41df-b591-c3a554d3b5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599151770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1599151770
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2875804902
Short name T197
Test name
Test status
Simulation time 369734000 ps
CPU time 8.86 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:39:30 PM PDT 24
Peak memory 237272 kb
Host smart-30b98304-1ab0-4ecb-8dde-a325744eebff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2875804902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2875804902
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1664313656
Short name T761
Test name
Test status
Simulation time 11760617 ps
CPU time 1.51 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:39:24 PM PDT 24
Peak memory 236344 kb
Host smart-7ca0667f-1744-4012-ad7f-367c8a28f207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664313656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1664313656
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.282156205
Short name T752
Test name
Test status
Simulation time 3815862607 ps
CPU time 38.77 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:57 PM PDT 24
Peak memory 249028 kb
Host smart-a3154f80-16b2-45c8-89a2-863f6ce155ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=282156205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.282156205
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1655566401
Short name T134
Test name
Test status
Simulation time 3892066251 ps
CPU time 306.1 seconds
Started Jun 24 06:39:10 PM PDT 24
Finished Jun 24 06:44:21 PM PDT 24
Peak memory 272032 kb
Host smart-f9acf6c6-e63d-45e9-8546-3416a7693adf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1655566401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1655566401
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4201104565
Short name T794
Test name
Test status
Simulation time 125748375 ps
CPU time 8.55 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:27 PM PDT 24
Peak memory 249016 kb
Host smart-a371729c-75ef-4b2f-aa39-2228166b135d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201104565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4201104565
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1111746270
Short name T805
Test name
Test status
Simulation time 53300346 ps
CPU time 2.74 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:21 PM PDT 24
Peak memory 237348 kb
Host smart-003d25cb-bcc9-49f1-be3a-c67cee7d97d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1111746270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1111746270
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2083645149
Short name T746
Test name
Test status
Simulation time 34368657 ps
CPU time 6.18 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:39:47 PM PDT 24
Peak memory 241868 kb
Host smart-abc8125c-a45e-43b1-a3f4-fdac5ce4865f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083645149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2083645149
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3298048482
Short name T735
Test name
Test status
Simulation time 62648603 ps
CPU time 3.71 seconds
Started Jun 24 06:39:29 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 237224 kb
Host smart-9b32853f-8445-4cb3-8275-4634d72d040c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3298048482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3298048482
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3377107308
Short name T762
Test name
Test status
Simulation time 11985358 ps
CPU time 1.54 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:39:35 PM PDT 24
Peak memory 236348 kb
Host smart-59cbc19a-9b81-450f-b41b-f4e08352e30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3377107308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3377107308
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1576985482
Short name T757
Test name
Test status
Simulation time 385890864 ps
CPU time 12.71 seconds
Started Jun 24 06:39:35 PM PDT 24
Finished Jun 24 06:39:50 PM PDT 24
Peak memory 248976 kb
Host smart-25905320-9105-4f04-b4e5-adbeb2901000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1576985482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1576985482
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3994676081
Short name T160
Test name
Test status
Simulation time 6658226868 ps
CPU time 189.87 seconds
Started Jun 24 06:39:30 PM PDT 24
Finished Jun 24 06:42:40 PM PDT 24
Peak memory 265676 kb
Host smart-221f69c0-bdf3-4c74-b580-0fca44d71cb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3994676081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3994676081
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1546336623
Short name T371
Test name
Test status
Simulation time 8170968429 ps
CPU time 537.44 seconds
Started Jun 24 06:39:32 PM PDT 24
Finished Jun 24 06:48:31 PM PDT 24
Peak memory 268952 kb
Host smart-327f4984-80fd-4e22-a4c8-24ec1f54d0db
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546336623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1546336623
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1702413823
Short name T732
Test name
Test status
Simulation time 232865095 ps
CPU time 7.84 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:39:42 PM PDT 24
Peak memory 248656 kb
Host smart-89fe230d-abd2-476b-bcd8-ba3d8571530b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1702413823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1702413823
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.612711656
Short name T775
Test name
Test status
Simulation time 133861427 ps
CPU time 2.35 seconds
Started Jun 24 06:39:31 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 236268 kb
Host smart-38a171df-209d-4d10-847b-7c185f03b429
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=612711656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.612711656
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2255467749
Short name T771
Test name
Test status
Simulation time 510764093 ps
CPU time 8.89 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 237820 kb
Host smart-d6c98168-5442-457e-8e0d-d9d79fd02d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255467749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2255467749
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2158183705
Short name T786
Test name
Test status
Simulation time 51689280 ps
CPU time 4.59 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 237268 kb
Host smart-51d3e346-e2e8-4f06-9790-e138d311acf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2158183705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2158183705
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1102288872
Short name T821
Test name
Test status
Simulation time 636268093 ps
CPU time 37.05 seconds
Started Jun 24 06:39:35 PM PDT 24
Finished Jun 24 06:40:16 PM PDT 24
Peak memory 248972 kb
Host smart-a31806cd-bd78-4e14-abfb-b7ca107a9a3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1102288872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1102288872
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3370536681
Short name T149
Test name
Test status
Simulation time 3247352057 ps
CPU time 199.63 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:42:59 PM PDT 24
Peak memory 265680 kb
Host smart-b8463a13-dc47-4686-aeab-64b3179971cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3370536681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3370536681
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2369436349
Short name T370
Test name
Test status
Simulation time 16755207663 ps
CPU time 1023.16 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:56:42 PM PDT 24
Peak memory 273636 kb
Host smart-f77d740d-31ef-48f8-99e5-828469b1582b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369436349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2369436349
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.404278730
Short name T712
Test name
Test status
Simulation time 577691436 ps
CPU time 11.1 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:39:52 PM PDT 24
Peak memory 249000 kb
Host smart-5ae721ed-66cf-48c8-8aa6-5202579ae3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404278730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.404278730
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3040899332
Short name T815
Test name
Test status
Simulation time 371237256 ps
CPU time 7.94 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 240728 kb
Host smart-22c3fa13-2531-461a-b08d-d064f14721cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040899332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3040899332
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.158656062
Short name T720
Test name
Test status
Simulation time 68966946 ps
CPU time 2.96 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:43 PM PDT 24
Peak memory 236340 kb
Host smart-e65bac04-b0f2-4ed2-960f-fb50121569d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=158656062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.158656062
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2995712416
Short name T784
Test name
Test status
Simulation time 9355378 ps
CPU time 1.25 seconds
Started Jun 24 06:39:43 PM PDT 24
Finished Jun 24 06:39:46 PM PDT 24
Peak memory 235400 kb
Host smart-19e0dde5-a52b-4cf7-a349-92749306b595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2995712416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2995712416
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.371023375
Short name T765
Test name
Test status
Simulation time 321548980 ps
CPU time 21.33 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:40:05 PM PDT 24
Peak memory 244588 kb
Host smart-784987cf-f54e-4e6f-b1b8-dad230e445a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=371023375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.371023375
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.242508830
Short name T143
Test name
Test status
Simulation time 17038118555 ps
CPU time 818.03 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:53:19 PM PDT 24
Peak memory 266100 kb
Host smart-f63d6e0f-ae38-4f52-8cd6-45d658584645
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242508830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.242508830
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1156963115
Short name T713
Test name
Test status
Simulation time 367538832 ps
CPU time 10.6 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:51 PM PDT 24
Peak memory 249028 kb
Host smart-ad0e48d7-fa53-43d9-9b21-4eb4fe40d1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1156963115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1156963115
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1791510906
Short name T359
Test name
Test status
Simulation time 519168920 ps
CPU time 11.26 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:40:00 PM PDT 24
Peak memory 252040 kb
Host smart-067fbbde-6edb-4d69-83ce-b0983327cd7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791510906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1791510906
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3946549847
Short name T826
Test name
Test status
Simulation time 76684992 ps
CPU time 3.2 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:39:51 PM PDT 24
Peak memory 237256 kb
Host smart-1b7be7a3-da6d-45ab-a3ad-95faf9dd8337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3946549847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3946549847
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3918979333
Short name T793
Test name
Test status
Simulation time 1941576833 ps
CPU time 21.67 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 244616 kb
Host smart-d2db46cc-0461-4161-b592-be2178756247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3918979333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3918979333
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1201089199
Short name T133
Test name
Test status
Simulation time 7317490759 ps
CPU time 292.22 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:44:36 PM PDT 24
Peak memory 265652 kb
Host smart-35099de5-2eed-4725-a214-0b7a14c3f945
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1201089199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1201089199
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1931568450
Short name T366
Test name
Test status
Simulation time 9196931893 ps
CPU time 704.76 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:51:26 PM PDT 24
Peak memory 265764 kb
Host smart-f0cca8fc-16d7-435a-bba5-2cf9e46ba60c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931568450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1931568450
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2932033560
Short name T749
Test name
Test status
Simulation time 303407478 ps
CPU time 19.15 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:40:02 PM PDT 24
Peak memory 254112 kb
Host smart-81de3069-4d26-4cea-8ec4-dd7faaff92a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2932033560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2932033560
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.866609690
Short name T163
Test name
Test status
Simulation time 1082361837 ps
CPU time 26.24 seconds
Started Jun 24 06:39:43 PM PDT 24
Finished Jun 24 06:40:11 PM PDT 24
Peak memory 240724 kb
Host smart-073c03a0-8b4e-4221-89c9-1b70fddc77de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=866609690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.866609690
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2332171049
Short name T372
Test name
Test status
Simulation time 30155713 ps
CPU time 5.26 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:39:52 PM PDT 24
Peak memory 240508 kb
Host smart-a72ee689-89f0-48f0-8c3e-3046c3a35f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332171049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2332171049
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1599314791
Short name T193
Test name
Test status
Simulation time 494461047 ps
CPU time 4.63 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:39:51 PM PDT 24
Peak memory 236344 kb
Host smart-976b593b-40a1-4549-80c1-2e41d389e883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1599314791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1599314791
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2983984628
Short name T830
Test name
Test status
Simulation time 7958187 ps
CPU time 1.46 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:39:49 PM PDT 24
Peak memory 236412 kb
Host smart-96738a34-ee97-406e-a6a8-98da23dd4f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983984628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2983984628
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1956272349
Short name T803
Test name
Test status
Simulation time 87692172 ps
CPU time 11.14 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:39:59 PM PDT 24
Peak memory 248824 kb
Host smart-614a4093-54e9-4fc4-b1c7-c34b42ccfcb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1956272349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1956272349
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3699692293
Short name T369
Test name
Test status
Simulation time 18885845962 ps
CPU time 301.6 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:44:50 PM PDT 24
Peak memory 270572 kb
Host smart-a9f6448c-9a71-43a8-8717-528225225597
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699692293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3699692293
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1398164264
Short name T774
Test name
Test status
Simulation time 402329969 ps
CPU time 6.88 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:39:54 PM PDT 24
Peak memory 248632 kb
Host smart-9d0d9b2e-2ba7-48cf-81d0-415d188f766b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1398164264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1398164264
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1369983084
Short name T362
Test name
Test status
Simulation time 175697795 ps
CPU time 11.25 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:40:00 PM PDT 24
Peak memory 251296 kb
Host smart-93d25de4-5dd2-40af-9580-c7d176ec747b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369983084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1369983084
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2407531450
Short name T728
Test name
Test status
Simulation time 186773514 ps
CPU time 4.74 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:39:50 PM PDT 24
Peak memory 237356 kb
Host smart-4195aaaa-70d1-4ef8-81cd-71d36bb2e008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2407531450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2407531450
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2599287877
Short name T792
Test name
Test status
Simulation time 6476748 ps
CPU time 1.55 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:39:49 PM PDT 24
Peak memory 237352 kb
Host smart-ac8c971d-2352-4c8d-87ee-381d572b89f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2599287877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2599287877
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.30678353
Short name T726
Test name
Test status
Simulation time 890748918 ps
CPU time 18.34 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:40:04 PM PDT 24
Peak memory 248980 kb
Host smart-c1254220-b72d-40b1-a5f6-65dff4f6c0d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=30678353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outs
tanding.30678353
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2071315159
Short name T718
Test name
Test status
Simulation time 368886882 ps
CPU time 13.49 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:40:00 PM PDT 24
Peak memory 249028 kb
Host smart-d848fd69-542b-4b37-85c5-3500f3a36428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2071315159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2071315159
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1488543186
Short name T725
Test name
Test status
Simulation time 232738020 ps
CPU time 4.69 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 242748 kb
Host smart-cf633e20-9ae2-45d9-84e8-04b01bcd9b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488543186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1488543186
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3312167607
Short name T796
Test name
Test status
Simulation time 100034095 ps
CPU time 3.37 seconds
Started Jun 24 06:39:43 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 237284 kb
Host smart-8f46db00-6eee-44af-96fb-376e53b26224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3312167607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3312167607
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.59564671
Short name T787
Test name
Test status
Simulation time 11945402 ps
CPU time 1.43 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:39:53 PM PDT 24
Peak memory 237340 kb
Host smart-8fd8a626-cfa7-4eb1-b2c2-27a51df5f1ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=59564671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.59564671
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3619760260
Short name T764
Test name
Test status
Simulation time 336719233 ps
CPU time 14.19 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 245544 kb
Host smart-90dadcb3-33fa-4f4c-8a88-45fc8ad42d86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3619760260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3619760260
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3789025384
Short name T243
Test name
Test status
Simulation time 341381063 ps
CPU time 26.09 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:40:13 PM PDT 24
Peak memory 249036 kb
Host smart-9636077e-2816-499e-9fd9-118501fcd301
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3789025384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3789025384
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2672628303
Short name T824
Test name
Test status
Simulation time 103170702 ps
CPU time 2.51 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:39:50 PM PDT 24
Peak memory 237428 kb
Host smart-6eef6c4f-f4aa-4f01-80af-ea15c69b5eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2672628303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2672628303
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2153744267
Short name T751
Test name
Test status
Simulation time 798349679 ps
CPU time 14.96 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:40:06 PM PDT 24
Peak memory 242108 kb
Host smart-e9356cb4-946c-430c-a2ba-0dda446fe8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153744267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2153744267
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4179939059
Short name T723
Test name
Test status
Simulation time 62324574 ps
CPU time 4.85 seconds
Started Jun 24 06:39:49 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 237288 kb
Host smart-fed23084-bb42-4283-9814-286d47fe75c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4179939059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.4179939059
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.247871525
Short name T817
Test name
Test status
Simulation time 15339669 ps
CPU time 1.34 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:39:51 PM PDT 24
Peak memory 237316 kb
Host smart-454bc621-ebf8-4675-83ed-1bba71b31f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=247871525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.247871525
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3180255206
Short name T789
Test name
Test status
Simulation time 504999199 ps
CPU time 36.83 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:40:26 PM PDT 24
Peak memory 245392 kb
Host smart-f72842a8-bca0-486b-94f7-8c2aa115a0a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3180255206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3180255206
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2726945801
Short name T777
Test name
Test status
Simulation time 951449448 ps
CPU time 21.69 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:40:12 PM PDT 24
Peak memory 248908 kb
Host smart-a05d62e8-8fb5-465d-bcf0-020510373063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726945801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2726945801
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2920723481
Short name T364
Test name
Test status
Simulation time 188432811 ps
CPU time 13.35 seconds
Started Jun 24 06:39:51 PM PDT 24
Finished Jun 24 06:40:06 PM PDT 24
Peak memory 254648 kb
Host smart-053f0997-9f48-4163-9984-4f0c558b407b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920723481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2920723481
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.140860320
Short name T785
Test name
Test status
Simulation time 314974453 ps
CPU time 5.22 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:39:55 PM PDT 24
Peak memory 237288 kb
Host smart-18096515-420b-416c-ab52-71a92086e7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=140860320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.140860320
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1435743057
Short name T800
Test name
Test status
Simulation time 16025369 ps
CPU time 1.43 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:39:53 PM PDT 24
Peak memory 236404 kb
Host smart-3982d883-5518-4865-9ee0-51fbdc981b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1435743057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1435743057
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.357637910
Short name T820
Test name
Test status
Simulation time 85236600 ps
CPU time 13.89 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:40:04 PM PDT 24
Peak memory 245560 kb
Host smart-d911086e-46ac-4bf2-adda-b4493584f664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=357637910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.357637910
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2619586331
Short name T146
Test name
Test status
Simulation time 6830431603 ps
CPU time 458.58 seconds
Started Jun 24 06:39:49 PM PDT 24
Finished Jun 24 06:47:30 PM PDT 24
Peak memory 273716 kb
Host smart-f0e1481f-12b6-4491-a454-d4d4d5454f2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2619586331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2619586331
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1737199470
Short name T367
Test name
Test status
Simulation time 5011232475 ps
CPU time 790.34 seconds
Started Jun 24 06:39:50 PM PDT 24
Finished Jun 24 06:53:02 PM PDT 24
Peak memory 272748 kb
Host smart-e7979ba1-da1d-45c9-88e6-0bee1593c8d9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737199470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1737199470
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3073410015
Short name T724
Test name
Test status
Simulation time 549564252 ps
CPU time 7.29 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:39:58 PM PDT 24
Peak memory 249244 kb
Host smart-1df4e3d2-ec0b-4428-a330-13a0c7208a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073410015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3073410015
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4249893726
Short name T167
Test name
Test status
Simulation time 3141224105 ps
CPU time 47.45 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:40:38 PM PDT 24
Peak memory 245632 kb
Host smart-e89de435-d27a-413c-8165-7c2b9930826a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4249893726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4249893726
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4179170904
Short name T808
Test name
Test status
Simulation time 68744759 ps
CPU time 4.76 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:04 PM PDT 24
Peak memory 239720 kb
Host smart-a7e2e48f-e815-4902-8934-e072cd88a291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179170904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4179170904
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.61104908
Short name T755
Test name
Test status
Simulation time 61097229 ps
CPU time 5.52 seconds
Started Jun 24 06:39:48 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 236340 kb
Host smart-5e4387d7-beb9-4549-a94b-a5cd39ee9a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=61104908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.61104908
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3158058245
Short name T807
Test name
Test status
Simulation time 2788098174 ps
CPU time 45.65 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:46 PM PDT 24
Peak memory 245608 kb
Host smart-ec0a2c0b-fe18-4a47-ae77-5f7b09438297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3158058245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3158058245
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4257590022
Short name T791
Test name
Test status
Simulation time 52681602 ps
CPU time 7.79 seconds
Started Jun 24 06:39:47 PM PDT 24
Finished Jun 24 06:39:57 PM PDT 24
Peak memory 249108 kb
Host smart-05afa5ec-94ec-40b9-bee0-be8991738497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4257590022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4257590022
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1936743892
Short name T196
Test name
Test status
Simulation time 3263293234 ps
CPU time 248.47 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:43:29 PM PDT 24
Peak memory 242012 kb
Host smart-491fcad9-86d9-45f7-a957-9c11ca9dad97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1936743892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1936743892
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1199190800
Short name T716
Test name
Test status
Simulation time 1641601428 ps
CPU time 199.12 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:42:38 PM PDT 24
Peak memory 237288 kb
Host smart-b2632290-dcf8-45f3-baf6-9fd8f14158cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1199190800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1199190800
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1482519737
Short name T739
Test name
Test status
Simulation time 250100874 ps
CPU time 9.81 seconds
Started Jun 24 06:39:14 PM PDT 24
Finished Jun 24 06:39:31 PM PDT 24
Peak memory 240728 kb
Host smart-9cc9ccdf-e107-4b18-9d15-62b13262e0c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1482519737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1482519737
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1982417630
Short name T360
Test name
Test status
Simulation time 137383357 ps
CPU time 9.84 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:39:32 PM PDT 24
Peak memory 240812 kb
Host smart-12665061-9f43-4ee6-94dd-22722f304f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982417630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1982417630
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.514565955
Short name T783
Test name
Test status
Simulation time 115910531 ps
CPU time 4.95 seconds
Started Jun 24 06:39:11 PM PDT 24
Finished Jun 24 06:39:21 PM PDT 24
Peak memory 236320 kb
Host smart-1596c6fd-4575-4035-9ee0-4d438a65a469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=514565955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.514565955
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2932108586
Short name T730
Test name
Test status
Simulation time 9707046 ps
CPU time 1.39 seconds
Started Jun 24 06:39:14 PM PDT 24
Finished Jun 24 06:39:23 PM PDT 24
Peak memory 237360 kb
Host smart-b9bd440c-6d7e-4ff3-b93e-eaf50b87c3dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2932108586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2932108586
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1940011075
Short name T802
Test name
Test status
Simulation time 3150193639 ps
CPU time 39.84 seconds
Started Jun 24 06:39:15 PM PDT 24
Finished Jun 24 06:40:02 PM PDT 24
Peak memory 249056 kb
Host smart-56e75914-b332-4e78-ae0e-54308910c869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1940011075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1940011075
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4240662523
Short name T138
Test name
Test status
Simulation time 7837616553 ps
CPU time 585.68 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:49:04 PM PDT 24
Peak memory 269508 kb
Host smart-9dc96af0-7e8c-4894-b024-937d3bf8b052
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240662523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4240662523
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2986711327
Short name T722
Test name
Test status
Simulation time 464310832 ps
CPU time 8.14 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:39:29 PM PDT 24
Peak memory 248880 kb
Host smart-ffeff83a-a7bc-44b2-bd5b-df43526fc81e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2986711327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2986711327
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2270961032
Short name T772
Test name
Test status
Simulation time 11715667 ps
CPU time 1.4 seconds
Started Jun 24 06:39:59 PM PDT 24
Finished Jun 24 06:40:03 PM PDT 24
Peak memory 235424 kb
Host smart-044d0699-7dfe-4114-b10d-646f9f3e9ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270961032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2270961032
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2396513189
Short name T801
Test name
Test status
Simulation time 17437597 ps
CPU time 1.85 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 236440 kb
Host smart-ef1759c8-4b49-46a1-865c-794322eb1cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2396513189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2396513189
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.583956560
Short name T710
Test name
Test status
Simulation time 6558245 ps
CPU time 1.56 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 237308 kb
Host smart-d0f9a733-eb42-404b-be41-66050ed22e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=583956560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.583956560
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.844857587
Short name T823
Test name
Test status
Simulation time 9125176 ps
CPU time 1.54 seconds
Started Jun 24 06:39:56 PM PDT 24
Finished Jun 24 06:39:59 PM PDT 24
Peak memory 237356 kb
Host smart-81786e74-808f-44fe-a268-94d9f639a2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844857587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.844857587
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1230011094
Short name T165
Test name
Test status
Simulation time 14441417 ps
CPU time 1.33 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:07 PM PDT 24
Peak memory 236400 kb
Host smart-033c9ce7-e5e4-4602-b1bb-ccb2ebbb99ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1230011094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1230011094
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2991231426
Short name T828
Test name
Test status
Simulation time 12583197 ps
CPU time 1.44 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:39:59 PM PDT 24
Peak memory 236328 kb
Host smart-1aed155b-adce-489a-8e13-12df84b6b1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2991231426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2991231426
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3991900736
Short name T717
Test name
Test status
Simulation time 9854181 ps
CPU time 1.53 seconds
Started Jun 24 06:39:56 PM PDT 24
Finished Jun 24 06:39:58 PM PDT 24
Peak memory 236432 kb
Host smart-c5820c5d-8e9e-4604-b880-6b0a8b7b6b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3991900736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3991900736
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1025174079
Short name T769
Test name
Test status
Simulation time 15321372 ps
CPU time 1.23 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 237232 kb
Host smart-c13dab56-5ffb-44a7-892b-5be27d5b0733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1025174079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1025174079
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2048570246
Short name T736
Test name
Test status
Simulation time 10238865 ps
CPU time 1.73 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:00 PM PDT 24
Peak memory 235408 kb
Host smart-c68231a3-d3ea-4ec3-adda-89946f1e83c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2048570246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2048570246
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.154276078
Short name T750
Test name
Test status
Simulation time 21478984 ps
CPU time 1.36 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 236440 kb
Host smart-7febf9a8-6a84-4c13-b759-a641743c9b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=154276078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.154276078
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1353512817
Short name T731
Test name
Test status
Simulation time 1071209384 ps
CPU time 143.8 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:41:58 PM PDT 24
Peak memory 240656 kb
Host smart-45314e38-b3f5-40df-a9a7-73106033ac27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1353512817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1353512817
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3419769978
Short name T748
Test name
Test status
Simulation time 4473166177 ps
CPU time 252.72 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:43:32 PM PDT 24
Peak memory 240772 kb
Host smart-e71b166e-126d-4722-a866-f302e69858c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3419769978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3419769978
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1789729593
Short name T711
Test name
Test status
Simulation time 70748651 ps
CPU time 5.98 seconds
Started Jun 24 06:39:11 PM PDT 24
Finished Jun 24 06:39:24 PM PDT 24
Peak memory 240716 kb
Host smart-ca928b1a-8387-4603-8bf1-2a7f02833884
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1789729593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1789729593
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.23339562
Short name T729
Test name
Test status
Simulation time 158974963 ps
CPU time 11.02 seconds
Started Jun 24 06:39:31 PM PDT 24
Finished Jun 24 06:39:43 PM PDT 24
Peak memory 240804 kb
Host smart-c74d9e9a-c1f6-46c6-8a4a-3a74724561f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23339562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.alert_handler_csr_mem_rw_with_rand_reset.23339562
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3288964842
Short name T781
Test name
Test status
Simulation time 469070848 ps
CPU time 9.89 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:39:31 PM PDT 24
Peak memory 237276 kb
Host smart-cefb6c0c-01f1-40c8-8cb1-6855ff45480b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3288964842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3288964842
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.692572461
Short name T352
Test name
Test status
Simulation time 14848096 ps
CPU time 1.37 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:39:21 PM PDT 24
Peak memory 236360 kb
Host smart-c4b2088e-1c85-4347-9f7e-b857bc1faecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=692572461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.692572461
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2684389729
Short name T754
Test name
Test status
Simulation time 633575833 ps
CPU time 41.9 seconds
Started Jun 24 06:39:29 PM PDT 24
Finished Jun 24 06:40:12 PM PDT 24
Peak memory 248980 kb
Host smart-ba5d5488-feaf-4eaa-bfce-3a888cb86f9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2684389729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2684389729
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2545160824
Short name T747
Test name
Test status
Simulation time 177199106 ps
CPU time 13.35 seconds
Started Jun 24 06:39:13 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 248556 kb
Host smart-6a32f780-a296-4e56-8cc6-c9aac6ff1ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545160824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2545160824
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3687509208
Short name T180
Test name
Test status
Simulation time 69688081 ps
CPU time 2.31 seconds
Started Jun 24 06:39:12 PM PDT 24
Finished Jun 24 06:39:22 PM PDT 24
Peak memory 237372 kb
Host smart-77aea1dc-069f-4be3-b20e-e477103fbc04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3687509208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3687509208
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1961597789
Short name T768
Test name
Test status
Simulation time 14944287 ps
CPU time 1.33 seconds
Started Jun 24 06:40:02 PM PDT 24
Finished Jun 24 06:40:05 PM PDT 24
Peak memory 236264 kb
Host smart-7bfa6b4e-d302-49e7-b589-378338cd0410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1961597789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1961597789
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2200704753
Short name T780
Test name
Test status
Simulation time 26904576 ps
CPU time 1.58 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:06 PM PDT 24
Peak memory 237328 kb
Host smart-0d1ff57b-b989-486b-8c93-d6062eb821e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2200704753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2200704753
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2565413986
Short name T745
Test name
Test status
Simulation time 11367246 ps
CPU time 1.29 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 237348 kb
Host smart-b4eef232-ac7c-4adb-92aa-de2282ca5bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2565413986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2565413986
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.283828052
Short name T737
Test name
Test status
Simulation time 14182048 ps
CPU time 1.74 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:07 PM PDT 24
Peak memory 235376 kb
Host smart-8416ce12-d194-48f4-bd46-3ffa16619632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=283828052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.283828052
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1104467002
Short name T358
Test name
Test status
Simulation time 17089500 ps
CPU time 1.47 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:02 PM PDT 24
Peak memory 237340 kb
Host smart-b42d217b-9416-4f97-bedd-145a030e0b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1104467002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1104467002
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.511981010
Short name T829
Test name
Test status
Simulation time 14931061 ps
CPU time 1.24 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:06 PM PDT 24
Peak memory 235408 kb
Host smart-16386678-b5c4-44c4-ad39-e8e7bb062808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=511981010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.511981010
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3628264736
Short name T164
Test name
Test status
Simulation time 6833392 ps
CPU time 1.4 seconds
Started Jun 24 06:40:05 PM PDT 24
Finished Jun 24 06:40:09 PM PDT 24
Peak memory 236364 kb
Host smart-ae02bfb8-33e2-4264-98d1-e1915afbc594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3628264736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3628264736
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.388132654
Short name T763
Test name
Test status
Simulation time 20359259 ps
CPU time 1.44 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:40:13 PM PDT 24
Peak memory 237364 kb
Host smart-9fa4d12b-8f42-456e-89c8-be4cbb3156b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=388132654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.388132654
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1816985793
Short name T779
Test name
Test status
Simulation time 11703345 ps
CPU time 1.69 seconds
Started Jun 24 06:40:04 PM PDT 24
Finished Jun 24 06:40:08 PM PDT 24
Peak memory 237364 kb
Host smart-9dc6e25c-03fc-4235-a57c-52f07ae6d1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1816985793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1816985793
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1816333254
Short name T827
Test name
Test status
Simulation time 10305517 ps
CPU time 1.61 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 236364 kb
Host smart-b7b51221-7aff-40c7-9611-37810ada4509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1816333254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1816333254
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1066395720
Short name T825
Test name
Test status
Simulation time 3041680320 ps
CPU time 161.14 seconds
Started Jun 24 06:39:23 PM PDT 24
Finished Jun 24 06:42:06 PM PDT 24
Peak memory 240624 kb
Host smart-5d6f6056-a14a-404f-b333-c1ea1e471c23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1066395720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1066395720
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3700565315
Short name T814
Test name
Test status
Simulation time 2973794376 ps
CPU time 184.21 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:42:38 PM PDT 24
Peak memory 240768 kb
Host smart-64b66858-206e-4174-a226-0e2b03bb07f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3700565315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3700565315
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1940512027
Short name T194
Test name
Test status
Simulation time 420956020 ps
CPU time 8.51 seconds
Started Jun 24 06:39:24 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 240772 kb
Host smart-59797a9f-7742-4661-aef7-64643627012c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1940512027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1940512027
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.836095194
Short name T363
Test name
Test status
Simulation time 406390913 ps
CPU time 4.63 seconds
Started Jun 24 06:39:32 PM PDT 24
Finished Jun 24 06:39:37 PM PDT 24
Peak memory 240820 kb
Host smart-04198a63-d38c-4aa9-9d6e-d563de1953a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836095194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.836095194
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2399551140
Short name T776
Test name
Test status
Simulation time 120976315 ps
CPU time 5.89 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:39:40 PM PDT 24
Peak memory 237288 kb
Host smart-45090a00-91f0-4a26-bfc0-45cd6de3acce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2399551140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2399551140
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.63860317
Short name T778
Test name
Test status
Simulation time 14104916 ps
CPU time 1.57 seconds
Started Jun 24 06:39:29 PM PDT 24
Finished Jun 24 06:39:31 PM PDT 24
Peak memory 236408 kb
Host smart-dddeffed-def8-44f5-ad9f-8e426c9b9a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63860317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.63860317
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.173300724
Short name T198
Test name
Test status
Simulation time 1939799370 ps
CPU time 22.06 seconds
Started Jun 24 06:39:24 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 244624 kb
Host smart-4ef8f0ca-5aab-4fce-9e86-bd65800b562d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=173300724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.173300724
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3359604477
Short name T147
Test name
Test status
Simulation time 14244309113 ps
CPU time 283.18 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:44:17 PM PDT 24
Peak memory 273640 kb
Host smart-a43eb3af-430f-4bde-839d-88d7b518741e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3359604477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3359604477
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.76393335
Short name T773
Test name
Test status
Simulation time 97125778 ps
CPU time 6.44 seconds
Started Jun 24 06:39:35 PM PDT 24
Finished Jun 24 06:39:45 PM PDT 24
Peak memory 248852 kb
Host smart-bffb9710-91c7-4d01-b936-a9ffc0757248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=76393335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.76393335
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3145413414
Short name T166
Test name
Test status
Simulation time 15634820 ps
CPU time 1.28 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 236440 kb
Host smart-2a06076a-8c3e-404f-9d33-431b3f488d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3145413414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3145413414
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3704377695
Short name T810
Test name
Test status
Simulation time 9563266 ps
CPU time 1.18 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 235416 kb
Host smart-9d945670-553a-411a-980d-3f06bfe50b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3704377695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3704377695
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3623618526
Short name T714
Test name
Test status
Simulation time 8113981 ps
CPU time 1.36 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 237360 kb
Host smart-3b68ab7a-8859-4535-a72a-379bb35e52e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3623618526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3623618526
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2856439084
Short name T788
Test name
Test status
Simulation time 23803505 ps
CPU time 1.45 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:07 PM PDT 24
Peak memory 236396 kb
Host smart-decba615-64ec-4ecf-b6d5-2b5c67dd2480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2856439084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2856439084
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.205434212
Short name T357
Test name
Test status
Simulation time 15921907 ps
CPU time 1.35 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:11 PM PDT 24
Peak memory 237368 kb
Host smart-35697644-3b01-45de-91fb-5346a1e734f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205434212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.205434212
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.689905266
Short name T719
Test name
Test status
Simulation time 13249646 ps
CPU time 1.28 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:11 PM PDT 24
Peak memory 235396 kb
Host smart-f5ea6666-e43d-475d-abf8-f1f1e9e0f250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=689905266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.689905266
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3023899999
Short name T721
Test name
Test status
Simulation time 16638945 ps
CPU time 1.29 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:11 PM PDT 24
Peak memory 236412 kb
Host smart-5b32e764-685c-4bb7-b469-e56bb52a6150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3023899999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3023899999
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.725079373
Short name T799
Test name
Test status
Simulation time 14114697 ps
CPU time 1.38 seconds
Started Jun 24 06:40:05 PM PDT 24
Finished Jun 24 06:40:09 PM PDT 24
Peak memory 236444 kb
Host smart-12aec060-abba-4276-b305-cbe35b2c6770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=725079373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.725079373
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.901378754
Short name T355
Test name
Test status
Simulation time 15118256 ps
CPU time 1.3 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 237368 kb
Host smart-7b502a5f-87e2-408c-a7f6-06ee3f1c35ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=901378754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.901378754
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1589963479
Short name T804
Test name
Test status
Simulation time 7710918 ps
CPU time 1.44 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 236428 kb
Host smart-67c49bd2-4ccf-49fb-900b-88e7936b7f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589963479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1589963479
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2354904558
Short name T767
Test name
Test status
Simulation time 234523638 ps
CPU time 8.84 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:49 PM PDT 24
Peak memory 252936 kb
Host smart-753805b0-3a73-4839-908a-be696d54d00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354904558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2354904558
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1431573628
Short name T743
Test name
Test status
Simulation time 55487377 ps
CPU time 4.83 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:45 PM PDT 24
Peak memory 240008 kb
Host smart-1739db72-1b47-4926-af07-9fe966f9fff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1431573628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1431573628
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1363180458
Short name T727
Test name
Test status
Simulation time 11876751 ps
CPU time 1.34 seconds
Started Jun 24 06:39:35 PM PDT 24
Finished Jun 24 06:39:39 PM PDT 24
Peak memory 237364 kb
Host smart-827925eb-c7cb-496f-bbc9-5231189fd45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1363180458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1363180458
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4156922919
Short name T199
Test name
Test status
Simulation time 178370970 ps
CPU time 25.13 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:40:05 PM PDT 24
Peak memory 245560 kb
Host smart-3c3e72ac-b0fc-4958-b072-250f500b1fc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4156922919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4156922919
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4193231413
Short name T135
Test name
Test status
Simulation time 1011537908 ps
CPU time 107.43 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 257408 kb
Host smart-1fe4fe9a-d752-4e30-99eb-d0d2349e7e52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4193231413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.4193231413
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3338396044
Short name T822
Test name
Test status
Simulation time 8889121645 ps
CPU time 317.56 seconds
Started Jun 24 06:39:34 PM PDT 24
Finished Jun 24 06:44:53 PM PDT 24
Peak memory 268528 kb
Host smart-81df4771-931d-4625-ae0f-2f9002befc71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338396044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3338396044
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.569708446
Short name T816
Test name
Test status
Simulation time 949194970 ps
CPU time 15.57 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:59 PM PDT 24
Peak memory 254472 kb
Host smart-5b67b25b-acac-423d-8ed8-9771d781b180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=569708446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.569708446
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1781378729
Short name T806
Test name
Test status
Simulation time 198499208 ps
CPU time 8.86 seconds
Started Jun 24 06:39:46 PM PDT 24
Finished Jun 24 06:39:57 PM PDT 24
Peak memory 240252 kb
Host smart-7e619834-c8da-4cfb-9820-cc3277fc928b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781378729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1781378729
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.459003225
Short name T192
Test name
Test status
Simulation time 525781816 ps
CPU time 5.65 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:39:47 PM PDT 24
Peak memory 237508 kb
Host smart-72d8deba-7939-45de-91ba-923342f781bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=459003225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.459003225
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3386856146
Short name T354
Test name
Test status
Simulation time 13818519 ps
CPU time 1.72 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:42 PM PDT 24
Peak memory 236440 kb
Host smart-34c85d79-8b8f-4720-b20a-e78f6528eeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3386856146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3386856146
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.36568257
Short name T795
Test name
Test status
Simulation time 88487185 ps
CPU time 10.18 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:54 PM PDT 24
Peak memory 244612 kb
Host smart-42085eee-3fe7-4c3f-8846-c6ac2a6122cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=36568257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outst
anding.36568257
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4170996776
Short name T142
Test name
Test status
Simulation time 5616301509 ps
CPU time 207.88 seconds
Started Jun 24 06:39:38 PM PDT 24
Finished Jun 24 06:43:09 PM PDT 24
Peak memory 265576 kb
Host smart-8c99f34a-7cde-45f2-ad90-b27f3fc504df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4170996776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4170996776
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2076470076
Short name T365
Test name
Test status
Simulation time 8077540656 ps
CPU time 648.25 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:50:28 PM PDT 24
Peak memory 265620 kb
Host smart-ad04803e-8b6d-4a78-bdd1-1457e750718d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076470076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2076470076
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4286949641
Short name T744
Test name
Test status
Simulation time 316816723 ps
CPU time 18.87 seconds
Started Jun 24 06:39:35 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 248524 kb
Host smart-1898e32d-eb6c-4402-8ea6-55f161330131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4286949641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4286949641
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.775779214
Short name T178
Test name
Test status
Simulation time 73300340 ps
CPU time 5.48 seconds
Started Jun 24 06:39:37 PM PDT 24
Finished Jun 24 06:39:46 PM PDT 24
Peak memory 238404 kb
Host smart-689db29c-1d3c-4e59-9669-7858dec1f16a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775779214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.775779214
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.609618651
Short name T798
Test name
Test status
Simulation time 499086972 ps
CPU time 10.95 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:39:55 PM PDT 24
Peak memory 237280 kb
Host smart-46220e3b-02c4-407d-bbcc-02fe6cf8a5a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=609618651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.609618651
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.341150536
Short name T353
Test name
Test status
Simulation time 8093305 ps
CPU time 1.51 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:45 PM PDT 24
Peak memory 237312 kb
Host smart-aa25b43e-5e1d-4b68-b14a-7fb1b68cbafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=341150536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.341150536
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.231394915
Short name T797
Test name
Test status
Simulation time 2053603505 ps
CPU time 36.53 seconds
Started Jun 24 06:39:43 PM PDT 24
Finished Jun 24 06:40:22 PM PDT 24
Peak memory 245536 kb
Host smart-b4a4258e-86f2-4859-900e-a875569ed613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=231394915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.231394915
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2022266779
Short name T159
Test name
Test status
Simulation time 2637888161 ps
CPU time 176.33 seconds
Started Jun 24 06:39:45 PM PDT 24
Finished Jun 24 06:42:44 PM PDT 24
Peak memory 265588 kb
Host smart-b9ff3948-8dee-44dc-b732-f5cd10a0e9bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2022266779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2022266779
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3035711904
Short name T155
Test name
Test status
Simulation time 6042932349 ps
CPU time 365.82 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:45:53 PM PDT 24
Peak memory 265628 kb
Host smart-f6bc8688-cc00-445b-b846-c60d6b0adc02
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035711904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3035711904
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2466689589
Short name T760
Test name
Test status
Simulation time 2424135411 ps
CPU time 19.74 seconds
Started Jun 24 06:39:39 PM PDT 24
Finished Jun 24 06:40:01 PM PDT 24
Peak memory 249080 kb
Host smart-05b7e3b4-e193-40b9-89f8-81e538bd4e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2466689589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2466689589
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2695267224
Short name T245
Test name
Test status
Simulation time 66508831 ps
CPU time 4.66 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:39:49 PM PDT 24
Peak memory 237420 kb
Host smart-9467fa22-dda0-44ba-90ae-ec9603d371a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2695267224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2695267224
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3024626091
Short name T211
Test name
Test status
Simulation time 101525775 ps
CPU time 7.79 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:39:52 PM PDT 24
Peak memory 239532 kb
Host smart-20ded9a3-3f34-44de-94da-4b42bdcb5fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024626091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3024626091
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.213895148
Short name T742
Test name
Test status
Simulation time 220029530 ps
CPU time 4.45 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:48 PM PDT 24
Peak memory 240120 kb
Host smart-31bcc5ff-9d08-468e-88b6-949504995868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=213895148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.213895148
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3669632835
Short name T738
Test name
Test status
Simulation time 55997626 ps
CPU time 1.36 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:45 PM PDT 24
Peak memory 237360 kb
Host smart-305fe939-783c-42fe-8f07-df8494749b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669632835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3669632835
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.587959138
Short name T758
Test name
Test status
Simulation time 1137398781 ps
CPU time 23.86 seconds
Started Jun 24 06:39:44 PM PDT 24
Finished Jun 24 06:40:11 PM PDT 24
Peak memory 245548 kb
Host smart-affb312c-08b3-41ab-ba29-5013c2766691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=587959138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.587959138
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.837547627
Short name T809
Test name
Test status
Simulation time 83884875 ps
CPU time 12.45 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:56 PM PDT 24
Peak memory 249036 kb
Host smart-6900a686-7e53-4b82-8681-3048c7fceeea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=837547627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.837547627
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2260734263
Short name T176
Test name
Test status
Simulation time 39438463 ps
CPU time 3.49 seconds
Started Jun 24 06:39:39 PM PDT 24
Finished Jun 24 06:39:46 PM PDT 24
Peak memory 238484 kb
Host smart-4e3b170d-ed05-43f7-ad80-b8640fc55a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2260734263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2260734263
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1579181713
Short name T812
Test name
Test status
Simulation time 454503294 ps
CPU time 8 seconds
Started Jun 24 06:39:28 PM PDT 24
Finished Jun 24 06:39:37 PM PDT 24
Peak memory 240640 kb
Host smart-ff70c49c-4837-421d-af83-375c31e28a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579181713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1579181713
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.110797804
Short name T782
Test name
Test status
Simulation time 67866847 ps
CPU time 3.53 seconds
Started Jun 24 06:39:36 PM PDT 24
Finished Jun 24 06:39:43 PM PDT 24
Peak memory 237272 kb
Host smart-83e09899-3c86-4717-828a-58dd04bbb887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=110797804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.110797804
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.318379127
Short name T741
Test name
Test status
Simulation time 9834933 ps
CPU time 1.35 seconds
Started Jun 24 06:39:33 PM PDT 24
Finished Jun 24 06:39:35 PM PDT 24
Peak memory 235324 kb
Host smart-d4b260f9-4aa8-40e7-a5a1-d1eb78a73d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=318379127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.318379127
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2084208980
Short name T191
Test name
Test status
Simulation time 100767688 ps
CPU time 11.81 seconds
Started Jun 24 06:39:28 PM PDT 24
Finished Jun 24 06:39:40 PM PDT 24
Peak memory 248964 kb
Host smart-518bb31a-4516-4f86-ae49-e7c7b1ce890c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084208980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2084208980
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2930266020
Short name T819
Test name
Test status
Simulation time 3662246791 ps
CPU time 124.59 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:41:49 PM PDT 24
Peak memory 265684 kb
Host smart-6ec50861-bef0-4552-a367-7cf0166d486e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2930266020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2930266020
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2047881136
Short name T156
Test name
Test status
Simulation time 2415391843 ps
CPU time 340.47 seconds
Started Jun 24 06:39:42 PM PDT 24
Finished Jun 24 06:45:25 PM PDT 24
Peak memory 269368 kb
Host smart-e3875784-31a1-4159-b1b2-a3285e19fa78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047881136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2047881136
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.410653561
Short name T811
Test name
Test status
Simulation time 159540211 ps
CPU time 11.15 seconds
Started Jun 24 06:39:41 PM PDT 24
Finished Jun 24 06:39:55 PM PDT 24
Peak memory 249000 kb
Host smart-b719177a-189c-45c8-bc90-89ca50c33332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410653561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.410653561
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1959666763
Short name T581
Test name
Test status
Simulation time 56532524912 ps
CPU time 1222.64 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 07:00:31 PM PDT 24
Peak memory 290060 kb
Host smart-c713c907-c295-49c7-8531-dfd96ddfba34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959666763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1959666763
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2318535336
Short name T389
Test name
Test status
Simulation time 664292352 ps
CPU time 9.99 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:20 PM PDT 24
Peak memory 248856 kb
Host smart-d39fdfe5-d02b-4f69-a47f-1500c59af49d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2318535336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2318535336
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2749582804
Short name T699
Test name
Test status
Simulation time 2911998668 ps
CPU time 59.69 seconds
Started Jun 24 06:39:58 PM PDT 24
Finished Jun 24 06:41:00 PM PDT 24
Peak memory 257348 kb
Host smart-019e21d9-374a-4eff-8c7b-5f78b2938cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27495
82804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2749582804
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.200174600
Short name T418
Test name
Test status
Simulation time 296331997 ps
CPU time 8.49 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:40:19 PM PDT 24
Peak memory 249044 kb
Host smart-01f77747-7d94-4147-a0bd-a7b2271f7557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
4600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.200174600
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3426519438
Short name T99
Test name
Test status
Simulation time 111548999774 ps
CPU time 1103.41 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:58:33 PM PDT 24
Peak memory 283392 kb
Host smart-2a7462bf-9160-4243-aaca-134164b53041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426519438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3426519438
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.865731511
Short name T229
Test name
Test status
Simulation time 3327740988 ps
CPU time 50.32 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:41:01 PM PDT 24
Peak memory 257364 kb
Host smart-401cf157-89fc-48ac-99e8-acfb5f8760b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86573
1511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.865731511
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.288892971
Short name T498
Test name
Test status
Simulation time 379017815 ps
CPU time 28.5 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 06:40:44 PM PDT 24
Peak memory 255496 kb
Host smart-3f94fd31-9b42-41f6-9a94-32000356362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28889
2971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.288892971
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3395844435
Short name T678
Test name
Test status
Simulation time 3271339133 ps
CPU time 47.08 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:40:58 PM PDT 24
Peak memory 256712 kb
Host smart-cefbdedd-0dba-4955-bfae-6abdc4d55a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
44435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3395844435
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1494898531
Short name T40
Test name
Test status
Simulation time 344416344 ps
CPU time 19.64 seconds
Started Jun 24 06:40:05 PM PDT 24
Finished Jun 24 06:40:28 PM PDT 24
Peak memory 249112 kb
Host smart-9ceaf024-aed8-4aab-bf96-f81840a64524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
98531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1494898531
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.890070330
Short name T51
Test name
Test status
Simulation time 37020753146 ps
CPU time 1961.02 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 07:12:51 PM PDT 24
Peak memory 301396 kb
Host smart-71a60f7e-27d4-41e7-bd36-9560337ed837
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890070330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.890070330
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2521390603
Short name T113
Test name
Test status
Simulation time 93583062608 ps
CPU time 970.55 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:56:20 PM PDT 24
Peak memory 281892 kb
Host smart-d88299ad-ea08-4f1a-b1c7-958826e36487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521390603 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2521390603
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1641804563
Short name T507
Test name
Test status
Simulation time 6249861614 ps
CPU time 618.05 seconds
Started Jun 24 06:40:00 PM PDT 24
Finished Jun 24 06:50:20 PM PDT 24
Peak memory 265540 kb
Host smart-c72c10bb-5cfb-48df-820e-e4c88ad3bdb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641804563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1641804563
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3812572364
Short name T433
Test name
Test status
Simulation time 12753037306 ps
CPU time 68.05 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:41:06 PM PDT 24
Peak memory 249156 kb
Host smart-ac5b1e8b-07b3-42ec-b1a6-aebe375f7d97
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3812572364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3812572364
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.16852112
Short name T663
Test name
Test status
Simulation time 1629162369 ps
CPU time 83.49 seconds
Started Jun 24 06:39:59 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 249288 kb
Host smart-869717fb-5dec-44ee-a159-cc93ef87ad1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16852
112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.16852112
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1409668211
Short name T631
Test name
Test status
Simulation time 911861245 ps
CPU time 19.44 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 06:40:35 PM PDT 24
Peak memory 249120 kb
Host smart-d2a5fe45-24d7-4a18-9a8d-759fb557ee3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
68211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1409668211
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2825005093
Short name T437
Test name
Test status
Simulation time 92995583644 ps
CPU time 1317.69 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 07:02:02 PM PDT 24
Peak memory 283388 kb
Host smart-81fe043f-d8d4-4d78-bab8-e3beef6f6662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825005093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2825005093
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2370766100
Short name T68
Test name
Test status
Simulation time 73502410296 ps
CPU time 3118.28 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 07:31:57 PM PDT 24
Peak memory 289908 kb
Host smart-a2015e35-fc47-4f28-987b-d0fd6dea2398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370766100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2370766100
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.983286532
Short name T546
Test name
Test status
Simulation time 1910254827 ps
CPU time 30.99 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:30 PM PDT 24
Peak memory 249184 kb
Host smart-c5d06b71-2162-4860-9c76-8e767a5805ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98328
6532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.983286532
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1013041009
Short name T613
Test name
Test status
Simulation time 553316556 ps
CPU time 30.53 seconds
Started Jun 24 06:40:12 PM PDT 24
Finished Jun 24 06:40:46 PM PDT 24
Peak memory 249048 kb
Host smart-746b4908-1dc5-437d-8402-cb40db6e1bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10130
41009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1013041009
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4253999678
Short name T35
Test name
Test status
Simulation time 180077411 ps
CPU time 11.08 seconds
Started Jun 24 06:40:02 PM PDT 24
Finished Jun 24 06:40:14 PM PDT 24
Peak memory 277408 kb
Host smart-8f5f05d5-6384-45df-afcb-8004089c8860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4253999678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4253999678
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2778290315
Short name T588
Test name
Test status
Simulation time 237083904 ps
CPU time 16.15 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:15 PM PDT 24
Peak memory 249040 kb
Host smart-98f92c57-0e06-44a7-a788-aa684c54ca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27782
90315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2778290315
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2922377045
Short name T440
Test name
Test status
Simulation time 4168220024 ps
CPU time 23.49 seconds
Started Jun 24 06:39:59 PM PDT 24
Finished Jun 24 06:40:24 PM PDT 24
Peak memory 249160 kb
Host smart-cada8753-14f6-4889-973a-01469df3d95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
77045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2922377045
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4267957415
Short name T55
Test name
Test status
Simulation time 33823436035 ps
CPU time 1116.48 seconds
Started Jun 24 06:40:07 PM PDT 24
Finished Jun 24 06:58:47 PM PDT 24
Peak memory 272360 kb
Host smart-e28ba516-314e-4120-9b4a-31a9fd5bca40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267957415 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4267957415
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2161483244
Short name T91
Test name
Test status
Simulation time 29952515411 ps
CPU time 1796.48 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 07:11:04 PM PDT 24
Peak memory 273028 kb
Host smart-9cfba9f2-2c78-4b5e-b90d-76f4422f6ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161483244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2161483244
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3272530804
Short name T591
Test name
Test status
Simulation time 1433365459 ps
CPU time 58.42 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:42:03 PM PDT 24
Peak memory 240892 kb
Host smart-d3245e9b-51e8-4836-bf78-ac0c43635296
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3272530804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3272530804
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4135390378
Short name T460
Test name
Test status
Simulation time 3686524414 ps
CPU time 78.81 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:42:23 PM PDT 24
Peak memory 257304 kb
Host smart-65787861-5173-44cd-9b5e-a050e569b025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41353
90378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4135390378
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2629416510
Short name T429
Test name
Test status
Simulation time 1914142298 ps
CPU time 31.55 seconds
Started Jun 24 06:40:55 PM PDT 24
Finished Jun 24 06:41:33 PM PDT 24
Peak memory 254716 kb
Host smart-ec143bf7-ce7d-46ae-8586-f452ddecd739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26294
16510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2629416510
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2596478878
Short name T201
Test name
Test status
Simulation time 21449985486 ps
CPU time 959.72 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:57:03 PM PDT 24
Peak memory 265620 kb
Host smart-d20dfcc5-36d1-4fc1-b985-2e872c8128a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596478878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2596478878
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.477472653
Short name T57
Test name
Test status
Simulation time 3014910863 ps
CPU time 50.08 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:56 PM PDT 24
Peak memory 256760 kb
Host smart-c8ab689c-55fd-466d-8c49-5be4153dd254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47747
2653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.477472653
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.760258327
Short name T620
Test name
Test status
Simulation time 1301623652 ps
CPU time 8.97 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:41:13 PM PDT 24
Peak memory 247652 kb
Host smart-f2a0efb7-57b8-4249-93ba-54ce010081c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76025
8327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.760258327
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.347157049
Short name T705
Test name
Test status
Simulation time 74770398 ps
CPU time 9.56 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:18 PM PDT 24
Peak memory 254584 kb
Host smart-e6fe49ad-6e40-477c-92e7-6b5e60796139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34715
7049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.347157049
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2848471316
Short name T420
Test name
Test status
Simulation time 2533263278 ps
CPU time 66.87 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:42:10 PM PDT 24
Peak memory 249164 kb
Host smart-63a28030-05aa-4eb1-a91d-fbc6e8346c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
71316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2848471316
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3638703904
Short name T241
Test name
Test status
Simulation time 155181620869 ps
CPU time 6203.26 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 08:24:27 PM PDT 24
Peak memory 322540 kb
Host smart-cd182f62-b46a-4757-b21f-79300f2b9964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638703904 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3638703904
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2719645036
Short name T654
Test name
Test status
Simulation time 315280196 ps
CPU time 15.08 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:41:19 PM PDT 24
Peak memory 249040 kb
Host smart-f929077d-c69b-418c-93b3-b68d13e5f45c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2719645036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2719645036
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1630261370
Short name T465
Test name
Test status
Simulation time 15437735901 ps
CPU time 249.01 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:45:17 PM PDT 24
Peak memory 257316 kb
Host smart-91a6d384-a253-4294-8391-42cd1fb8635e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16302
61370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1630261370
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2697251651
Short name T680
Test name
Test status
Simulation time 4186521766 ps
CPU time 24.86 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:41:29 PM PDT 24
Peak memory 256392 kb
Host smart-96f35977-a3ac-4953-9acb-ada12bfccf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972
51651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2697251651
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2564142958
Short name T347
Test name
Test status
Simulation time 26844886298 ps
CPU time 1275.11 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 07:02:20 PM PDT 24
Peak memory 272400 kb
Host smart-d04e7ea3-76e7-4885-a4f8-ce4a65fab586
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564142958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2564142958
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.818418370
Short name T476
Test name
Test status
Simulation time 34157706271 ps
CPU time 1631.79 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 07:08:20 PM PDT 24
Peak memory 290104 kb
Host smart-7ba45caa-6763-4c24-b008-a3f489a92b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818418370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.818418370
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2819209907
Short name T693
Test name
Test status
Simulation time 1730790662 ps
CPU time 50.51 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:41:56 PM PDT 24
Peak memory 253332 kb
Host smart-250f1568-4ca5-43b9-93af-ff857eea3af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819209907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2819209907
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3505094175
Short name T419
Test name
Test status
Simulation time 1667004118 ps
CPU time 33.49 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:42 PM PDT 24
Peak memory 249116 kb
Host smart-8c7db5fd-8740-42e3-a963-ddfb7483c4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050
94175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3505094175
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3546545169
Short name T692
Test name
Test status
Simulation time 754582981 ps
CPU time 55.64 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:42:03 PM PDT 24
Peak memory 249420 kb
Host smart-79db8ba0-862b-4ef0-818b-698cdfc9415f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465
45169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3546545169
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3871077218
Short name T117
Test name
Test status
Simulation time 326051917 ps
CPU time 23.14 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:29 PM PDT 24
Peak memory 247916 kb
Host smart-4bdc7a6c-4205-4715-863e-09d25202e569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
77218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3871077218
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2328330891
Short name T412
Test name
Test status
Simulation time 1596076516 ps
CPU time 44.14 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:41:49 PM PDT 24
Peak memory 249104 kb
Host smart-0317e02f-2737-4482-aa80-77fb4b0c5d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23283
30891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2328330891
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.402135652
Short name T557
Test name
Test status
Simulation time 1063643974 ps
CPU time 68.58 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:42:15 PM PDT 24
Peak memory 256716 kb
Host smart-01eb8099-4d5a-436d-b509-c4b1fc02258b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402135652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.402135652
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1679916378
Short name T228
Test name
Test status
Simulation time 26309223 ps
CPU time 2.24 seconds
Started Jun 24 06:41:03 PM PDT 24
Finished Jun 24 06:41:17 PM PDT 24
Peak memory 249188 kb
Host smart-87106991-2671-4e8c-98fa-16779fbe746d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1679916378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1679916378
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2959305552
Short name T479
Test name
Test status
Simulation time 57441896858 ps
CPU time 3323.98 seconds
Started Jun 24 06:41:05 PM PDT 24
Finished Jun 24 07:36:40 PM PDT 24
Peak memory 289488 kb
Host smart-333bb6f5-bebe-45df-92d7-60348dffb9a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959305552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2959305552
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1457946727
Short name T542
Test name
Test status
Simulation time 954258217 ps
CPU time 12.18 seconds
Started Jun 24 06:41:05 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 249132 kb
Host smart-347a7298-5ebf-45c5-98e7-b4abfb327c6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1457946727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1457946727
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.708331153
Short name T603
Test name
Test status
Simulation time 1172747925 ps
CPU time 33.32 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:46 PM PDT 24
Peak memory 256268 kb
Host smart-f74d08c3-4f0b-415b-886f-2c07f1d3c340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70833
1153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.708331153
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.523601205
Short name T334
Test name
Test status
Simulation time 393322185654 ps
CPU time 1629.25 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 07:08:18 PM PDT 24
Peak memory 290100 kb
Host smart-0aa9c84a-9c2d-4a3c-a876-787686d0c6e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523601205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.523601205
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2264929973
Short name T260
Test name
Test status
Simulation time 34783131425 ps
CPU time 775.01 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:54:10 PM PDT 24
Peak memory 273584 kb
Host smart-b801a476-c668-466c-9612-e329c8323d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264929973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2264929973
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2281153484
Short name T489
Test name
Test status
Simulation time 1073692355 ps
CPU time 28.19 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:36 PM PDT 24
Peak memory 256752 kb
Host smart-7feb3f74-fcd6-452d-8842-be29012263b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
53484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2281153484
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.489864299
Short name T71
Test name
Test status
Simulation time 612664045 ps
CPU time 30.81 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:39 PM PDT 24
Peak memory 256904 kb
Host smart-770329e4-8193-4496-b4df-4735a5daff01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48986
4299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.489864299
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1477806083
Short name T41
Test name
Test status
Simulation time 1489681502 ps
CPU time 24.81 seconds
Started Jun 24 06:41:11 PM PDT 24
Finished Jun 24 06:41:43 PM PDT 24
Peak memory 256184 kb
Host smart-522af743-cbde-4ab3-ba5f-c8e4f08311a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
06083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1477806083
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1322765291
Short name T398
Test name
Test status
Simulation time 1151750522 ps
CPU time 62.6 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:42:17 PM PDT 24
Peak memory 257192 kb
Host smart-68f8b0b2-eb23-40cb-af76-d6f4b12c1cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13227
65291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1322765291
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1691320942
Short name T689
Test name
Test status
Simulation time 230191020919 ps
CPU time 3143.61 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:33:38 PM PDT 24
Peak memory 289460 kb
Host smart-1f91222f-ff0a-474d-a200-16c1afa449ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691320942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1691320942
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1307509899
Short name T509
Test name
Test status
Simulation time 300333126209 ps
CPU time 1815.03 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:11:30 PM PDT 24
Peak memory 297880 kb
Host smart-415a44b8-6f06-44d8-821d-a58112bacce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307509899 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1307509899
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.969249609
Short name T221
Test name
Test status
Simulation time 53037758 ps
CPU time 2.49 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 249160 kb
Host smart-e404db8c-9fb6-420b-bf1a-8baabd1a0732
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=969249609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.969249609
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2030412834
Short name T46
Test name
Test status
Simulation time 141791506828 ps
CPU time 2008.66 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 07:14:39 PM PDT 24
Peak memory 284980 kb
Host smart-88a7acd7-d306-4f2a-a6fa-b560062d0e07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030412834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2030412834
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.473114780
Short name T691
Test name
Test status
Simulation time 231571681 ps
CPU time 11.45 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 06:41:23 PM PDT 24
Peak memory 249036 kb
Host smart-a9dfe15c-cc63-4e40-b703-6b8047a5763f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=473114780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.473114780
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3268229221
Short name T424
Test name
Test status
Simulation time 6254552758 ps
CPU time 124.4 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:43:10 PM PDT 24
Peak memory 257188 kb
Host smart-c29e468d-567d-453d-aac9-6acb6906611b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32682
29221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3268229221
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3699877375
Short name T67
Test name
Test status
Simulation time 4149402596 ps
CPU time 43.48 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 256244 kb
Host smart-1b3af331-c3ee-4d46-bca7-b44de90281ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
77375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3699877375
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2074320962
Short name T706
Test name
Test status
Simulation time 67543588479 ps
CPU time 1442.95 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 07:05:13 PM PDT 24
Peak memory 290020 kb
Host smart-10b42dbc-08b5-4db5-841e-b12239ba69b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074320962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2074320962
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1094904254
Short name T597
Test name
Test status
Simulation time 55527475820 ps
CPU time 3261.35 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:35:36 PM PDT 24
Peak memory 289084 kb
Host smart-a6572a6c-e3c1-4a62-b1f4-e3a5632c8224
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094904254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1094904254
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4138142100
Short name T330
Test name
Test status
Simulation time 8472460775 ps
CPU time 95.28 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:42:40 PM PDT 24
Peak memory 248680 kb
Host smart-1c9d1d59-f6e1-454e-ada8-a8a0a6d2fa73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138142100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4138142100
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.53403940
Short name T610
Test name
Test status
Simulation time 217845114 ps
CPU time 14.84 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:24 PM PDT 24
Peak memory 249120 kb
Host smart-7d4fda99-7c5b-4cef-8f52-487b7fbe19fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53403
940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.53403940
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2759626865
Short name T533
Test name
Test status
Simulation time 386340299 ps
CPU time 20.13 seconds
Started Jun 24 06:41:03 PM PDT 24
Finished Jun 24 06:41:33 PM PDT 24
Peak memory 249020 kb
Host smart-7f8178fb-bfc0-4919-8f2b-76c4f5f304be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
26865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2759626865
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.353293081
Short name T659
Test name
Test status
Simulation time 142045047 ps
CPU time 10.61 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:21 PM PDT 24
Peak memory 256048 kb
Host smart-d90a3c98-1b09-437e-9442-177f502f7fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329
3081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.353293081
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2397186841
Short name T106
Test name
Test status
Simulation time 312716358816 ps
CPU time 6155.03 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 08:23:48 PM PDT 24
Peak memory 338408 kb
Host smart-9f77bc8a-3b4c-45fe-afa5-3bd3c3def73f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397186841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2397186841
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2468001576
Short name T227
Test name
Test status
Simulation time 168321994 ps
CPU time 3.92 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:41:22 PM PDT 24
Peak memory 248944 kb
Host smart-f820bfb5-98d7-4341-ac41-0752fdcbcd27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2468001576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2468001576
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1157288198
Short name T524
Test name
Test status
Simulation time 55864377915 ps
CPU time 2977.51 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:30:52 PM PDT 24
Peak memory 289536 kb
Host smart-f15d4b03-b8f4-47f8-9517-81c06240cb48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157288198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1157288198
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2835884131
Short name T564
Test name
Test status
Simulation time 928271757 ps
CPU time 37.95 seconds
Started Jun 24 06:41:03 PM PDT 24
Finished Jun 24 06:41:52 PM PDT 24
Peak memory 249068 kb
Host smart-71f439e9-4015-4aec-b606-3ede888988de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2835884131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2835884131
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1067516635
Short name T402
Test name
Test status
Simulation time 11732537195 ps
CPU time 139.98 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 06:43:31 PM PDT 24
Peak memory 257284 kb
Host smart-b3c8bf74-c371-47d6-ad0e-d518d1b3d93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
16635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1067516635
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1981602566
Short name T442
Test name
Test status
Simulation time 146521455 ps
CPU time 12.46 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 256004 kb
Host smart-253e56b7-bf60-4920-b14b-b76aaae2e29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
02566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1981602566
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3168750423
Short name T595
Test name
Test status
Simulation time 42855370605 ps
CPU time 2281.98 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 07:19:20 PM PDT 24
Peak memory 289480 kb
Host smart-3a2c05e7-24f3-4007-827b-e7150238b7b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168750423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3168750423
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.689332402
Short name T475
Test name
Test status
Simulation time 10224501311 ps
CPU time 1220.88 seconds
Started Jun 24 06:41:05 PM PDT 24
Finished Jun 24 07:01:36 PM PDT 24
Peak memory 289488 kb
Host smart-e9f315d2-119d-4275-809f-12f51e951141
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689332402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.689332402
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.295702816
Short name T701
Test name
Test status
Simulation time 78944493440 ps
CPU time 441.4 seconds
Started Jun 24 06:41:05 PM PDT 24
Finished Jun 24 06:48:37 PM PDT 24
Peak memory 248700 kb
Host smart-bac0aba4-2240-4eaa-bc12-7e5ade66cd9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295702816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.295702816
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2185446677
Short name T492
Test name
Test status
Simulation time 929031539 ps
CPU time 45.68 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:56 PM PDT 24
Peak memory 256568 kb
Host smart-389c17a1-55aa-4016-a480-6a82c718f7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
46677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2185446677
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2606956471
Short name T601
Test name
Test status
Simulation time 198532567 ps
CPU time 12.85 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 252292 kb
Host smart-c113e270-fcd3-40b5-b0d6-b3cec9d3d3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26069
56471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2606956471
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3664960225
Short name T286
Test name
Test status
Simulation time 496498205 ps
CPU time 10.73 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:23 PM PDT 24
Peak memory 249084 kb
Host smart-88d03206-492e-44fa-87a6-e7071bb18d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
60225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3664960225
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1558624512
Short name T185
Test name
Test status
Simulation time 145193921 ps
CPU time 11.77 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:24 PM PDT 24
Peak memory 248920 kb
Host smart-9a98caed-51db-4618-a005-28dd5169e510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
24512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1558624512
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3884552545
Short name T19
Test name
Test status
Simulation time 172721198 ps
CPU time 3.95 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 249380 kb
Host smart-286d9298-2bba-4276-adab-b5294bca5ab1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3884552545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3884552545
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3328701701
Short name T574
Test name
Test status
Simulation time 59919318530 ps
CPU time 1335.56 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 07:03:30 PM PDT 24
Peak memory 288564 kb
Host smart-eae905a5-f15f-46dc-a410-dfa52fdbc3b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328701701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3328701701
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1593915251
Short name T589
Test name
Test status
Simulation time 301846455 ps
CPU time 9.07 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:41:18 PM PDT 24
Peak memory 240844 kb
Host smart-010f4d5b-37fd-4492-a1f1-e9558f9a3250
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1593915251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1593915251
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2446388430
Short name T505
Test name
Test status
Simulation time 32868285963 ps
CPU time 105.37 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:43:00 PM PDT 24
Peak memory 249296 kb
Host smart-875b57de-7f58-4247-ba57-1a6912de1994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
88430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2446388430
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.219627430
Short name T621
Test name
Test status
Simulation time 18602565 ps
CPU time 2.97 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:41:21 PM PDT 24
Peak memory 239628 kb
Host smart-483c5fc2-791e-405f-a13a-59fe0ffd118b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21962
7430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.219627430
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2806552630
Short name T254
Test name
Test status
Simulation time 8746292495 ps
CPU time 699.47 seconds
Started Jun 24 06:41:10 PM PDT 24
Finished Jun 24 06:52:58 PM PDT 24
Peak memory 273600 kb
Host smart-f219da87-031f-451e-af09-5c9d63e3e825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806552630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2806552630
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.963634800
Short name T100
Test name
Test status
Simulation time 55921402229 ps
CPU time 1209.67 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 07:01:28 PM PDT 24
Peak memory 288896 kb
Host smart-4fda6a5f-c120-41be-8b74-2fbd6db2e0e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963634800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.963634800
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1085792828
Short name T301
Test name
Test status
Simulation time 38626931493 ps
CPU time 381.08 seconds
Started Jun 24 06:41:00 PM PDT 24
Finished Jun 24 06:47:30 PM PDT 24
Peak memory 248444 kb
Host smart-6f0e151d-87cb-4509-92d3-ffdd7892941f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085792828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1085792828
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3256543490
Short name T656
Test name
Test status
Simulation time 719520822 ps
CPU time 10.76 seconds
Started Jun 24 06:41:04 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 254916 kb
Host smart-48e33fe2-a1f2-4186-941e-de5d7d31b646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565
43490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3256543490
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3616951133
Short name T525
Test name
Test status
Simulation time 328896517 ps
CPU time 28.02 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:41:46 PM PDT 24
Peak memory 255992 kb
Host smart-a72631f2-e5c6-4ef2-92e6-f7bc991f6d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36169
51133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3616951133
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2802231006
Short name T246
Test name
Test status
Simulation time 634165202 ps
CPU time 20.42 seconds
Started Jun 24 06:41:01 PM PDT 24
Finished Jun 24 06:41:31 PM PDT 24
Peak memory 247924 kb
Host smart-c9f1ad08-73f3-4528-941c-5567c94235bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28022
31006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2802231006
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.948563343
Short name T457
Test name
Test status
Simulation time 195467871 ps
CPU time 13.88 seconds
Started Jun 24 06:41:10 PM PDT 24
Finished Jun 24 06:41:32 PM PDT 24
Peak memory 256508 kb
Host smart-102cca76-f4a0-4c58-a1d7-a04db2c1abb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94856
3343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.948563343
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1489775283
Short name T225
Test name
Test status
Simulation time 43370836 ps
CPU time 4.45 seconds
Started Jun 24 06:41:17 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 249248 kb
Host smart-f4b13fc0-1350-4ce6-94f8-0104856ff885
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1489775283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1489775283
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4096781475
Short name T579
Test name
Test status
Simulation time 7377774761 ps
CPU time 928.75 seconds
Started Jun 24 06:41:13 PM PDT 24
Finished Jun 24 06:56:48 PM PDT 24
Peak memory 273184 kb
Host smart-bbc55f04-31e8-4824-8b03-05e931eb4747
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096781475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4096781475
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1272881115
Short name T202
Test name
Test status
Simulation time 821329309 ps
CPU time 23.72 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:41:42 PM PDT 24
Peak memory 249004 kb
Host smart-5204565e-f99d-4473-8588-3188a2b0d7a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1272881115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1272881115
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.366030561
Short name T683
Test name
Test status
Simulation time 13083505752 ps
CPU time 204.61 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 06:44:42 PM PDT 24
Peak memory 250228 kb
Host smart-d686deda-09a5-4a93-b908-5474864ead97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36603
0561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.366030561
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4080659643
Short name T555
Test name
Test status
Simulation time 2964343440 ps
CPU time 31.17 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:41:53 PM PDT 24
Peak memory 249188 kb
Host smart-36b270ec-2437-4c69-bb3d-9682245ddf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
59643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4080659643
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3664932223
Short name T335
Test name
Test status
Simulation time 46080557799 ps
CPU time 1027.98 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 06:58:25 PM PDT 24
Peak memory 273232 kb
Host smart-643b6559-d9e0-45b8-99ac-faddcf54472a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664932223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3664932223
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.382411753
Short name T466
Test name
Test status
Simulation time 131322377389 ps
CPU time 1945.61 seconds
Started Jun 24 06:41:10 PM PDT 24
Finished Jun 24 07:13:44 PM PDT 24
Peak memory 281872 kb
Host smart-3b97f234-7b69-43b4-afb4-e56a74daf780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382411753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.382411753
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4141724740
Short name T325
Test name
Test status
Simulation time 10502550581 ps
CPU time 381.59 seconds
Started Jun 24 06:41:21 PM PDT 24
Finished Jun 24 06:47:44 PM PDT 24
Peak memory 248832 kb
Host smart-d5cc4b23-466a-4a3e-8769-b542dc2ee7fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141724740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4141724740
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3293801297
Short name T374
Test name
Test status
Simulation time 477418854 ps
CPU time 32.96 seconds
Started Jun 24 06:41:16 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 249084 kb
Host smart-e4228cda-79e0-4092-9e86-b8910644af6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32938
01297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3293801297
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2535315127
Short name T119
Test name
Test status
Simulation time 473049633 ps
CPU time 22.66 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 06:41:40 PM PDT 24
Peak memory 249052 kb
Host smart-73b106fc-474e-4ca7-92be-7cb4fec73482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
15127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2535315127
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4234978932
Short name T276
Test name
Test status
Simulation time 536229380 ps
CPU time 34.57 seconds
Started Jun 24 06:41:12 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 255988 kb
Host smart-602e2c3d-433f-462a-ac67-b89652181221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
78932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4234978932
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4172174161
Short name T696
Test name
Test status
Simulation time 149378345 ps
CPU time 8.71 seconds
Started Jun 24 06:41:09 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 257020 kb
Host smart-52221335-3f46-4737-9808-e2863c005a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
74161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4172174161
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.948067933
Short name T130
Test name
Test status
Simulation time 78724228 ps
CPU time 3.27 seconds
Started Jun 24 06:41:07 PM PDT 24
Finished Jun 24 06:41:20 PM PDT 24
Peak memory 249232 kb
Host smart-1631bd82-ea31-4cd0-aa96-595bc14cfa38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=948067933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.948067933
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1320493239
Short name T232
Test name
Test status
Simulation time 9739951777 ps
CPU time 38.22 seconds
Started Jun 24 06:41:13 PM PDT 24
Finished Jun 24 06:41:58 PM PDT 24
Peak memory 249152 kb
Host smart-2d4d8d0f-94bf-473a-8d92-4b3eac36aced
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1320493239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1320493239
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.870058138
Short name T62
Test name
Test status
Simulation time 2298467210 ps
CPU time 47.61 seconds
Started Jun 24 06:41:14 PM PDT 24
Finished Jun 24 06:42:07 PM PDT 24
Peak memory 257232 kb
Host smart-87628377-34d3-4500-8900-f73a0ecfa668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87005
8138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.870058138
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2993593967
Short name T562
Test name
Test status
Simulation time 167924645 ps
CPU time 24.53 seconds
Started Jun 24 06:41:17 PM PDT 24
Finished Jun 24 06:41:45 PM PDT 24
Peak memory 249092 kb
Host smart-04ebf2ae-8178-43cd-b792-ca71038f1d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
93967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2993593967
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1624825643
Short name T483
Test name
Test status
Simulation time 9854083069 ps
CPU time 774.1 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 06:54:11 PM PDT 24
Peak memory 273364 kb
Host smart-09397cd2-1e33-42ac-b304-24b6249c53ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624825643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1624825643
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.458962648
Short name T516
Test name
Test status
Simulation time 8720827572 ps
CPU time 352.34 seconds
Started Jun 24 06:41:15 PM PDT 24
Finished Jun 24 06:47:12 PM PDT 24
Peak memory 248724 kb
Host smart-6de44686-f1f6-4090-9b52-05464a79a1fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458962648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.458962648
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2628704398
Short name T563
Test name
Test status
Simulation time 8972646840 ps
CPU time 69.43 seconds
Started Jun 24 06:41:08 PM PDT 24
Finished Jun 24 06:42:27 PM PDT 24
Peak memory 249328 kb
Host smart-51088c8b-88b3-43cf-b2e6-13c3eda98549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26287
04398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2628704398
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.294877029
Short name T515
Test name
Test status
Simulation time 1178794473 ps
CPU time 64.09 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:42:26 PM PDT 24
Peak memory 257424 kb
Host smart-c18cac7c-1ae6-4f24-b677-69e2bd91b3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487
7029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.294877029
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4157113168
Short name T463
Test name
Test status
Simulation time 121393074 ps
CPU time 4.54 seconds
Started Jun 24 06:41:20 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 239820 kb
Host smart-073750a9-cfe6-49cf-b059-15913608b0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
13168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4157113168
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2401711276
Short name T697
Test name
Test status
Simulation time 3086125059 ps
CPU time 27.66 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:41:49 PM PDT 24
Peak memory 248624 kb
Host smart-eeb9fc24-231f-4337-a31c-cbeb6c2d13b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
11276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2401711276
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.722405742
Short name T511
Test name
Test status
Simulation time 17825227750 ps
CPU time 1597.08 seconds
Started Jun 24 06:41:16 PM PDT 24
Finished Jun 24 07:07:58 PM PDT 24
Peak memory 289692 kb
Host smart-9e1c5cf6-e22d-4b13-980b-e945f717f0ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722405742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.722405742
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3919239090
Short name T223
Test name
Test status
Simulation time 33968739 ps
CPU time 3.51 seconds
Started Jun 24 06:41:10 PM PDT 24
Finished Jun 24 06:41:22 PM PDT 24
Peak memory 249272 kb
Host smart-d8e791bc-8ab5-4efe-a2cf-431defe0bd71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3919239090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3919239090
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.964005674
Short name T688
Test name
Test status
Simulation time 132690414081 ps
CPU time 2097.31 seconds
Started Jun 24 06:41:16 PM PDT 24
Finished Jun 24 07:16:18 PM PDT 24
Peak memory 287796 kb
Host smart-0c35fccf-ba02-4810-b415-9583b5d87c5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964005674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.964005674
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.223906747
Short name T458
Test name
Test status
Simulation time 2224874370 ps
CPU time 25.93 seconds
Started Jun 24 06:41:10 PM PDT 24
Finished Jun 24 06:41:44 PM PDT 24
Peak memory 249152 kb
Host smart-0be71e61-34a7-4e56-8bdf-6f658eefc413
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=223906747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.223906747
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2075187704
Short name T707
Test name
Test status
Simulation time 896618201 ps
CPU time 69.19 seconds
Started Jun 24 06:41:14 PM PDT 24
Finished Jun 24 06:42:29 PM PDT 24
Peak memory 249296 kb
Host smart-fc7e8a31-b831-4acc-b5e7-7ecd8f35ce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
87704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2075187704
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3775492624
Short name T488
Test name
Test status
Simulation time 1269180418 ps
CPU time 63.75 seconds
Started Jun 24 06:41:06 PM PDT 24
Finished Jun 24 06:42:20 PM PDT 24
Peak memory 255308 kb
Host smart-5cb506cf-e57e-458d-aba1-c00fcf0931be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754
92624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3775492624
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2787140916
Short name T348
Test name
Test status
Simulation time 53431691643 ps
CPU time 2946.04 seconds
Started Jun 24 06:41:11 PM PDT 24
Finished Jun 24 07:30:25 PM PDT 24
Peak memory 289776 kb
Host smart-146731f6-a45c-400b-89a9-d18cccce3d76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787140916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2787140916
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3553749390
Short name T427
Test name
Test status
Simulation time 36641403524 ps
CPU time 2174.79 seconds
Started Jun 24 06:41:20 PM PDT 24
Finished Jun 24 07:17:37 PM PDT 24
Peak memory 288916 kb
Host smart-12a66b42-239b-42da-a112-ba4dcb30c20f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553749390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3553749390
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1460314530
Short name T320
Test name
Test status
Simulation time 1978718699 ps
CPU time 85.21 seconds
Started Jun 24 06:41:14 PM PDT 24
Finished Jun 24 06:42:45 PM PDT 24
Peak memory 248764 kb
Host smart-2415067d-6734-48ad-b2e2-49acfb18aecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460314530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1460314530
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3359156504
Short name T446
Test name
Test status
Simulation time 74551497 ps
CPU time 8.61 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:41:30 PM PDT 24
Peak memory 253356 kb
Host smart-de9bd643-6cb7-4fd0-8d56-c0f1de6dab18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
56504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3359156504
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1113690256
Short name T529
Test name
Test status
Simulation time 104093400 ps
CPU time 7.44 seconds
Started Jun 24 06:41:22 PM PDT 24
Finished Jun 24 06:41:30 PM PDT 24
Peak memory 253600 kb
Host smart-a606d447-5a92-4afb-9aa6-f070f5542475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11136
90256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1113690256
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.81170786
Short name T75
Test name
Test status
Simulation time 1769501528 ps
CPU time 29.94 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:41:52 PM PDT 24
Peak memory 256872 kb
Host smart-2b813824-d9c5-4bfb-a4a7-7400a2f109c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81170
786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.81170786
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.738623006
Short name T390
Test name
Test status
Simulation time 745933866 ps
CPU time 28.8 seconds
Started Jun 24 06:41:19 PM PDT 24
Finished Jun 24 06:41:51 PM PDT 24
Peak memory 248536 kb
Host smart-1469323e-3355-4baf-9653-768f70b44896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73862
3006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.738623006
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3593573196
Short name T105
Test name
Test status
Simulation time 33358688914 ps
CPU time 1626.09 seconds
Started Jun 24 06:41:20 PM PDT 24
Finished Jun 24 07:08:28 PM PDT 24
Peak memory 289456 kb
Host smart-16a2b183-3613-4e6a-92d7-eeffa6b2785c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593573196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3593573196
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4196963035
Short name T224
Test name
Test status
Simulation time 83799399 ps
CPU time 2.93 seconds
Started Jun 24 06:41:30 PM PDT 24
Finished Jun 24 06:41:34 PM PDT 24
Peak memory 249276 kb
Host smart-1c30a23c-4c34-4bd1-a816-a9c1df1d8271
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4196963035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4196963035
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3130754253
Short name T462
Test name
Test status
Simulation time 26216069638 ps
CPU time 1381.04 seconds
Started Jun 24 06:41:31 PM PDT 24
Finished Jun 24 07:04:33 PM PDT 24
Peak memory 289104 kb
Host smart-4950bff2-16b2-4023-ba87-ba43d26ef469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130754253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3130754253
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2005939334
Short name T16
Test name
Test status
Simulation time 2018675485 ps
CPU time 23.96 seconds
Started Jun 24 06:41:29 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 249040 kb
Host smart-b86c23c2-2d82-4c29-8fb0-6551c1acc0ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2005939334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2005939334
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1649858893
Short name T468
Test name
Test status
Simulation time 22625976151 ps
CPU time 311.58 seconds
Started Jun 24 06:41:28 PM PDT 24
Finished Jun 24 06:46:40 PM PDT 24
Peak memory 251320 kb
Host smart-de3c2c42-189b-4cba-945b-2483f0ab85c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16498
58893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1649858893
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.995982983
Short name T496
Test name
Test status
Simulation time 3444111283 ps
CPU time 51.15 seconds
Started Jun 24 06:41:27 PM PDT 24
Finished Jun 24 06:42:19 PM PDT 24
Peak memory 255656 kb
Host smart-8965bff4-b2e9-47d6-84c2-33c9b136a277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99598
2983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.995982983
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1570232217
Short name T333
Test name
Test status
Simulation time 74718059326 ps
CPU time 2412.5 seconds
Started Jun 24 06:41:25 PM PDT 24
Finished Jun 24 07:21:38 PM PDT 24
Peak memory 289332 kb
Host smart-d03185ee-f42c-479b-b08e-a0c9b63f5955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570232217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1570232217
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2213414614
Short name T120
Test name
Test status
Simulation time 9990275694 ps
CPU time 1127.25 seconds
Started Jun 24 06:41:31 PM PDT 24
Finished Jun 24 07:00:19 PM PDT 24
Peak memory 285200 kb
Host smart-226b1dc4-24cd-4f3c-a7e6-3b5a68a26350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213414614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2213414614
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3213417478
Short name T7
Test name
Test status
Simulation time 5810561885 ps
CPU time 238.95 seconds
Started Jun 24 06:41:27 PM PDT 24
Finished Jun 24 06:45:27 PM PDT 24
Peak memory 248732 kb
Host smart-f98b34c3-33be-4245-a8d5-64c92c3a3c99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213417478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3213417478
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.161649421
Short name T695
Test name
Test status
Simulation time 170718884 ps
CPU time 3.94 seconds
Started Jun 24 06:41:31 PM PDT 24
Finished Jun 24 06:41:36 PM PDT 24
Peak memory 240840 kb
Host smart-fdeeec1d-a67c-4c4c-9820-aeb52226185a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16164
9421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.161649421
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4265083222
Short name T88
Test name
Test status
Simulation time 51800335 ps
CPU time 2.55 seconds
Started Jun 24 06:41:26 PM PDT 24
Finished Jun 24 06:41:30 PM PDT 24
Peak memory 239816 kb
Host smart-320b3109-43b9-476c-9e99-949cfe30157a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42650
83222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4265083222
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2914598361
Short name T637
Test name
Test status
Simulation time 1022103005 ps
CPU time 19.17 seconds
Started Jun 24 06:41:25 PM PDT 24
Finished Jun 24 06:41:46 PM PDT 24
Peak memory 249096 kb
Host smart-009810ee-8ed3-41d1-b8ce-3e09cf97071d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29145
98361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2914598361
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2136781559
Short name T43
Test name
Test status
Simulation time 312110352806 ps
CPU time 2904.34 seconds
Started Jun 24 06:41:26 PM PDT 24
Finished Jun 24 07:29:52 PM PDT 24
Peak memory 290036 kb
Host smart-0672de91-91fb-44a6-946b-f3a65f323284
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136781559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2136781559
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2179640860
Short name T226
Test name
Test status
Simulation time 452584619 ps
CPU time 4.13 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:40:30 PM PDT 24
Peak memory 249204 kb
Host smart-c03a87ae-62f1-4a88-8ad7-2f24798bb465
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2179640860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2179640860
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4267712392
Short name T600
Test name
Test status
Simulation time 19039201549 ps
CPU time 989.35 seconds
Started Jun 24 06:40:04 PM PDT 24
Finished Jun 24 06:56:35 PM PDT 24
Peak memory 272984 kb
Host smart-452c6d8f-9ebe-46fa-b504-128624e6aad2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267712392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4267712392
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2033745642
Short name T661
Test name
Test status
Simulation time 206344843 ps
CPU time 11.9 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:40:39 PM PDT 24
Peak memory 249036 kb
Host smart-f9fd627d-69b7-450a-af30-4b7dfab359c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2033745642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2033745642
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1845462501
Short name T520
Test name
Test status
Simulation time 1161097538 ps
CPU time 66.52 seconds
Started Jun 24 06:40:02 PM PDT 24
Finished Jun 24 06:41:10 PM PDT 24
Peak memory 249336 kb
Host smart-7931d1d0-5282-4879-9e25-a51bd164ea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18454
62501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1845462501
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1149765332
Short name T549
Test name
Test status
Simulation time 30512946 ps
CPU time 4.85 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 06:40:14 PM PDT 24
Peak memory 251556 kb
Host smart-38f8e8d8-3f03-4303-97d1-1461a97189db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
65332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1149765332
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1933206524
Short name T337
Test name
Test status
Simulation time 20101538576 ps
CPU time 1544.95 seconds
Started Jun 24 06:40:06 PM PDT 24
Finished Jun 24 07:05:55 PM PDT 24
Peak memory 288752 kb
Host smart-e4be87f8-74ec-4ce3-8654-821570698a49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933206524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1933206524
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.266677264
Short name T255
Test name
Test status
Simulation time 50058744347 ps
CPU time 2828.93 seconds
Started Jun 24 06:40:04 PM PDT 24
Finished Jun 24 07:27:15 PM PDT 24
Peak memory 281492 kb
Host smart-6c099d85-37f0-4caa-b7a6-5cd509b52c17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266677264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.266677264
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3356478590
Short name T682
Test name
Test status
Simulation time 15038665852 ps
CPU time 161.46 seconds
Started Jun 24 06:40:04 PM PDT 24
Finished Jun 24 06:42:47 PM PDT 24
Peak memory 248724 kb
Host smart-3de5ed7f-0fbb-46cd-b1d7-525179255322
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356478590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3356478590
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2049008620
Short name T450
Test name
Test status
Simulation time 211170336 ps
CPU time 17.07 seconds
Started Jun 24 06:39:57 PM PDT 24
Finished Jun 24 06:40:16 PM PDT 24
Peak memory 249112 kb
Host smart-193e35e0-5523-4647-aad5-c18d22c4d920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
08620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2049008620
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2539598842
Short name T394
Test name
Test status
Simulation time 165612742 ps
CPU time 15.37 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:20 PM PDT 24
Peak memory 249304 kb
Host smart-ce017ea1-899c-4fc6-a36a-ab96388b324d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25395
98842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2539598842
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1760258317
Short name T385
Test name
Test status
Simulation time 405709367 ps
CPU time 8.18 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:12 PM PDT 24
Peak memory 250268 kb
Host smart-0b835ec4-d58d-4df4-b9b2-19d4b7eef6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
58317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1760258317
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1111119702
Short name T646
Test name
Test status
Simulation time 156670455 ps
CPU time 13.08 seconds
Started Jun 24 06:40:03 PM PDT 24
Finished Jun 24 06:40:18 PM PDT 24
Peak memory 249052 kb
Host smart-fa989dac-a93c-4ca8-a83a-06f6417e3f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
19702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1111119702
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1909476564
Short name T60
Test name
Test status
Simulation time 39001007274 ps
CPU time 2295.83 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 07:18:41 PM PDT 24
Peak memory 283140 kb
Host smart-903e12a1-025c-4726-ac8f-2c7ce1c37c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909476564 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1909476564
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2767644315
Short name T580
Test name
Test status
Simulation time 66575800739 ps
CPU time 1098.86 seconds
Started Jun 24 06:41:27 PM PDT 24
Finished Jun 24 06:59:47 PM PDT 24
Peak memory 265508 kb
Host smart-9e0d87e9-d145-4526-bb7a-d61851c68cc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767644315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2767644315
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2712507491
Short name T641
Test name
Test status
Simulation time 2930895882 ps
CPU time 90.67 seconds
Started Jun 24 06:41:25 PM PDT 24
Finished Jun 24 06:42:57 PM PDT 24
Peak memory 257296 kb
Host smart-55e3c0b6-86ce-4cb2-afd6-c8e09c108076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27125
07491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2712507491
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3882192877
Short name T81
Test name
Test status
Simulation time 2688469222 ps
CPU time 40.06 seconds
Started Jun 24 06:41:27 PM PDT 24
Finished Jun 24 06:42:08 PM PDT 24
Peak memory 249184 kb
Host smart-6cc9fc25-fc2c-433b-9ce9-2d27ad74511b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
92877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3882192877
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1332529834
Short name T108
Test name
Test status
Simulation time 9181808161 ps
CPU time 730.61 seconds
Started Jun 24 06:41:30 PM PDT 24
Finished Jun 24 06:53:41 PM PDT 24
Peak memory 265628 kb
Host smart-5ef89ac6-f91c-4559-8e3f-a6cde1fcd4bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332529834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1332529834
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2697797414
Short name T205
Test name
Test status
Simulation time 6593178105 ps
CPU time 617.94 seconds
Started Jun 24 06:41:26 PM PDT 24
Finished Jun 24 06:51:45 PM PDT 24
Peak memory 265512 kb
Host smart-d424a876-15d1-4fcd-84f0-ba735573e741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697797414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2697797414
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.15411154
Short name T619
Test name
Test status
Simulation time 4273639678 ps
CPU time 168.39 seconds
Started Jun 24 06:41:26 PM PDT 24
Finished Jun 24 06:44:16 PM PDT 24
Peak memory 248660 kb
Host smart-63128921-729e-4ce4-aa51-9e21554322eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15411154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.15411154
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1070921437
Short name T537
Test name
Test status
Simulation time 108011116 ps
CPU time 5.03 seconds
Started Jun 24 06:41:27 PM PDT 24
Finished Jun 24 06:41:33 PM PDT 24
Peak memory 249020 kb
Host smart-d307d246-9cc3-475d-88d1-334819b8903d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709
21437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1070921437
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.989691110
Short name T658
Test name
Test status
Simulation time 411825881 ps
CPU time 26.22 seconds
Started Jun 24 06:41:26 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 256164 kb
Host smart-61204ce1-0372-47ea-9fed-9a56dad02b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98969
1110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.989691110
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.750285873
Short name T532
Test name
Test status
Simulation time 264005696 ps
CPU time 33.47 seconds
Started Jun 24 06:41:31 PM PDT 24
Finished Jun 24 06:42:05 PM PDT 24
Peak memory 248052 kb
Host smart-49f50e68-0f90-4e4b-b228-70f0943d2238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75028
5873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.750285873
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3829717382
Short name T20
Test name
Test status
Simulation time 476590621 ps
CPU time 32.45 seconds
Started Jun 24 06:41:33 PM PDT 24
Finished Jun 24 06:42:06 PM PDT 24
Peak memory 249104 kb
Host smart-020fb709-f704-427c-9332-c2731de4c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38297
17382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3829717382
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4144904829
Short name T506
Test name
Test status
Simulation time 239652548 ps
CPU time 23.97 seconds
Started Jun 24 06:41:28 PM PDT 24
Finished Jun 24 06:41:53 PM PDT 24
Peak memory 256524 kb
Host smart-8d2802e6-eaa6-40fc-a96a-b19c08678864
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144904829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4144904829
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1266822091
Short name T182
Test name
Test status
Simulation time 84751397006 ps
CPU time 8945.94 seconds
Started Jun 24 06:41:34 PM PDT 24
Finished Jun 24 09:10:42 PM PDT 24
Peak memory 353980 kb
Host smart-286a5c30-26ee-4d49-ac63-dd3b6236d35c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266822091 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1266822091
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1420098500
Short name T98
Test name
Test status
Simulation time 17279698011 ps
CPU time 1561.32 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 07:07:50 PM PDT 24
Peak memory 290120 kb
Host smart-7adfe515-af25-4b71-965d-d2c9b6de1fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420098500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1420098500
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4035698795
Short name T63
Test name
Test status
Simulation time 314657990 ps
CPU time 30.73 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 06:42:19 PM PDT 24
Peak memory 256508 kb
Host smart-b5bbef6a-b993-4c22-bc7a-4513a857e474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
98795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4035698795
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2865099654
Short name T487
Test name
Test status
Simulation time 138799023 ps
CPU time 12.56 seconds
Started Jun 24 06:41:50 PM PDT 24
Finished Jun 24 06:42:03 PM PDT 24
Peak memory 255148 kb
Host smart-4b260551-f819-4393-ad70-dc5d5d098072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28650
99654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2865099654
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2887248512
Short name T328
Test name
Test status
Simulation time 11706366712 ps
CPU time 1001.01 seconds
Started Jun 24 06:41:56 PM PDT 24
Finished Jun 24 06:58:38 PM PDT 24
Peak memory 273728 kb
Host smart-9c65a0d0-1eab-4343-aee7-743d1eb43702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887248512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2887248512
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.261383184
Short name T203
Test name
Test status
Simulation time 10503237956 ps
CPU time 871.23 seconds
Started Jun 24 06:41:49 PM PDT 24
Finished Jun 24 06:56:21 PM PDT 24
Peak memory 273192 kb
Host smart-86d9ccef-6c2e-4e96-92fa-59b20e1093f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261383184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.261383184
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1303771480
Short name T616
Test name
Test status
Simulation time 22439616376 ps
CPU time 445.53 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 06:49:14 PM PDT 24
Peak memory 248296 kb
Host smart-4896625d-c5d1-406a-bd5d-099286161c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303771480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1303771480
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.897642340
Short name T647
Test name
Test status
Simulation time 169743553 ps
CPU time 20.11 seconds
Started Jun 24 06:41:31 PM PDT 24
Finished Jun 24 06:41:52 PM PDT 24
Peak memory 249296 kb
Host smart-30b01b46-79e1-46f0-9cae-84aa5674d602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89764
2340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.897642340
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.60102385
Short name T634
Test name
Test status
Simulation time 2716436893 ps
CPU time 71.19 seconds
Started Jun 24 06:41:46 PM PDT 24
Finished Jun 24 06:42:58 PM PDT 24
Peak memory 249100 kb
Host smart-eddcaad0-1bc8-4560-afb4-2e14b663df46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60102
385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.60102385
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.215565458
Short name T375
Test name
Test status
Simulation time 1020741572 ps
CPU time 63.13 seconds
Started Jun 24 06:41:45 PM PDT 24
Finished Jun 24 06:42:49 PM PDT 24
Peak memory 255432 kb
Host smart-e31cc798-1046-4f57-9049-6f070330f406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
5458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.215565458
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.439632589
Short name T604
Test name
Test status
Simulation time 901482151 ps
CPU time 25.78 seconds
Started Jun 24 06:41:30 PM PDT 24
Finished Jun 24 06:41:57 PM PDT 24
Peak memory 249092 kb
Host smart-1d705940-a2db-4b62-87b6-ce3e81924938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43963
2589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.439632589
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2753123302
Short name T587
Test name
Test status
Simulation time 60225608280 ps
CPU time 1792.4 seconds
Started Jun 24 06:41:50 PM PDT 24
Finished Jun 24 07:11:43 PM PDT 24
Peak memory 273024 kb
Host smart-bc0686bb-d2e3-436f-8618-f1bb8547db94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753123302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2753123302
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.18156750
Short name T508
Test name
Test status
Simulation time 2223640181 ps
CPU time 71.46 seconds
Started Jun 24 06:41:45 PM PDT 24
Finished Jun 24 06:42:57 PM PDT 24
Peak memory 249212 kb
Host smart-91cec129-f017-4b27-bcda-b15c1f84d297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.18156750
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1527287542
Short name T80
Test name
Test status
Simulation time 1214544425 ps
CPU time 40.05 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 06:42:28 PM PDT 24
Peak memory 249072 kb
Host smart-2b10b982-ebf4-4a16-90c1-debee89d049c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272
87542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1527287542
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1576796379
Short name T326
Test name
Test status
Simulation time 24222295380 ps
CPU time 1062.9 seconds
Started Jun 24 06:41:46 PM PDT 24
Finished Jun 24 06:59:30 PM PDT 24
Peak memory 273768 kb
Host smart-4ae1b7d0-2cf2-4985-9ad9-7b22dd96c890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576796379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1576796379
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1284212636
Short name T252
Test name
Test status
Simulation time 76915992772 ps
CPU time 2373.07 seconds
Started Jun 24 06:41:50 PM PDT 24
Finished Jun 24 07:21:24 PM PDT 24
Peak memory 282352 kb
Host smart-bf82d965-bd4d-457b-b96f-16a75a01ff14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284212636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1284212636
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3090438157
Short name T332
Test name
Test status
Simulation time 3581221307 ps
CPU time 141.38 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 06:44:09 PM PDT 24
Peak memory 248848 kb
Host smart-a1ca9e04-89bf-45cc-ae31-1bb99dc6abe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090438157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3090438157
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.577028701
Short name T657
Test name
Test status
Simulation time 1710137348 ps
CPU time 37.9 seconds
Started Jun 24 06:41:48 PM PDT 24
Finished Jun 24 06:42:26 PM PDT 24
Peak memory 249068 kb
Host smart-8da434eb-bbe7-4c65-8f25-f395204b8620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57702
8701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.577028701
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4160162040
Short name T391
Test name
Test status
Simulation time 158582203 ps
CPU time 4 seconds
Started Jun 24 06:41:46 PM PDT 24
Finished Jun 24 06:41:50 PM PDT 24
Peak memory 239716 kb
Host smart-0c62944b-38b1-482c-8d2b-c5b8f9c7d908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41601
62040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4160162040
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.928254665
Short name T400
Test name
Test status
Simulation time 1180413323 ps
CPU time 27.49 seconds
Started Jun 24 06:41:46 PM PDT 24
Finished Jun 24 06:42:15 PM PDT 24
Peak memory 249096 kb
Host smart-4ae5b2ee-6557-45d4-ab62-af837bcc51b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92825
4665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.928254665
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.743877935
Short name T530
Test name
Test status
Simulation time 310153954486 ps
CPU time 2840.38 seconds
Started Jun 24 06:41:46 PM PDT 24
Finished Jun 24 07:29:08 PM PDT 24
Peak memory 289980 kb
Host smart-1ccfac51-dd65-410d-aa8f-cc0e55fe7fea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743877935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.743877935
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3311378076
Short name T444
Test name
Test status
Simulation time 65569605163 ps
CPU time 1159.83 seconds
Started Jun 24 06:42:04 PM PDT 24
Finished Jun 24 07:01:25 PM PDT 24
Peak memory 265580 kb
Host smart-54013a69-e14a-4ba9-85eb-3f1e050c7428
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311378076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3311378076
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1359407823
Short name T528
Test name
Test status
Simulation time 7469760049 ps
CPU time 116.62 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:44:05 PM PDT 24
Peak memory 257356 kb
Host smart-1a272550-83a9-40f7-ae53-82eb001157f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
07823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1359407823
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1842519473
Short name T575
Test name
Test status
Simulation time 189735074 ps
CPU time 13.36 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:42:21 PM PDT 24
Peak memory 252292 kb
Host smart-9f30017c-063c-4b96-ba7e-39738fc09c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18425
19473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1842519473
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.949498353
Short name T110
Test name
Test status
Simulation time 14564459151 ps
CPU time 1300.68 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 07:03:49 PM PDT 24
Peak memory 289620 kb
Host smart-c253820b-5e30-4138-8e81-b5c640f688cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949498353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.949498353
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1707120677
Short name T490
Test name
Test status
Simulation time 18421200522 ps
CPU time 682.95 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:53:30 PM PDT 24
Peak memory 273240 kb
Host smart-1dffcb77-9958-4611-98bc-5df08fe1dfeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707120677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1707120677
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3949685853
Short name T655
Test name
Test status
Simulation time 5858040695 ps
CPU time 243.66 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:46:10 PM PDT 24
Peak memory 248812 kb
Host smart-303399ec-5847-41f0-bd9f-5da3bff4ee19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949685853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3949685853
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.777501838
Short name T187
Test name
Test status
Simulation time 2047711645 ps
CPU time 59.56 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:43:07 PM PDT 24
Peak memory 256720 kb
Host smart-315ed1bd-6ad1-45af-8c0b-5cb0de56d297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77750
1838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.777501838
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1171683107
Short name T233
Test name
Test status
Simulation time 1595871802 ps
CPU time 23.04 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:42:30 PM PDT 24
Peak memory 249008 kb
Host smart-dae535a7-f22f-428d-b601-7a9f43da6ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
83107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1171683107
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4096499170
Short name T401
Test name
Test status
Simulation time 4129226078 ps
CPU time 32.96 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:42:40 PM PDT 24
Peak memory 256016 kb
Host smart-4ffcee8d-213c-45a2-be28-feb9fba4a11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
99170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4096499170
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4196457874
Short name T478
Test name
Test status
Simulation time 259962991 ps
CPU time 17.12 seconds
Started Jun 24 06:41:47 PM PDT 24
Finished Jun 24 06:42:05 PM PDT 24
Peak memory 249080 kb
Host smart-7a8c8a58-bcfe-43a8-aa1b-2115ec27c850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41964
57874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4196457874
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1931296097
Short name T267
Test name
Test status
Simulation time 88457832206 ps
CPU time 2186.77 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 07:18:33 PM PDT 24
Peak memory 298108 kb
Host smart-963fb68e-c6ec-4cfa-8753-ca65087ea8aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931296097 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1931296097
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2433919472
Short name T526
Test name
Test status
Simulation time 12407115687 ps
CPU time 1179.7 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 07:01:48 PM PDT 24
Peak memory 286660 kb
Host smart-467cd818-78b6-4c08-9465-37ded8456a20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433919472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2433919472
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3638372773
Short name T416
Test name
Test status
Simulation time 746622656 ps
CPU time 58.47 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:43:06 PM PDT 24
Peak memory 257368 kb
Host smart-91e02dd7-5aa2-438d-9a21-3f5311ba58d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
72773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3638372773
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3650463313
Short name T78
Test name
Test status
Simulation time 1002506326 ps
CPU time 12.75 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:21 PM PDT 24
Peak memory 249468 kb
Host smart-b8b09e12-c9a5-4d24-a724-bbd7c2ed3191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
63313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3650463313
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3598748324
Short name T708
Test name
Test status
Simulation time 47450869959 ps
CPU time 2968.61 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 07:31:36 PM PDT 24
Peak memory 289508 kb
Host smart-83db8244-192c-4459-b803-81d7e838821d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598748324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3598748324
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.812496391
Short name T690
Test name
Test status
Simulation time 41369129351 ps
CPU time 448.73 seconds
Started Jun 24 06:42:04 PM PDT 24
Finished Jun 24 06:49:34 PM PDT 24
Peak memory 248728 kb
Host smart-3628a5ae-6762-430d-8778-698225db7557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812496391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.812496391
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.200684030
Short name T504
Test name
Test status
Simulation time 884366360 ps
CPU time 18.24 seconds
Started Jun 24 06:42:04 PM PDT 24
Finished Jun 24 06:42:23 PM PDT 24
Peak memory 249036 kb
Host smart-d1e593af-eae7-4dd5-b58f-515696010ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
4030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.200684030
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.690358054
Short name T79
Test name
Test status
Simulation time 334581997 ps
CPU time 23.28 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:31 PM PDT 24
Peak memory 249464 kb
Host smart-b554f55a-8441-4ece-9b11-5b86c859a642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69035
8054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.690358054
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1642949317
Short name T648
Test name
Test status
Simulation time 346066386 ps
CPU time 25.95 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:34 PM PDT 24
Peak memory 249056 kb
Host smart-ab096c18-4d5b-451e-bb9f-6ba3c2ffbf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16429
49317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1642949317
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2902337494
Short name T527
Test name
Test status
Simulation time 3971542793 ps
CPU time 120.44 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:44:08 PM PDT 24
Peak memory 257364 kb
Host smart-eaf38bf6-7b1b-4f9c-9b8d-7490327ca9c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902337494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2902337494
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3768025483
Short name T103
Test name
Test status
Simulation time 55701231251 ps
CPU time 1229.13 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 07:02:38 PM PDT 24
Peak memory 289220 kb
Host smart-d38e010e-74e4-4183-ae51-17972d18cf80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768025483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3768025483
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.836711017
Short name T422
Test name
Test status
Simulation time 8368314331 ps
CPU time 190.9 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:45:20 PM PDT 24
Peak memory 257272 kb
Host smart-e5bfa557-a1c1-4def-a35a-8da0d0586197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83671
1017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.836711017
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2464263691
Short name T566
Test name
Test status
Simulation time 446638902 ps
CPU time 20.74 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:29 PM PDT 24
Peak memory 249124 kb
Host smart-71783c2c-0563-4c4a-992f-d13e9cb4a43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
63691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2464263691
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.384543194
Short name T341
Test name
Test status
Simulation time 17317418853 ps
CPU time 1211.5 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 07:02:19 PM PDT 24
Peak memory 273728 kb
Host smart-06af44c4-8cde-49c4-bd51-0e459881cccb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384543194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.384543194
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.499631688
Short name T583
Test name
Test status
Simulation time 15132253817 ps
CPU time 1425.65 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 07:05:54 PM PDT 24
Peak memory 287768 kb
Host smart-d599e2e8-6469-4675-ac2c-0e6792300716
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499631688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.499631688
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1948579672
Short name T9
Test name
Test status
Simulation time 5947411009 ps
CPU time 223.36 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:45:50 PM PDT 24
Peak memory 248448 kb
Host smart-9d55a077-5e3d-430a-b07e-88d71614aba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948579672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1948579672
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2129262275
Short name T428
Test name
Test status
Simulation time 1802471700 ps
CPU time 11.42 seconds
Started Jun 24 06:42:05 PM PDT 24
Finished Jun 24 06:42:18 PM PDT 24
Peak memory 249036 kb
Host smart-1e2bcf95-6405-4d55-8829-7f45c0574db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21292
62275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2129262275
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.21562104
Short name T554
Test name
Test status
Simulation time 131097532 ps
CPU time 10.64 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:19 PM PDT 24
Peak memory 255320 kb
Host smart-a55550be-d0d0-4973-9a02-fdbaf0e3c581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.21562104
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1087621030
Short name T694
Test name
Test status
Simulation time 113665540 ps
CPU time 17.21 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:26 PM PDT 24
Peak memory 249444 kb
Host smart-944c7a71-5b60-4e61-90fe-ea81bed0672b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10876
21030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1087621030
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3536299489
Short name T379
Test name
Test status
Simulation time 1316784888 ps
CPU time 39.63 seconds
Started Jun 24 06:42:06 PM PDT 24
Finished Jun 24 06:42:48 PM PDT 24
Peak memory 257224 kb
Host smart-c183e997-a29e-4e3d-9d1f-7056fe8f9602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362
99489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3536299489
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.92303997
Short name T630
Test name
Test status
Simulation time 991690961 ps
CPU time 66.35 seconds
Started Jun 24 06:42:04 PM PDT 24
Finished Jun 24 06:43:12 PM PDT 24
Peak memory 257296 kb
Host smart-8b359416-906d-4bb4-9010-97d17fb9b7e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92303997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_hand
ler_stress_all.92303997
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.498787357
Short name T523
Test name
Test status
Simulation time 611051212 ps
CPU time 71.66 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:43:39 PM PDT 24
Peak memory 249160 kb
Host smart-e3418eb2-69cb-4350-a00d-f90a596755fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49878
7357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.498787357
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2983150945
Short name T387
Test name
Test status
Simulation time 44798820 ps
CPU time 5.59 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 06:42:32 PM PDT 24
Peak memory 251544 kb
Host smart-34379de5-2a65-459b-a923-4da5e9bc9b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29831
50945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2983150945
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4079865580
Short name T89
Test name
Test status
Simulation time 12693959886 ps
CPU time 1090.72 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 07:00:38 PM PDT 24
Peak memory 289228 kb
Host smart-73b5a293-346f-47b6-8822-7a53f80b8ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079865580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4079865580
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.878418981
Short name T271
Test name
Test status
Simulation time 96670919181 ps
CPU time 1603.1 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 07:09:09 PM PDT 24
Peak memory 273668 kb
Host smart-e844930f-db60-48bb-83ba-955e71dc78b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878418981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.878418981
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2553817432
Short name T300
Test name
Test status
Simulation time 3857268342 ps
CPU time 165.08 seconds
Started Jun 24 06:42:28 PM PDT 24
Finished Jun 24 06:45:15 PM PDT 24
Peak memory 247564 kb
Host smart-36d62b56-1b38-4ddd-9d73-4bee5db689a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553817432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2553817432
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.402381939
Short name T643
Test name
Test status
Simulation time 662754569 ps
CPU time 30.31 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 06:42:53 PM PDT 24
Peak memory 250104 kb
Host smart-049d12b1-f4a7-43d3-8688-bd0e9a2bbf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40238
1939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.402381939
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4144143056
Short name T665
Test name
Test status
Simulation time 1173768878 ps
CPU time 26.77 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 06:42:56 PM PDT 24
Peak memory 255984 kb
Host smart-e71bab8c-8f92-40e2-a4a6-de99484d8717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
43056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4144143056
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3782007234
Short name T284
Test name
Test status
Simulation time 3489794040 ps
CPU time 50.12 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 06:43:19 PM PDT 24
Peak memory 249180 kb
Host smart-76374b77-4b3b-4405-98f7-946ba4caa9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37820
07234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3782007234
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1750665149
Short name T495
Test name
Test status
Simulation time 3575507551 ps
CPU time 34.6 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:42:59 PM PDT 24
Peak memory 249160 kb
Host smart-d492fd77-cad5-4faa-98a0-dac1667edc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
65149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1750665149
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2973911456
Short name T93
Test name
Test status
Simulation time 225506404797 ps
CPU time 6033.12 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 08:23:00 PM PDT 24
Peak memory 347500 kb
Host smart-b2a66c4e-3d88-47b5-b6d6-3b46f737e296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973911456 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2973911456
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1367300060
Short name T596
Test name
Test status
Simulation time 6017700498 ps
CPU time 201.43 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:45:46 PM PDT 24
Peak memory 256548 kb
Host smart-0b1bd5e8-1005-42cd-a3d8-dc30118a8a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13673
00060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1367300060
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.237755697
Short name T448
Test name
Test status
Simulation time 623339470 ps
CPU time 41.47 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 06:43:05 PM PDT 24
Peak memory 256552 kb
Host smart-f3bda2fb-7c96-49d5-a43d-dc6f923b8d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
5697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.237755697
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3573802210
Short name T206
Test name
Test status
Simulation time 76899508194 ps
CPU time 2984.97 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 07:32:08 PM PDT 24
Peak memory 289220 kb
Host smart-ef99db9a-4f9e-4c6a-bd4e-4326621bb9f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573802210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3573802210
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3861199449
Short name T234
Test name
Test status
Simulation time 41050078862 ps
CPU time 940.98 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 06:58:07 PM PDT 24
Peak memory 270988 kb
Host smart-984e4ab9-c816-44aa-b2e3-88897da778b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861199449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3861199449
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.433007430
Short name T316
Test name
Test status
Simulation time 48632743107 ps
CPU time 520.43 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:51:05 PM PDT 24
Peak memory 248724 kb
Host smart-8baa87e6-9ef0-47b8-b6fe-e8022ab9f057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433007430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.433007430
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2336503987
Short name T461
Test name
Test status
Simulation time 918380880 ps
CPU time 20.24 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:42:47 PM PDT 24
Peak memory 249116 kb
Host smart-b3ef08ac-cea9-4bc5-a9a5-4c935a004048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23365
03987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2336503987
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4025161196
Short name T543
Test name
Test status
Simulation time 679144124 ps
CPU time 8.92 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 06:42:37 PM PDT 24
Peak memory 249052 kb
Host smart-05aee766-8a70-46ca-9349-64d74242718c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40251
61196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4025161196
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2467566168
Short name T293
Test name
Test status
Simulation time 1088383743 ps
CPU time 26.34 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:42:51 PM PDT 24
Peak memory 256136 kb
Host smart-8fe485db-a71c-4ca5-988e-7267c54b8ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24675
66168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2467566168
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3154353180
Short name T538
Test name
Test status
Simulation time 595648377 ps
CPU time 10.69 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 06:42:39 PM PDT 24
Peak memory 249036 kb
Host smart-29071292-ebf9-46ca-80e7-40168c173521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
53180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3154353180
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3092937513
Short name T584
Test name
Test status
Simulation time 24022590002 ps
CPU time 1537.46 seconds
Started Jun 24 06:42:28 PM PDT 24
Finished Jun 24 07:08:08 PM PDT 24
Peak memory 282736 kb
Host smart-e37bac87-0c74-4e5d-98e7-56e39e014573
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092937513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3092937513
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.423169154
Short name T181
Test name
Test status
Simulation time 104167780131 ps
CPU time 5913.87 seconds
Started Jun 24 06:42:28 PM PDT 24
Finished Jun 24 08:21:04 PM PDT 24
Peak memory 339072 kb
Host smart-1a6fae7f-bba9-4d11-8b7c-abfa8cfc7d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423169154 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.423169154
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2158801965
Short name T482
Test name
Test status
Simulation time 8920520736 ps
CPU time 246.49 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 06:46:33 PM PDT 24
Peak memory 251548 kb
Host smart-6bf6e5b5-cafe-4c16-a215-feaabcfb334b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
01965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2158801965
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1287747030
Short name T474
Test name
Test status
Simulation time 635273585 ps
CPU time 20.88 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:42:45 PM PDT 24
Peak memory 256220 kb
Host smart-9c527d78-0fda-4aa8-8940-2dc2e2034eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
47030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1287747030
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3931659132
Short name T268
Test name
Test status
Simulation time 190859316985 ps
CPU time 1633.4 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 07:09:36 PM PDT 24
Peak memory 273668 kb
Host smart-8f1eb7a6-76fe-4796-b97e-e3bdd949a6ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931659132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3931659132
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.629987200
Short name T585
Test name
Test status
Simulation time 27447717514 ps
CPU time 772.77 seconds
Started Jun 24 06:42:28 PM PDT 24
Finished Jun 24 06:55:23 PM PDT 24
Peak memory 273744 kb
Host smart-aa1efe92-b3d4-4e3e-928c-0f94e40cf086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629987200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.629987200
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3022657445
Short name T386
Test name
Test status
Simulation time 2886682613 ps
CPU time 17.83 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 06:42:45 PM PDT 24
Peak memory 249080 kb
Host smart-4badc2f0-5408-4d11-924c-3278ef717297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
57445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3022657445
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2624186887
Short name T69
Test name
Test status
Simulation time 714184324 ps
CPU time 8.24 seconds
Started Jun 24 06:42:29 PM PDT 24
Finished Jun 24 06:42:39 PM PDT 24
Peak memory 247904 kb
Host smart-e40facec-df21-44dc-94ea-57a45b968686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26241
86887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2624186887
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.19672877
Short name T407
Test name
Test status
Simulation time 49488684 ps
CPU time 2.65 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:42:27 PM PDT 24
Peak memory 240816 kb
Host smart-242b1e5e-c423-4239-9072-2a15bfa91647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.19672877
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4241415844
Short name T49
Test name
Test status
Simulation time 80644388822 ps
CPU time 5046.76 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 08:06:31 PM PDT 24
Peak memory 298212 kb
Host smart-7b43a36e-875c-4147-a6d3-0f1ebe015d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241415844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4241415844
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3822118812
Short name T183
Test name
Test status
Simulation time 26277305434 ps
CPU time 1593.32 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 07:08:59 PM PDT 24
Peak memory 273728 kb
Host smart-12333120-849b-4a33-87c7-7c1489c2d1d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822118812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3822118812
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3702906898
Short name T392
Test name
Test status
Simulation time 25662539035 ps
CPU time 200.16 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 06:45:45 PM PDT 24
Peak memory 257488 kb
Host smart-78d6008b-4ab2-490e-97c8-bf23f0f2b169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
06898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3702906898
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2167683932
Short name T500
Test name
Test status
Simulation time 1093547209 ps
CPU time 30.37 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:42:58 PM PDT 24
Peak memory 249044 kb
Host smart-c67ae0b1-33bd-47b2-b84e-fa714c423dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21676
83932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2167683932
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.249532189
Short name T436
Test name
Test status
Simulation time 78813643737 ps
CPU time 2158.64 seconds
Started Jun 24 06:42:21 PM PDT 24
Finished Jun 24 07:18:21 PM PDT 24
Peak memory 287896 kb
Host smart-d6a97df6-cc2a-4bb6-bd9b-e2f3956504fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249532189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.249532189
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.595513227
Short name T299
Test name
Test status
Simulation time 20892523027 ps
CPU time 229.62 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:46:15 PM PDT 24
Peak memory 248660 kb
Host smart-79cb61ec-01f8-49c3-ae6c-c241af7552bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595513227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.595513227
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4288314716
Short name T501
Test name
Test status
Simulation time 732232050 ps
CPU time 50.57 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:43:18 PM PDT 24
Peak memory 257292 kb
Host smart-54b25403-afcc-4ca4-bc4d-e7000dab7fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883
14716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4288314716
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1643018053
Short name T502
Test name
Test status
Simulation time 524306283 ps
CPU time 26.55 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 06:42:50 PM PDT 24
Peak memory 248008 kb
Host smart-44a7b9cb-3d3b-44fb-b891-3d6b66e754ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
18053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1643018053
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3313521708
Short name T270
Test name
Test status
Simulation time 1031717245 ps
CPU time 24.83 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 06:42:51 PM PDT 24
Peak memory 249104 kb
Host smart-62f0d5a8-1f78-473e-9816-eaabc0ff4658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
21708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3313521708
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2002610685
Short name T216
Test name
Test status
Simulation time 52837651 ps
CPU time 3.18 seconds
Started Jun 24 06:40:27 PM PDT 24
Finished Jun 24 06:40:32 PM PDT 24
Peak memory 249112 kb
Host smart-dbeb1ac4-de38-4d21-bc11-4ff8fb89c641
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2002610685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2002610685
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2174017902
Short name T618
Test name
Test status
Simulation time 14872946743 ps
CPU time 921.06 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:55:46 PM PDT 24
Peak memory 271196 kb
Host smart-7d2e64a0-5e61-4285-a36a-77714fd4acdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174017902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2174017902
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1369638548
Short name T238
Test name
Test status
Simulation time 1264459366 ps
CPU time 53.09 seconds
Started Jun 24 06:40:26 PM PDT 24
Finished Jun 24 06:41:21 PM PDT 24
Peak memory 249188 kb
Host smart-5c517e11-b5ca-49e9-91cf-a1133b42beb3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1369638548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1369638548
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2316322100
Short name T397
Test name
Test status
Simulation time 371399065 ps
CPU time 13.87 seconds
Started Jun 24 06:40:21 PM PDT 24
Finished Jun 24 06:40:36 PM PDT 24
Peak memory 249248 kb
Host smart-21bc9edf-149c-4ca8-ab29-043ecae70409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
22100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2316322100
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2062618424
Short name T282
Test name
Test status
Simulation time 3187201280 ps
CPU time 51.41 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:41:17 PM PDT 24
Peak memory 256044 kb
Host smart-d92a922d-7e0e-4207-9c7d-6f2fac8f0369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
18424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2062618424
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.315634899
Short name T645
Test name
Test status
Simulation time 113070722408 ps
CPU time 1488.7 seconds
Started Jun 24 06:40:28 PM PDT 24
Finished Jun 24 07:05:18 PM PDT 24
Peak memory 288744 kb
Host smart-357b2c6b-dc71-4097-ab52-76c89aa44357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315634899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.315634899
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2599190678
Short name T676
Test name
Test status
Simulation time 104043829100 ps
CPU time 1661.07 seconds
Started Jun 24 06:40:29 PM PDT 24
Finished Jun 24 07:08:11 PM PDT 24
Peak memory 273704 kb
Host smart-41d3ddca-b17f-4e4d-9524-d9d75ca98557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599190678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2599190678
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1497404499
Short name T305
Test name
Test status
Simulation time 10654965431 ps
CPU time 418.37 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:47:26 PM PDT 24
Peak memory 248740 kb
Host smart-27f32e9a-1cbb-4a33-b67b-e40b3fb409bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497404499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1497404499
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.133332505
Short name T627
Test name
Test status
Simulation time 2213006241 ps
CPU time 15.73 seconds
Started Jun 24 06:40:23 PM PDT 24
Finished Jun 24 06:40:40 PM PDT 24
Peak memory 256380 kb
Host smart-252e7534-b909-4212-b323-f326c5758ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
2505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.133332505
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2956399463
Short name T128
Test name
Test status
Simulation time 184485502 ps
CPU time 12.54 seconds
Started Jun 24 06:40:23 PM PDT 24
Finished Jun 24 06:40:36 PM PDT 24
Peak memory 252756 kb
Host smart-b02c023c-cc92-45b1-9a49-e6962ccfa757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29563
99463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2956399463
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3875849586
Short name T11
Test name
Test status
Simulation time 241883214 ps
CPU time 12.78 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:40:40 PM PDT 24
Peak memory 275256 kb
Host smart-cc243139-0522-4e4d-9abb-63d42574b9f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3875849586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3875849586
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2577551063
Short name T376
Test name
Test status
Simulation time 245309345 ps
CPU time 30.63 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:40:56 PM PDT 24
Peak memory 256388 kb
Host smart-6adca8a0-7f43-42bf-86be-657b4822be33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
51063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2577551063
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1534413203
Short name T410
Test name
Test status
Simulation time 1351266285 ps
CPU time 43.71 seconds
Started Jun 24 06:40:21 PM PDT 24
Finished Jun 24 06:41:05 PM PDT 24
Peak memory 249096 kb
Host smart-4793836e-7a90-4de1-bab0-e1e0df483063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15344
13203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1534413203
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2202171649
Short name T278
Test name
Test status
Simulation time 61270588641 ps
CPU time 1122.24 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:59:07 PM PDT 24
Peak memory 289436 kb
Host smart-cf337006-ac2a-4f01-921b-1c834dcc439d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202171649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2202171649
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1003241725
Short name T273
Test name
Test status
Simulation time 77443269091 ps
CPU time 2370.85 seconds
Started Jun 24 06:42:27 PM PDT 24
Finished Jun 24 07:22:00 PM PDT 24
Peak memory 289468 kb
Host smart-4d71c2a7-1742-4823-844b-d23b589e6427
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003241725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1003241725
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1678314572
Short name T441
Test name
Test status
Simulation time 579615347 ps
CPU time 30.56 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 06:42:54 PM PDT 24
Peak memory 255560 kb
Host smart-3f74ff74-19f9-4662-8fb8-abc773538eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783
14572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1678314572
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3081201653
Short name T83
Test name
Test status
Simulation time 1231868028 ps
CPU time 39.91 seconds
Started Jun 24 06:42:25 PM PDT 24
Finished Jun 24 06:43:06 PM PDT 24
Peak memory 249120 kb
Host smart-7daeb830-bd9d-4c1f-962f-98188ef6df8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30812
01653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3081201653
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4145649534
Short name T308
Test name
Test status
Simulation time 30931174885 ps
CPU time 634.9 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:53:28 PM PDT 24
Peak memory 272408 kb
Host smart-d889abfd-b99b-4da4-ad42-c2ce0fd338f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145649534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4145649534
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3768456660
Short name T42
Test name
Test status
Simulation time 9037415512 ps
CPU time 1092.38 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 07:01:05 PM PDT 24
Peak memory 286140 kb
Host smart-d988ba74-68c7-4cf1-aca1-77580c05065e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768456660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3768456660
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.85164577
Short name T685
Test name
Test status
Simulation time 64923300474 ps
CPU time 162.42 seconds
Started Jun 24 06:42:23 PM PDT 24
Finished Jun 24 06:45:07 PM PDT 24
Peak memory 248472 kb
Host smart-54797d4a-6f30-43e9-9f9b-ba8a0fee7d92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85164577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.85164577
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.273015230
Short name T633
Test name
Test status
Simulation time 572143346 ps
CPU time 33.67 seconds
Started Jun 24 06:42:22 PM PDT 24
Finished Jun 24 06:42:58 PM PDT 24
Peak memory 249096 kb
Host smart-a329a363-7c29-41ed-90fa-9161c2bef216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
5230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.273015230
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2821181598
Short name T636
Test name
Test status
Simulation time 4457161120 ps
CPU time 51.86 seconds
Started Jun 24 06:42:26 PM PDT 24
Finished Jun 24 06:43:19 PM PDT 24
Peak memory 256016 kb
Host smart-020261eb-bb0e-437e-a281-55e5bcaefa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28211
81598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2821181598
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1625644157
Short name T521
Test name
Test status
Simulation time 3054543806 ps
CPU time 56.8 seconds
Started Jun 24 06:42:24 PM PDT 24
Finished Jun 24 06:43:22 PM PDT 24
Peak memory 249168 kb
Host smart-a16524af-04f4-4420-adb4-edf5fe40d482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
44157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1625644157
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2492443335
Short name T558
Test name
Test status
Simulation time 12605581344 ps
CPU time 1226.18 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 07:03:18 PM PDT 24
Peak memory 290124 kb
Host smart-6ce14cfd-e452-4566-a744-139b3c280c53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492443335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2492443335
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1218454924
Short name T456
Test name
Test status
Simulation time 128637882600 ps
CPU time 1081.93 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 07:00:54 PM PDT 24
Peak memory 265456 kb
Host smart-4345b6fa-ef49-4eca-8e69-172aa95ad345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218454924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1218454924
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.475297235
Short name T481
Test name
Test status
Simulation time 2526362461 ps
CPU time 172.74 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:45:46 PM PDT 24
Peak memory 257332 kb
Host smart-23fe3ccc-3938-48ce-a555-c78694344f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47529
7235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.475297235
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4176891934
Short name T277
Test name
Test status
Simulation time 700383221 ps
CPU time 46.1 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:39 PM PDT 24
Peak memory 249432 kb
Host smart-ce1112e4-d87c-4b87-805a-38d56a3e5063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
91934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4176891934
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2640843770
Short name T345
Test name
Test status
Simulation time 41926636649 ps
CPU time 1011.32 seconds
Started Jun 24 06:42:53 PM PDT 24
Finished Jun 24 06:59:46 PM PDT 24
Peak memory 273784 kb
Host smart-804c27fd-0d8c-40a4-b372-8595b7277573
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640843770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2640843770
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.440844770
Short name T550
Test name
Test status
Simulation time 78943772332 ps
CPU time 1247.31 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 07:03:39 PM PDT 24
Peak memory 272816 kb
Host smart-e969cb60-ef3c-463c-bb17-87c789dd20f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440844770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.440844770
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.290974202
Short name T635
Test name
Test status
Simulation time 29395223259 ps
CPU time 309.38 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:48:02 PM PDT 24
Peak memory 248572 kb
Host smart-90062623-8954-40ad-bdae-21f498e31671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290974202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.290974202
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1238689534
Short name T373
Test name
Test status
Simulation time 1913740730 ps
CPU time 55.72 seconds
Started Jun 24 06:42:54 PM PDT 24
Finished Jun 24 06:43:51 PM PDT 24
Peak memory 256420 kb
Host smart-2582bfed-d145-4c2c-a3e1-6b56d778149e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12386
89534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1238689534
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.989500010
Short name T209
Test name
Test status
Simulation time 660355546 ps
CPU time 44.04 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:37 PM PDT 24
Peak memory 256028 kb
Host smart-7737a840-201d-46dd-b3e6-90c3218b163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98950
0010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.989500010
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.448196794
Short name T539
Test name
Test status
Simulation time 340918623 ps
CPU time 20.62 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:43:13 PM PDT 24
Peak memory 248212 kb
Host smart-c140cc55-7bdf-4323-aa19-f1f52ae63c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44819
6794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.448196794
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2983389549
Short name T592
Test name
Test status
Simulation time 502811629 ps
CPU time 30.06 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:43:21 PM PDT 24
Peak memory 257268 kb
Host smart-d8e776e8-dd85-4ef0-8449-7ce21600058f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29833
89549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2983389549
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1977794547
Short name T586
Test name
Test status
Simulation time 50370781856 ps
CPU time 3052.51 seconds
Started Jun 24 06:42:53 PM PDT 24
Finished Jun 24 07:33:47 PM PDT 24
Peak memory 302664 kb
Host smart-6223dd31-6229-413b-ac6a-34d58513e8d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977794547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1977794547
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2569383832
Short name T244
Test name
Test status
Simulation time 130221562426 ps
CPU time 5468.39 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 08:14:02 PM PDT 24
Peak memory 338392 kb
Host smart-70924afa-3a04-4384-ac0f-83d4dd950c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569383832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2569383832
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2560489682
Short name T565
Test name
Test status
Simulation time 12399540366 ps
CPU time 1132.34 seconds
Started Jun 24 06:42:54 PM PDT 24
Finished Jun 24 07:01:47 PM PDT 24
Peak memory 283536 kb
Host smart-27a6197e-da8b-4964-aff7-93e413dc9142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560489682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2560489682
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3888328056
Short name T378
Test name
Test status
Simulation time 15511483800 ps
CPU time 266.46 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:47:18 PM PDT 24
Peak memory 257240 kb
Host smart-4e428920-c8e2-4e40-86a2-c605b1b424ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
28056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3888328056
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3096600152
Short name T698
Test name
Test status
Simulation time 1226780266 ps
CPU time 43.11 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:43:35 PM PDT 24
Peak memory 255360 kb
Host smart-949ed28c-399e-4340-bcf0-c641dfab881f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30966
00152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3096600152
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.332024251
Short name T338
Test name
Test status
Simulation time 39539487199 ps
CPU time 2533.73 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 07:25:06 PM PDT 24
Peak memory 288324 kb
Host smart-2e4967da-636b-4137-9845-48ce63a30e29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332024251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.332024251
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2821922787
Short name T573
Test name
Test status
Simulation time 19469314387 ps
CPU time 1215.14 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 07:03:06 PM PDT 24
Peak memory 273068 kb
Host smart-a51c7e94-6502-415c-b92b-fe04fcd69f2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821922787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2821922787
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1127932951
Short name T432
Test name
Test status
Simulation time 425314918 ps
CPU time 23.98 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 06:43:14 PM PDT 24
Peak memory 249100 kb
Host smart-990dbfd3-e123-4032-b625-6d0d79fc2465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
32951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1127932951
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3574526021
Short name T540
Test name
Test status
Simulation time 3901693889 ps
CPU time 54.73 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:48 PM PDT 24
Peak memory 256636 kb
Host smart-75992d61-bc4d-4bfe-b4dd-dfe8ecfc7c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745
26021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3574526021
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.796782461
Short name T31
Test name
Test status
Simulation time 2198229689 ps
CPU time 25.71 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 06:43:16 PM PDT 24
Peak memory 249136 kb
Host smart-e6cd67ed-0763-4b4b-8551-e1b080cf312e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79678
2461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.796782461
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.750926869
Short name T471
Test name
Test status
Simulation time 47390566756 ps
CPU time 1024.49 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 06:59:55 PM PDT 24
Peak memory 282236 kb
Host smart-46d852b6-adc9-45b8-bcfe-31d021a3d671
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750926869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.750926869
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.641048981
Short name T681
Test name
Test status
Simulation time 43549933022 ps
CPU time 838.11 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:56:51 PM PDT 24
Peak memory 273128 kb
Host smart-f7e1b7b5-8fb8-4457-a446-3a1f94e1d22f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641048981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.641048981
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2860564432
Short name T679
Test name
Test status
Simulation time 531883407 ps
CPU time 48.99 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:43:41 PM PDT 24
Peak memory 257260 kb
Host smart-25f8699b-fce8-41da-858d-a19f127ecedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
64432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2860564432
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.472389215
Short name T513
Test name
Test status
Simulation time 473994518 ps
CPU time 20.97 seconds
Started Jun 24 06:42:49 PM PDT 24
Finished Jun 24 06:43:12 PM PDT 24
Peak memory 255796 kb
Host smart-e6736f2f-f189-4a2c-be5b-651bb75a4515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47238
9215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.472389215
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3960559596
Short name T74
Test name
Test status
Simulation time 100874339948 ps
CPU time 1387.94 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 07:06:18 PM PDT 24
Peak memory 273756 kb
Host smart-db09e61b-5c5a-42da-b445-68296eec410a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960559596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3960559596
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3433068274
Short name T414
Test name
Test status
Simulation time 108410719808 ps
CPU time 1401.34 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 07:06:40 PM PDT 24
Peak memory 272932 kb
Host smart-d4b2fd21-4b82-4a7a-8bbd-a418de9d15a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433068274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3433068274
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.913869320
Short name T653
Test name
Test status
Simulation time 2802221476 ps
CPU time 21.71 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:15 PM PDT 24
Peak memory 256644 kb
Host smart-d9d1d83f-e32c-429e-a122-7cae95b82f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91386
9320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.913869320
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.252300867
Short name T687
Test name
Test status
Simulation time 540542693 ps
CPU time 34.63 seconds
Started Jun 24 06:42:50 PM PDT 24
Finished Jun 24 06:43:27 PM PDT 24
Peak memory 255936 kb
Host smart-331896a9-4a74-4590-a87f-19a42b247e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
0867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.252300867
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3451829765
Short name T296
Test name
Test status
Simulation time 2818961032 ps
CPU time 65.76 seconds
Started Jun 24 06:42:51 PM PDT 24
Finished Jun 24 06:43:59 PM PDT 24
Peak memory 248504 kb
Host smart-1efcb570-0814-425f-b137-7925141b615f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34518
29765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3451829765
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3580353211
Short name T623
Test name
Test status
Simulation time 59033219 ps
CPU time 3.95 seconds
Started Jun 24 06:42:54 PM PDT 24
Finished Jun 24 06:42:59 PM PDT 24
Peak memory 240880 kb
Host smart-96543463-d2cf-42e2-91b8-39530080db1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35803
53211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3580353211
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2329686363
Short name T204
Test name
Test status
Simulation time 8617351703 ps
CPU time 834.38 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:57:05 PM PDT 24
Peak memory 273756 kb
Host smart-4906048c-4740-4ffc-8b2c-5a8a37bcb457
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329686363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2329686363
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.995257056
Short name T240
Test name
Test status
Simulation time 14925945235 ps
CPU time 921.41 seconds
Started Jun 24 06:43:08 PM PDT 24
Finished Jun 24 06:58:30 PM PDT 24
Peak memory 269944 kb
Host smart-c6fb6774-0a63-4287-9c16-56fec92dc57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995257056 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.995257056
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1712605099
Short name T2
Test name
Test status
Simulation time 41624866901 ps
CPU time 1215.71 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 07:03:34 PM PDT 24
Peak memory 285300 kb
Host smart-a3452489-32d4-4510-9470-32af6a0e6183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712605099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1712605099
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2606975490
Short name T607
Test name
Test status
Simulation time 5807267351 ps
CPU time 148.85 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:45:41 PM PDT 24
Peak memory 256208 kb
Host smart-f52a959a-e252-4bf2-8c36-c1cd39395359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26069
75490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2606975490
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3412327345
Short name T536
Test name
Test status
Simulation time 351690785 ps
CPU time 27.72 seconds
Started Jun 24 06:43:12 PM PDT 24
Finished Jun 24 06:43:41 PM PDT 24
Peak memory 255884 kb
Host smart-715d129c-bab8-49fe-bb9a-278e0b6d38ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34123
27345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3412327345
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2124538109
Short name T486
Test name
Test status
Simulation time 11046990087 ps
CPU time 825.8 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:56:56 PM PDT 24
Peak memory 272852 kb
Host smart-8e6edea7-b34d-4c7e-bfe9-8012e20164a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124538109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2124538109
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1022232089
Short name T615
Test name
Test status
Simulation time 32089864593 ps
CPU time 1649.13 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 07:10:48 PM PDT 24
Peak memory 273696 kb
Host smart-7ab963dc-d299-455a-9629-2583db2a7a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022232089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1022232089
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3686141825
Short name T608
Test name
Test status
Simulation time 34873795011 ps
CPU time 412.72 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:50:05 PM PDT 24
Peak memory 248832 kb
Host smart-879acd9c-6e92-434d-afcc-1ca227cba863
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686141825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3686141825
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2212822026
Short name T18
Test name
Test status
Simulation time 106689202 ps
CPU time 5.89 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 06:43:24 PM PDT 24
Peak memory 253796 kb
Host smart-1b7986c7-c82d-4802-b421-650074aeb33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22128
22026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2212822026
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3242953914
Short name T467
Test name
Test status
Simulation time 2952283046 ps
CPU time 49.62 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:44:01 PM PDT 24
Peak memory 256160 kb
Host smart-f6358beb-5a4b-4763-9867-a003ffc8f453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
53914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3242953914
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.33767815
Short name T667
Test name
Test status
Simulation time 1476311334 ps
CPU time 17.47 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:43:28 PM PDT 24
Peak memory 254904 kb
Host smart-92a59e21-7488-4a80-a37f-ab0d107e7b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33767
815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.33767815
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1120332474
Short name T605
Test name
Test status
Simulation time 162365872 ps
CPU time 20.23 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:43:31 PM PDT 24
Peak memory 249016 kb
Host smart-a9511765-7415-4b9a-a081-9c98a15282f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
32474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1120332474
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2355268437
Short name T294
Test name
Test status
Simulation time 324487670438 ps
CPU time 1919.23 seconds
Started Jun 24 06:43:14 PM PDT 24
Finished Jun 24 07:15:17 PM PDT 24
Peak memory 298324 kb
Host smart-92209e34-c43f-4907-bb17-8bcb9b9c033a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355268437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2355268437
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3956499929
Short name T87
Test name
Test status
Simulation time 22549011920 ps
CPU time 1577.76 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 07:09:30 PM PDT 24
Peak memory 286532 kb
Host smart-8ee1a484-2009-44ef-932b-0a342390ecc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956499929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3956499929
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1049607497
Short name T253
Test name
Test status
Simulation time 124067045285 ps
CPU time 1208.06 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 07:03:19 PM PDT 24
Peak memory 267540 kb
Host smart-5c2b6d41-5f95-4c16-a9d9-76f022014888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049607497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1049607497
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1133440053
Short name T236
Test name
Test status
Simulation time 4882615973 ps
CPU time 133.31 seconds
Started Jun 24 06:43:08 PM PDT 24
Finished Jun 24 06:45:22 PM PDT 24
Peak memory 257324 kb
Host smart-c81041c3-68d6-423f-8705-9a4494de2d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
40053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1133440053
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3360642850
Short name T664
Test name
Test status
Simulation time 727088640 ps
CPU time 33.39 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 06:43:52 PM PDT 24
Peak memory 256908 kb
Host smart-8d4d71df-fda1-4e22-97e0-82125801c34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33606
42850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3360642850
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3887071579
Short name T346
Test name
Test status
Simulation time 15700924890 ps
CPU time 1279.99 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 07:04:32 PM PDT 24
Peak memory 272952 kb
Host smart-6ad55bdb-773a-4fb5-998d-62a4e839ae74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887071579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3887071579
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2450041364
Short name T594
Test name
Test status
Simulation time 74376541468 ps
CPU time 2359.61 seconds
Started Jun 24 06:43:08 PM PDT 24
Finished Jun 24 07:22:29 PM PDT 24
Peak memory 289428 kb
Host smart-ea0b488a-c4c2-40ea-b103-d29013536e7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450041364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2450041364
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.680464131
Short name T8
Test name
Test status
Simulation time 27053751436 ps
CPU time 559.05 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:52:31 PM PDT 24
Peak memory 254872 kb
Host smart-3eea2c06-78c5-44e8-9591-a08edd7c93ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680464131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.680464131
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2475436076
Short name T65
Test name
Test status
Simulation time 346210722 ps
CPU time 21.75 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:43:33 PM PDT 24
Peak memory 249084 kb
Host smart-b4a9e063-9231-4bb4-9f6c-1204490fd1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
36076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2475436076
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1345969846
Short name T396
Test name
Test status
Simulation time 2150474921 ps
CPU time 18.77 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:43:29 PM PDT 24
Peak memory 254792 kb
Host smart-56dd9f89-e022-4f24-9431-46c897c7bc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
69846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1345969846
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3671167518
Short name T82
Test name
Test status
Simulation time 660201033 ps
CPU time 29.62 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 06:43:47 PM PDT 24
Peak memory 256056 kb
Host smart-13f45a01-1073-4da6-ab5a-e60d875475bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36711
67518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3671167518
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3905491613
Short name T413
Test name
Test status
Simulation time 623968037 ps
CPU time 41.99 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:43:54 PM PDT 24
Peak memory 257260 kb
Host smart-370a094a-0df5-4474-8124-22836f7dfbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054
91613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3905491613
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.396253412
Short name T670
Test name
Test status
Simulation time 14013110263 ps
CPU time 194.59 seconds
Started Jun 24 06:43:11 PM PDT 24
Finished Jun 24 06:46:28 PM PDT 24
Peak memory 257260 kb
Host smart-e0b25b7f-beba-45d1-8d9b-e8b500e6438c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396253412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.396253412
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3072103168
Short name T28
Test name
Test status
Simulation time 142276556068 ps
CPU time 1968.65 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 07:16:01 PM PDT 24
Peak memory 298480 kb
Host smart-58bfa2a0-5c20-416d-84a5-688ac7166b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072103168 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3072103168
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3873749826
Short name T700
Test name
Test status
Simulation time 76598557922 ps
CPU time 1334.61 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 07:05:25 PM PDT 24
Peak memory 273024 kb
Host smart-972f2a6b-f638-4bfd-8f63-54aa31d4116f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873749826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3873749826
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2947656097
Short name T207
Test name
Test status
Simulation time 15332545345 ps
CPU time 282.31 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:47:54 PM PDT 24
Peak memory 257240 kb
Host smart-43395584-c120-439d-95ab-f99c4cd190ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29476
56097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2947656097
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.480677712
Short name T434
Test name
Test status
Simulation time 779959065 ps
CPU time 43.36 seconds
Started Jun 24 06:43:07 PM PDT 24
Finished Jun 24 06:43:51 PM PDT 24
Peak memory 255424 kb
Host smart-1b774da0-8123-4360-bab5-9b387ee19b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48067
7712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.480677712
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1148924145
Short name T339
Test name
Test status
Simulation time 104466304988 ps
CPU time 1054.37 seconds
Started Jun 24 06:43:15 PM PDT 24
Finished Jun 24 07:00:53 PM PDT 24
Peak memory 289396 kb
Host smart-2e3dd5ba-a843-482c-883d-7e3a4c3a83c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148924145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1148924145
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2195506464
Short name T560
Test name
Test status
Simulation time 115032431903 ps
CPU time 1687.79 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 07:11:18 PM PDT 24
Peak memory 273116 kb
Host smart-c578cce1-5c0d-4626-9707-79137596507c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195506464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2195506464
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.28644299
Short name T248
Test name
Test status
Simulation time 21107710821 ps
CPU time 310.1 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:48:22 PM PDT 24
Peak memory 248144 kb
Host smart-1d286cee-8f02-4b74-b05b-61668897dd91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28644299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.28644299
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1936812504
Short name T602
Test name
Test status
Simulation time 748871051 ps
CPU time 42.71 seconds
Started Jun 24 06:43:14 PM PDT 24
Finished Jun 24 06:44:00 PM PDT 24
Peak memory 256652 kb
Host smart-c097559e-9376-4949-928f-6ae2da30e429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368
12504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1936812504
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2125192709
Short name T632
Test name
Test status
Simulation time 581492040 ps
CPU time 8.77 seconds
Started Jun 24 06:43:08 PM PDT 24
Finished Jun 24 06:43:18 PM PDT 24
Peak memory 254752 kb
Host smart-87a4c1c5-d192-4a0a-89e1-8fcb1cfd5569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251
92709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2125192709
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3961413493
Short name T208
Test name
Test status
Simulation time 455454429 ps
CPU time 36.46 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 06:43:49 PM PDT 24
Peak memory 248020 kb
Host smart-83ce6b8c-535b-49dc-b21e-0625e71e09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39614
13493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3961413493
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.257585721
Short name T674
Test name
Test status
Simulation time 601313794 ps
CPU time 23.25 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:43:34 PM PDT 24
Peak memory 256536 kb
Host smart-e4dfa189-96dc-4518-940c-0c06d8df8749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758
5721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.257585721
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2709133164
Short name T281
Test name
Test status
Simulation time 233765174309 ps
CPU time 3352.51 seconds
Started Jun 24 06:43:10 PM PDT 24
Finished Jun 24 07:39:05 PM PDT 24
Peak memory 289460 kb
Host smart-52357e13-c3d3-4945-836b-ce4ff6bb3fa9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709133164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2709133164
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1413226051
Short name T210
Test name
Test status
Simulation time 207848515322 ps
CPU time 3737.15 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 07:45:28 PM PDT 24
Peak memory 305804 kb
Host smart-201dc9d6-2159-4dd6-9fe6-4cdc1ccae36f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413226051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1413226051
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4273971957
Short name T624
Test name
Test status
Simulation time 15280187921 ps
CPU time 975.32 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:59:44 PM PDT 24
Peak memory 273660 kb
Host smart-d0676fa4-7db5-46e8-9a5c-a9c9b94783a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273971957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4273971957
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.687778116
Short name T576
Test name
Test status
Simulation time 3377092198 ps
CPU time 201.33 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 06:47:01 PM PDT 24
Peak memory 256476 kb
Host smart-cd3628ff-df03-41ea-8439-304c61a2f5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68777
8116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.687778116
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1125320113
Short name T472
Test name
Test status
Simulation time 1023241895 ps
CPU time 35.16 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:44:08 PM PDT 24
Peak memory 256188 kb
Host smart-802cd5ba-ec8c-40e4-bde0-507505680d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
20113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1125320113
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1405430583
Short name T340
Test name
Test status
Simulation time 37484527961 ps
CPU time 808.71 seconds
Started Jun 24 06:43:30 PM PDT 24
Finished Jun 24 06:57:20 PM PDT 24
Peak memory 273368 kb
Host smart-39ad7d1d-db0f-4f73-baaf-18f57aa3c71d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405430583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1405430583
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2292713702
Short name T5
Test name
Test status
Simulation time 57304193701 ps
CPU time 1995.62 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 07:16:47 PM PDT 24
Peak memory 287388 kb
Host smart-5ca8feee-654b-48b1-801e-3993c0c08219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292713702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2292713702
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2099743445
Short name T327
Test name
Test status
Simulation time 21562052190 ps
CPU time 213.61 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:47:03 PM PDT 24
Peak memory 248748 kb
Host smart-75bb7202-4c46-47ed-ac50-29b370f57bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099743445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2099743445
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1914400794
Short name T470
Test name
Test status
Simulation time 145275532 ps
CPU time 9.21 seconds
Started Jun 24 06:43:09 PM PDT 24
Finished Jun 24 06:43:20 PM PDT 24
Peak memory 249068 kb
Host smart-64ba934f-1543-4003-870c-c56b2637595f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
00794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1914400794
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3648516959
Short name T122
Test name
Test status
Simulation time 35855379 ps
CPU time 5.25 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:43:38 PM PDT 24
Peak memory 251480 kb
Host smart-c8ac61f4-cb27-4bb3-b431-a682314022a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36485
16959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3648516959
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1501469603
Short name T295
Test name
Test status
Simulation time 342509359 ps
CPU time 30.03 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:43:58 PM PDT 24
Peak memory 247924 kb
Host smart-7643e8dc-d8e2-4cee-a8a4-83a35e73bd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
69603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1501469603
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1421346433
Short name T547
Test name
Test status
Simulation time 270995844 ps
CPU time 26.44 seconds
Started Jun 24 06:43:11 PM PDT 24
Finished Jun 24 06:43:39 PM PDT 24
Peak memory 249196 kb
Host smart-2da29266-1fcd-47ae-8d3a-2beca712c358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14213
46433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1421346433
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2753644847
Short name T512
Test name
Test status
Simulation time 19137976941 ps
CPU time 1732.12 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 07:12:23 PM PDT 24
Peak memory 289276 kb
Host smart-4e423f5d-ba84-4406-aec2-0acb85058555
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753644847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2753644847
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3866792162
Short name T567
Test name
Test status
Simulation time 11628889751 ps
CPU time 1221.65 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 07:03:57 PM PDT 24
Peak memory 289284 kb
Host smart-f75f6af7-d750-478b-9fda-c95eba529655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866792162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3866792162
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.793568853
Short name T611
Test name
Test status
Simulation time 12431223482 ps
CPU time 198.01 seconds
Started Jun 24 06:43:30 PM PDT 24
Finished Jun 24 06:47:09 PM PDT 24
Peak memory 257364 kb
Host smart-a5be6e2e-d19e-4ab3-925d-ac3584643d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79356
8853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.793568853
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3101203204
Short name T640
Test name
Test status
Simulation time 1208543299 ps
CPU time 72.7 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:44:44 PM PDT 24
Peak memory 256320 kb
Host smart-3dc65d4f-9049-4537-ac0b-66676d589350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012
03204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3101203204
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1721200480
Short name T343
Test name
Test status
Simulation time 53895136066 ps
CPU time 990.09 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 07:00:06 PM PDT 24
Peak memory 273224 kb
Host smart-ec42f3d5-6e98-43dd-a713-42034f07b713
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721200480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1721200480
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1283346868
Short name T559
Test name
Test status
Simulation time 25524991251 ps
CPU time 1618.55 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 07:10:41 PM PDT 24
Peak memory 288852 kb
Host smart-ae50a8bf-2cce-431d-8d34-95a71916521f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283346868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1283346868
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3689231623
Short name T309
Test name
Test status
Simulation time 5561590094 ps
CPU time 228.96 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 06:47:28 PM PDT 24
Peak memory 248292 kb
Host smart-6d25252c-b4e9-49aa-b6b0-c648d89d65c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689231623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3689231623
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3143002925
Short name T184
Test name
Test status
Simulation time 515944908 ps
CPU time 13.38 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:43:49 PM PDT 24
Peak memory 249060 kb
Host smart-7057f913-bf8e-4911-a7e9-d6f5fa3da8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31430
02925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3143002925
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.895587709
Short name T124
Test name
Test status
Simulation time 518676924 ps
CPU time 19.78 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:43:48 PM PDT 24
Peak memory 247980 kb
Host smart-798d1c85-4ec9-4667-8763-02eef26f64de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89558
7709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.895587709
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3839954269
Short name T617
Test name
Test status
Simulation time 1585192119 ps
CPU time 30.03 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 06:44:06 PM PDT 24
Peak memory 247920 kb
Host smart-aaa07a80-fe21-4a2b-a9ae-dfbfaa69e87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38399
54269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3839954269
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.231607758
Short name T64
Test name
Test status
Simulation time 112710770 ps
CPU time 10.75 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:43:41 PM PDT 24
Peak memory 257252 kb
Host smart-21d03e6c-70d4-4789-8ba5-f0bfea436386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
7758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.231607758
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.662301476
Short name T684
Test name
Test status
Simulation time 120474500873 ps
CPU time 1234.76 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 07:04:48 PM PDT 24
Peak memory 284336 kb
Host smart-e1716021-4cda-46a5-a44e-030568df14dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662301476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.662301476
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.4220110370
Short name T45
Test name
Test status
Simulation time 2424940158 ps
CPU time 115.97 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:45:32 PM PDT 24
Peak memory 257272 kb
Host smart-40d3c642-3d45-4c36-bc2f-664232881edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
10370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4220110370
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3033195381
Short name T188
Test name
Test status
Simulation time 1238450347 ps
CPU time 81.01 seconds
Started Jun 24 06:43:31 PM PDT 24
Finished Jun 24 06:45:14 PM PDT 24
Peak memory 256280 kb
Host smart-ff112a65-e7a8-4d7b-8d4e-f7ff49d0d739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
95381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3033195381
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1851620796
Short name T510
Test name
Test status
Simulation time 52450230771 ps
CPU time 2816.98 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 07:31:12 PM PDT 24
Peak memory 289360 kb
Host smart-594a167d-5925-4eb0-9f50-c4554fbceb96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851620796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1851620796
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2302008271
Short name T598
Test name
Test status
Simulation time 93989963291 ps
CPU time 2807.28 seconds
Started Jun 24 06:43:46 PM PDT 24
Finished Jun 24 07:31:07 PM PDT 24
Peak memory 285236 kb
Host smart-ee8c35d1-7a2e-48a6-a849-2fa30e23047a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302008271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2302008271
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.538458149
Short name T262
Test name
Test status
Simulation time 158101950 ps
CPU time 23.04 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:43:54 PM PDT 24
Peak memory 249216 kb
Host smart-6ac090ad-99ec-480e-adcb-9bf9dafea948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53845
8149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.538458149
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.67612284
Short name T669
Test name
Test status
Simulation time 933365437 ps
CPU time 45.66 seconds
Started Jun 24 06:43:27 PM PDT 24
Finished Jun 24 06:44:23 PM PDT 24
Peak memory 256164 kb
Host smart-70a96032-0588-425e-ac32-474e1ea84643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67612
284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.67612284
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2904646371
Short name T25
Test name
Test status
Simulation time 4935742433 ps
CPU time 38.08 seconds
Started Jun 24 06:43:26 PM PDT 24
Finished Jun 24 06:44:10 PM PDT 24
Peak memory 250136 kb
Host smart-563ec666-54ed-4354-821e-d5049b8b6736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
46371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2904646371
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1139958082
Short name T411
Test name
Test status
Simulation time 28417453 ps
CPU time 4.8 seconds
Started Jun 24 06:43:25 PM PDT 24
Finished Jun 24 06:43:36 PM PDT 24
Peak memory 251312 kb
Host smart-b942566d-4f4c-4e24-9414-174ab13fd68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11399
58082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1139958082
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1608893963
Short name T577
Test name
Test status
Simulation time 846413565745 ps
CPU time 6617.81 seconds
Started Jun 24 06:43:41 PM PDT 24
Finished Jun 24 08:34:32 PM PDT 24
Peak memory 339184 kb
Host smart-c05c7ed2-cfd5-4581-8e49-51082c86e12d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608893963 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1608893963
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2019332353
Short name T220
Test name
Test status
Simulation time 50310166 ps
CPU time 2.44 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 06:40:28 PM PDT 24
Peak memory 249220 kb
Host smart-5f06bd18-0ea8-4ac6-8eea-305b5832a325
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2019332353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2019332353
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.475492149
Short name T125
Test name
Test status
Simulation time 113287236443 ps
CPU time 1914.31 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 07:12:20 PM PDT 24
Peak memory 282940 kb
Host smart-de66801e-5aaf-40de-949e-09ca214dd8b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475492149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.475492149
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2280218826
Short name T395
Test name
Test status
Simulation time 801963975 ps
CPU time 7.61 seconds
Started Jun 24 06:40:23 PM PDT 24
Finished Jun 24 06:40:31 PM PDT 24
Peak memory 249120 kb
Host smart-b14aeef9-45e9-4afa-a986-eb3191563aca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2280218826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2280218826
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4038955925
Short name T609
Test name
Test status
Simulation time 1582352086 ps
CPU time 94.51 seconds
Started Jun 24 06:40:22 PM PDT 24
Finished Jun 24 06:41:57 PM PDT 24
Peak memory 249176 kb
Host smart-d6552404-d285-458b-a64b-7e35275691db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
55925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4038955925
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2948922014
Short name T393
Test name
Test status
Simulation time 507152425 ps
CPU time 28.77 seconds
Started Jun 24 06:40:22 PM PDT 24
Finished Jun 24 06:40:51 PM PDT 24
Peak memory 256492 kb
Host smart-1852b135-ceaf-4808-b58b-a350dc8c9546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29489
22014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2948922014
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2108290529
Short name T499
Test name
Test status
Simulation time 7633772051 ps
CPU time 735.34 seconds
Started Jun 24 06:40:23 PM PDT 24
Finished Jun 24 06:52:40 PM PDT 24
Peak memory 265548 kb
Host smart-4c984236-6b89-4787-b684-285dbf6a56fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108290529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2108290529
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3317010841
Short name T578
Test name
Test status
Simulation time 14511314479 ps
CPU time 1251.96 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 07:01:17 PM PDT 24
Peak memory 285724 kb
Host smart-9517609b-8adf-4012-a750-fb5192ccac05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317010841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3317010841
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1934597551
Short name T324
Test name
Test status
Simulation time 8718906948 ps
CPU time 343.86 seconds
Started Jun 24 06:40:23 PM PDT 24
Finished Jun 24 06:46:08 PM PDT 24
Peak memory 248768 kb
Host smart-1ad18964-2626-4687-aa8b-9ea40c4493c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934597551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1934597551
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2346888030
Short name T403
Test name
Test status
Simulation time 275096394 ps
CPU time 14.09 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:40:41 PM PDT 24
Peak memory 256316 kb
Host smart-6f9e4d61-4e27-425d-9247-9ee514b15a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23468
88030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2346888030
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1232978328
Short name T408
Test name
Test status
Simulation time 542772409 ps
CPU time 26.13 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:40:52 PM PDT 24
Peak memory 248528 kb
Host smart-4bd36297-ba28-4089-945a-5ee06d128706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
78328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1232978328
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3977923908
Short name T12
Test name
Test status
Simulation time 3598175814 ps
CPU time 26.4 seconds
Started Jun 24 06:40:27 PM PDT 24
Finished Jun 24 06:40:55 PM PDT 24
Peak memory 270252 kb
Host smart-b2407453-b560-4876-8ef5-81ac39c3ec89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3977923908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3977923908
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2460890959
Short name T264
Test name
Test status
Simulation time 399212784 ps
CPU time 24.49 seconds
Started Jun 24 06:40:25 PM PDT 24
Finished Jun 24 06:40:51 PM PDT 24
Peak memory 256092 kb
Host smart-b160460e-c0db-4f48-95e9-2c22427b5693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
90959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2460890959
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1206173318
Short name T381
Test name
Test status
Simulation time 121436716 ps
CPU time 9.18 seconds
Started Jun 24 06:40:26 PM PDT 24
Finished Jun 24 06:40:37 PM PDT 24
Peak memory 249100 kb
Host smart-ee6c936f-d92f-47ce-a155-bdfb95685c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
73318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1206173318
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.89176194
Short name T30
Test name
Test status
Simulation time 32060199435 ps
CPU time 1917.36 seconds
Started Jun 24 06:40:22 PM PDT 24
Finished Jun 24 07:12:20 PM PDT 24
Peak memory 287620 kb
Host smart-3698b0d3-3463-49b9-a61b-67ff3545fe03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89176194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handl
er_stress_all.89176194
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3280301183
Short name T4
Test name
Test status
Simulation time 71001644016 ps
CPU time 1936.31 seconds
Started Jun 24 06:40:24 PM PDT 24
Finished Jun 24 07:12:42 PM PDT 24
Peak memory 290116 kb
Host smart-0c5e26c2-a18d-463f-a63b-0e95c5980c63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280301183 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3280301183
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2351041225
Short name T52
Test name
Test status
Simulation time 90148449870 ps
CPU time 2643.7 seconds
Started Jun 24 06:43:45 PM PDT 24
Finished Jun 24 07:28:22 PM PDT 24
Peak memory 285392 kb
Host smart-f97a53a3-f82e-4a69-baed-090f907bc74a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351041225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2351041225
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3225976238
Short name T251
Test name
Test status
Simulation time 4877545441 ps
CPU time 200.54 seconds
Started Jun 24 06:43:43 PM PDT 24
Finished Jun 24 06:47:36 PM PDT 24
Peak memory 257280 kb
Host smart-cd82a07b-646d-4ae8-9d1d-4345ae887a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
76238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3225976238
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3923645477
Short name T606
Test name
Test status
Simulation time 4835363562 ps
CPU time 78.02 seconds
Started Jun 24 06:43:46 PM PDT 24
Finished Jun 24 06:45:37 PM PDT 24
Peak memory 249176 kb
Host smart-fa7096a1-9508-4c69-ab88-e7732a24c2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
45477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3923645477
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3610059528
Short name T121
Test name
Test status
Simulation time 192379624054 ps
CPU time 3065.94 seconds
Started Jun 24 06:43:43 PM PDT 24
Finished Jun 24 07:35:21 PM PDT 24
Peak memory 281560 kb
Host smart-da038973-985c-4dbf-a604-7cee97b94f39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610059528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3610059528
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1099131398
Short name T709
Test name
Test status
Simulation time 1938293885 ps
CPU time 39.12 seconds
Started Jun 24 06:43:41 PM PDT 24
Finished Jun 24 06:44:53 PM PDT 24
Peak memory 249044 kb
Host smart-27372c9c-5187-47cb-8271-b80877847fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991
31398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1099131398
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2681549379
Short name T569
Test name
Test status
Simulation time 4839603890 ps
CPU time 76.19 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 06:45:31 PM PDT 24
Peak memory 256084 kb
Host smart-9e63e01f-c5c2-4bed-b7ac-b15d2f0178ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26815
49379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2681549379
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2380585875
Short name T289
Test name
Test status
Simulation time 4751858458 ps
CPU time 54.35 seconds
Started Jun 24 06:43:41 PM PDT 24
Finished Jun 24 06:45:08 PM PDT 24
Peak memory 257024 kb
Host smart-0ca4fb67-7ef2-4446-a578-bdd6f86b8a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23805
85875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2380585875
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2066548378
Short name T473
Test name
Test status
Simulation time 3319075780 ps
CPU time 42.05 seconds
Started Jun 24 06:43:44 PM PDT 24
Finished Jun 24 06:45:00 PM PDT 24
Peak memory 257304 kb
Host smart-6dcf764e-21ef-445c-b4ed-8b8973947c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20665
48378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2066548378
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3840524561
Short name T250
Test name
Test status
Simulation time 48129547814 ps
CPU time 1807.01 seconds
Started Jun 24 06:43:46 PM PDT 24
Finished Jun 24 07:14:26 PM PDT 24
Peak memory 298180 kb
Host smart-d0e852c6-589a-4984-850c-89fb442938a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840524561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3840524561
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3564247282
Short name T59
Test name
Test status
Simulation time 63156997535 ps
CPU time 5341.29 seconds
Started Jun 24 06:43:41 PM PDT 24
Finished Jun 24 08:13:15 PM PDT 24
Peak memory 314784 kb
Host smart-14e8dfaa-bb39-4be9-a90d-d48c2d2714e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564247282 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3564247282
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3096804270
Short name T535
Test name
Test status
Simulation time 23988396224 ps
CPU time 1275.26 seconds
Started Jun 24 06:43:44 PM PDT 24
Finished Jun 24 07:05:33 PM PDT 24
Peak memory 272920 kb
Host smart-2842ae7e-9fe3-49f0-9c2b-56317b583490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096804270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3096804270
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2515332985
Short name T662
Test name
Test status
Simulation time 4803952865 ps
CPU time 137.69 seconds
Started Jun 24 06:43:43 PM PDT 24
Finished Jun 24 06:46:33 PM PDT 24
Peak memory 250668 kb
Host smart-2d88563d-f341-4423-b3ce-808d96b0cf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
32985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2515332985
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2073026011
Short name T439
Test name
Test status
Simulation time 372123822 ps
CPU time 6.82 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 06:44:22 PM PDT 24
Peak memory 241148 kb
Host smart-b029b3e0-ab95-457b-aa4f-527e81fe9b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
26011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2073026011
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3788496626
Short name T642
Test name
Test status
Simulation time 121580822431 ps
CPU time 1980.13 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 07:17:15 PM PDT 24
Peak memory 268632 kb
Host smart-b3d7c6e5-5d79-4452-bf08-ec564d6100f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788496626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3788496626
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1937932541
Short name T628
Test name
Test status
Simulation time 52466383406 ps
CPU time 3428.99 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 07:41:24 PM PDT 24
Peak memory 289708 kb
Host smart-70b80d9c-e090-4375-bb66-db4d39a0b316
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937932541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1937932541
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3149003073
Short name T672
Test name
Test status
Simulation time 32725513966 ps
CPU time 501.66 seconds
Started Jun 24 06:43:47 PM PDT 24
Finished Jun 24 06:52:41 PM PDT 24
Peak memory 248732 kb
Host smart-21c02278-cd36-49cd-970e-b7563f7002f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149003073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3149003073
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2265985682
Short name T447
Test name
Test status
Simulation time 52545722 ps
CPU time 4.59 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 06:44:19 PM PDT 24
Peak memory 240896 kb
Host smart-68a8967b-d502-4b50-addc-1e47d69f2a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22659
85682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2265985682
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.494702527
Short name T237
Test name
Test status
Simulation time 220636295 ps
CPU time 25.48 seconds
Started Jun 24 06:43:45 PM PDT 24
Finished Jun 24 06:44:43 PM PDT 24
Peak memory 256096 kb
Host smart-0ad1258b-b844-4bb5-b09a-2712c1099af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49470
2527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.494702527
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2590145028
Short name T76
Test name
Test status
Simulation time 6043539082 ps
CPU time 63.21 seconds
Started Jun 24 06:43:41 PM PDT 24
Finished Jun 24 06:45:17 PM PDT 24
Peak memory 256392 kb
Host smart-2d99350a-2509-4301-b686-a4a2e683bc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
45028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2590145028
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1865334351
Short name T415
Test name
Test status
Simulation time 2656943348 ps
CPU time 22.56 seconds
Started Jun 24 06:43:42 PM PDT 24
Finished Jun 24 06:44:36 PM PDT 24
Peak memory 256396 kb
Host smart-0386a50f-2623-467c-b188-7150f38fcc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
34351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1865334351
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1851222619
Short name T485
Test name
Test status
Simulation time 147056939212 ps
CPU time 1760.12 seconds
Started Jun 24 06:44:00 PM PDT 24
Finished Jun 24 07:13:45 PM PDT 24
Peak memory 289992 kb
Host smart-62438697-2f03-477e-9b79-cfb15941a237
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851222619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1851222619
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4056327408
Short name T464
Test name
Test status
Simulation time 13184253252 ps
CPU time 201.36 seconds
Started Jun 24 06:44:01 PM PDT 24
Finished Jun 24 06:47:46 PM PDT 24
Peak memory 250332 kb
Host smart-037a50c9-12c3-40fd-8da9-8e343a9ad9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40563
27408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4056327408
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4156903428
Short name T650
Test name
Test status
Simulation time 664254486 ps
CPU time 24.25 seconds
Started Jun 24 06:43:57 PM PDT 24
Finished Jun 24 06:44:48 PM PDT 24
Peak memory 249028 kb
Host smart-611102a9-8657-4a73-bb38-946850f11315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
03428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4156903428
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.728972625
Short name T101
Test name
Test status
Simulation time 12159968260 ps
CPU time 971.16 seconds
Started Jun 24 06:44:05 PM PDT 24
Finished Jun 24 07:00:38 PM PDT 24
Peak memory 289668 kb
Host smart-ca2ddca2-32c9-4782-85e5-7e3eb72059bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728972625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.728972625
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.804058290
Short name T261
Test name
Test status
Simulation time 28848075068 ps
CPU time 703.05 seconds
Started Jun 24 06:44:03 PM PDT 24
Finished Jun 24 06:56:09 PM PDT 24
Peak memory 265772 kb
Host smart-be06dbf0-20d9-4349-b065-e03fcbeb0153
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804058290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.804058290
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1566589929
Short name T545
Test name
Test status
Simulation time 6888879856 ps
CPU time 305.92 seconds
Started Jun 24 06:44:00 PM PDT 24
Finished Jun 24 06:49:31 PM PDT 24
Peak memory 248596 kb
Host smart-b519d54b-5d4b-4e38-b2a5-521dbf87f7b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566589929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1566589929
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1900829501
Short name T639
Test name
Test status
Simulation time 3916130194 ps
CPU time 46.97 seconds
Started Jun 24 06:43:59 PM PDT 24
Finished Jun 24 06:45:12 PM PDT 24
Peak memory 249176 kb
Host smart-727906e3-7f9e-4621-82d4-e76d2d795bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19008
29501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1900829501
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3265118422
Short name T249
Test name
Test status
Simulation time 1265509516 ps
CPU time 18.97 seconds
Started Jun 24 06:44:02 PM PDT 24
Finished Jun 24 06:44:44 PM PDT 24
Peak memory 249460 kb
Host smart-619443ab-2c8a-4923-9d34-4805d1018c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651
18422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3265118422
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2685846326
Short name T409
Test name
Test status
Simulation time 3294338625 ps
CPU time 27.54 seconds
Started Jun 24 06:43:59 PM PDT 24
Finished Jun 24 06:44:52 PM PDT 24
Peak memory 257288 kb
Host smart-d99b327b-85a4-46b5-bef6-c7bbbddd5b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858
46326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2685846326
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3723784014
Short name T377
Test name
Test status
Simulation time 102209260 ps
CPU time 7.79 seconds
Started Jun 24 06:43:57 PM PDT 24
Finished Jun 24 06:44:32 PM PDT 24
Peak memory 249104 kb
Host smart-3a56f07a-e7c4-4cee-b8de-ccd9b6637618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
84014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3723784014
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2176467859
Short name T686
Test name
Test status
Simulation time 12534320036 ps
CPU time 1166.78 seconds
Started Jun 24 06:44:01 PM PDT 24
Finished Jun 24 07:03:52 PM PDT 24
Peak memory 289548 kb
Host smart-73432287-f48d-45d9-a813-52f2dc75021a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176467859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2176467859
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.348079373
Short name T571
Test name
Test status
Simulation time 18948416261 ps
CPU time 1221.06 seconds
Started Jun 24 06:44:16 PM PDT 24
Finished Jun 24 07:04:50 PM PDT 24
Peak memory 272992 kb
Host smart-3930b8d5-321a-4142-b6e0-14f7a719b03e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348079373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.348079373
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3131275697
Short name T66
Test name
Test status
Simulation time 1719880469 ps
CPU time 149.01 seconds
Started Jun 24 06:44:04 PM PDT 24
Finished Jun 24 06:46:54 PM PDT 24
Peak memory 257296 kb
Host smart-dd0be261-2b9b-452c-b91e-c330c8d06c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31312
75697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3131275697
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2117797964
Short name T388
Test name
Test status
Simulation time 785686888 ps
CPU time 51.37 seconds
Started Jun 24 06:44:00 PM PDT 24
Finished Jun 24 06:45:16 PM PDT 24
Peak memory 255844 kb
Host smart-06758d4a-8167-45a3-8bb4-165ecd368f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21177
97964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2117797964
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3484196107
Short name T6
Test name
Test status
Simulation time 112908035155 ps
CPU time 1598.71 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 07:11:08 PM PDT 24
Peak memory 273048 kb
Host smart-2c7a299e-e412-4c1a-b8e2-112cb440b453
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484196107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3484196107
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.262049050
Short name T593
Test name
Test status
Simulation time 271894108569 ps
CPU time 2267.27 seconds
Started Jun 24 06:44:16 PM PDT 24
Finished Jun 24 07:22:16 PM PDT 24
Peak memory 287908 kb
Host smart-6a3df9b7-31c4-49fb-bd82-968d34b6dde0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262049050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.262049050
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2691462446
Short name T298
Test name
Test status
Simulation time 5891996039 ps
CPU time 267.5 seconds
Started Jun 24 06:44:16 PM PDT 24
Finished Jun 24 06:48:56 PM PDT 24
Peak memory 248472 kb
Host smart-a7f85068-049e-43d5-83ac-a11a90eafdf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691462446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2691462446
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1213853240
Short name T519
Test name
Test status
Simulation time 1383037018 ps
CPU time 43.66 seconds
Started Jun 24 06:43:58 PM PDT 24
Finished Jun 24 06:45:08 PM PDT 24
Peak memory 249088 kb
Host smart-03b38a16-7142-480c-878f-b7261b0c7829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
53240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1213853240
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3555211045
Short name T671
Test name
Test status
Simulation time 178843847 ps
CPU time 21.39 seconds
Started Jun 24 06:43:57 PM PDT 24
Finished Jun 24 06:44:45 PM PDT 24
Peak memory 255648 kb
Host smart-92af4b35-a5bb-4ef2-8059-a86f789b96b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
11045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3555211045
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.413286680
Short name T279
Test name
Test status
Simulation time 5937336810 ps
CPU time 22.14 seconds
Started Jun 24 06:44:17 PM PDT 24
Finished Jun 24 06:44:51 PM PDT 24
Peak memory 256244 kb
Host smart-13900894-f549-4d71-b009-ef3e7df63619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41328
6680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.413286680
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.769154215
Short name T493
Test name
Test status
Simulation time 231527694 ps
CPU time 29.07 seconds
Started Jun 24 06:44:00 PM PDT 24
Finished Jun 24 06:44:54 PM PDT 24
Peak memory 249056 kb
Host smart-ffdce243-b902-441d-a583-2fb88000bd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76915
4215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.769154215
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.36513468
Short name T94
Test name
Test status
Simulation time 5539600020 ps
CPU time 355.73 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 06:50:24 PM PDT 24
Peak memory 257296 kb
Host smart-9bbec323-fc29-4207-a953-daede7d842ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36513468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_hand
ler_stress_all.36513468
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3826121037
Short name T430
Test name
Test status
Simulation time 85690651447 ps
CPU time 1301.15 seconds
Started Jun 24 06:44:20 PM PDT 24
Finished Jun 24 07:06:11 PM PDT 24
Peak memory 270796 kb
Host smart-71ca70bb-c838-46ba-b538-5e80f4dfec27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826121037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3826121037
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1467724348
Short name T380
Test name
Test status
Simulation time 1897253261 ps
CPU time 156.2 seconds
Started Jun 24 06:44:16 PM PDT 24
Finished Jun 24 06:47:05 PM PDT 24
Peak memory 257284 kb
Host smart-becfec50-acd3-4ed9-b9d9-a162e4765949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
24348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1467724348
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4037388017
Short name T626
Test name
Test status
Simulation time 367648944 ps
CPU time 28.05 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 06:44:56 PM PDT 24
Peak memory 255344 kb
Host smart-545088e9-2f43-4d9d-9736-fc30c24ec377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
88017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4037388017
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.190117355
Short name T649
Test name
Test status
Simulation time 6561432760 ps
CPU time 646.91 seconds
Started Jun 24 06:44:17 PM PDT 24
Finished Jun 24 06:55:16 PM PDT 24
Peak memory 273160 kb
Host smart-36bca860-f3e4-4a91-9ce1-6681d8c98792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190117355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.190117355
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3941663397
Short name T297
Test name
Test status
Simulation time 9217759383 ps
CPU time 364.12 seconds
Started Jun 24 06:44:17 PM PDT 24
Finished Jun 24 06:50:33 PM PDT 24
Peak memory 248472 kb
Host smart-4bc1330b-ea46-45e8-adc9-432113e1df04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941663397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3941663397
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1069935551
Short name T54
Test name
Test status
Simulation time 6923411558 ps
CPU time 62.4 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 06:45:31 PM PDT 24
Peak memory 249412 kb
Host smart-44f901df-a86e-4436-9309-da3d63bc31f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
35551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1069935551
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.4157905961
Short name T116
Test name
Test status
Simulation time 6479167403 ps
CPU time 34.19 seconds
Started Jun 24 06:44:20 PM PDT 24
Finished Jun 24 06:45:04 PM PDT 24
Peak memory 255516 kb
Host smart-91591a25-6d78-47c9-a9b3-5431253093d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41579
05961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4157905961
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1800135579
Short name T272
Test name
Test status
Simulation time 688664687 ps
CPU time 22.15 seconds
Started Jun 24 06:44:17 PM PDT 24
Finished Jun 24 06:44:51 PM PDT 24
Peak memory 249044 kb
Host smart-570214eb-a16e-4a2c-86b7-3a17e07d1b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18001
35579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1800135579
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3621264912
Short name T497
Test name
Test status
Simulation time 310831372 ps
CPU time 18.23 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 06:44:46 PM PDT 24
Peak memory 249008 kb
Host smart-0ff7a516-5666-4628-ad39-7be613e349f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
64912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3621264912
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1557220865
Short name T190
Test name
Test status
Simulation time 95049444991 ps
CPU time 877.82 seconds
Started Jun 24 06:44:15 PM PDT 24
Finished Jun 24 06:59:06 PM PDT 24
Peak memory 284752 kb
Host smart-57679b80-5ccf-44f7-93ac-3eccf7b7c422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557220865 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1557220865
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2637454854
Short name T102
Test name
Test status
Simulation time 77683051212 ps
CPU time 1170.74 seconds
Started Jun 24 06:44:35 PM PDT 24
Finished Jun 24 07:04:10 PM PDT 24
Peak memory 271760 kb
Host smart-913feb8a-2a1c-4cb1-904e-afb8555255d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637454854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2637454854
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2791538506
Short name T383
Test name
Test status
Simulation time 2552555292 ps
CPU time 155.44 seconds
Started Jun 24 06:44:30 PM PDT 24
Finished Jun 24 06:47:09 PM PDT 24
Peak memory 249184 kb
Host smart-2388c12e-42d7-41c9-86be-e259781a8565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
38506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2791538506
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3288009336
Short name T189
Test name
Test status
Simulation time 756940483 ps
CPU time 50.68 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 06:45:24 PM PDT 24
Peak memory 255444 kb
Host smart-10f49298-2a1d-4945-a49c-84646c80ffd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
09336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3288009336
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.66412462
Short name T322
Test name
Test status
Simulation time 46098931701 ps
CPU time 1915.55 seconds
Started Jun 24 06:44:33 PM PDT 24
Finished Jun 24 07:16:33 PM PDT 24
Peak memory 283532 kb
Host smart-4ce0711c-e8e4-484b-bb05-ae84e585ec97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66412462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.66412462
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1032268034
Short name T425
Test name
Test status
Simulation time 154157681028 ps
CPU time 2305.47 seconds
Started Jun 24 06:44:32 PM PDT 24
Finished Jun 24 07:23:01 PM PDT 24
Peak memory 289220 kb
Host smart-c3a069a6-cc6c-48e4-8001-02040cabd510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032268034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1032268034
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.309886936
Short name T247
Test name
Test status
Simulation time 36364970796 ps
CPU time 387.9 seconds
Started Jun 24 06:44:32 PM PDT 24
Finished Jun 24 06:51:03 PM PDT 24
Peak memory 248724 kb
Host smart-e3bfcf35-3297-4100-8e55-206f5c4262b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309886936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.309886936
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.720144858
Short name T423
Test name
Test status
Simulation time 330358068 ps
CPU time 5.89 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 06:44:40 PM PDT 24
Peak memory 240768 kb
Host smart-66e6ebfa-607f-40bf-b353-70d5a98c8372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72014
4858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.720144858
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1755568734
Short name T459
Test name
Test status
Simulation time 130508635 ps
CPU time 4.96 seconds
Started Jun 24 06:44:30 PM PDT 24
Finished Jun 24 06:44:38 PM PDT 24
Peak memory 240836 kb
Host smart-0b6a43e1-8125-4c34-a2cb-bf65d1b46be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17555
68734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1755568734
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.623581358
Short name T518
Test name
Test status
Simulation time 784921454 ps
CPU time 14.05 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 06:44:48 PM PDT 24
Peak memory 248244 kb
Host smart-b456d46f-43b2-4aaa-9b20-e9c633bdbaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62358
1358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.623581358
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3125890621
Short name T426
Test name
Test status
Simulation time 1339475732 ps
CPU time 36.8 seconds
Started Jun 24 06:44:16 PM PDT 24
Finished Jun 24 06:45:06 PM PDT 24
Peak memory 249116 kb
Host smart-f136228f-eb5e-4e4c-b001-a97b6e8e3f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258
90621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3125890621
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.733561629
Short name T86
Test name
Test status
Simulation time 83338311186 ps
CPU time 1677.95 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 07:12:32 PM PDT 24
Peak memory 282056 kb
Host smart-f96ab83f-a425-47e3-a3ea-b981d144e76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733561629 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.733561629
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3701322391
Short name T61
Test name
Test status
Simulation time 231738199042 ps
CPU time 1250.71 seconds
Started Jun 24 06:44:37 PM PDT 24
Finished Jun 24 07:05:31 PM PDT 24
Peak memory 272692 kb
Host smart-9b286b11-db5c-4ecb-a076-8ec19635983f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701322391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3701322391
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1350713370
Short name T235
Test name
Test status
Simulation time 4274779679 ps
CPU time 73.02 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 06:45:48 PM PDT 24
Peak memory 257180 kb
Host smart-477bd97e-05c7-44ef-b9ca-68dab55de629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13507
13370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1350713370
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1918980581
Short name T491
Test name
Test status
Simulation time 521554408 ps
CPU time 14.69 seconds
Started Jun 24 06:44:30 PM PDT 24
Finished Jun 24 06:44:48 PM PDT 24
Peak memory 249108 kb
Host smart-23f73172-ff21-47d1-a13b-4fdceb3ffda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
80581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1918980581
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3314915820
Short name T303
Test name
Test status
Simulation time 52191518009 ps
CPU time 304.44 seconds
Started Jun 24 06:44:33 PM PDT 24
Finished Jun 24 06:49:41 PM PDT 24
Peak memory 248284 kb
Host smart-302b9dc4-a4bf-4f8b-a3a8-db1197d2c0d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314915820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3314915820
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2737767476
Short name T44
Test name
Test status
Simulation time 627528060 ps
CPU time 38.1 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 06:45:13 PM PDT 24
Peak memory 256212 kb
Host smart-4ede89c8-199f-4f17-9f96-ae2f8ad444c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
67476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2737767476
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3529671676
Short name T438
Test name
Test status
Simulation time 926434114 ps
CPU time 25.84 seconds
Started Jun 24 06:44:32 PM PDT 24
Finished Jun 24 06:45:01 PM PDT 24
Peak memory 256592 kb
Host smart-6b272478-3fcc-45f9-af7e-720288dbd4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296
71676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3529671676
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3288497025
Short name T599
Test name
Test status
Simulation time 205403348 ps
CPU time 15.61 seconds
Started Jun 24 06:44:33 PM PDT 24
Finished Jun 24 06:44:52 PM PDT 24
Peak memory 249412 kb
Host smart-def30c9b-8c22-4685-8c5c-67751f861bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
97025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3288497025
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3369970535
Short name T677
Test name
Test status
Simulation time 4324093141 ps
CPU time 63.29 seconds
Started Jun 24 06:44:35 PM PDT 24
Finished Jun 24 06:45:42 PM PDT 24
Peak memory 247984 kb
Host smart-de52483f-36ba-474a-a619-b996c0a448d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33699
70535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3369970535
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3245122857
Short name T285
Test name
Test status
Simulation time 189913051025 ps
CPU time 2297.96 seconds
Started Jun 24 06:44:31 PM PDT 24
Finished Jun 24 07:22:53 PM PDT 24
Peak memory 289608 kb
Host smart-f3f32f23-28f5-4099-a542-75c92c3efd75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245122857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3245122857
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3809742206
Short name T572
Test name
Test status
Simulation time 234556716698 ps
CPU time 1850.35 seconds
Started Jun 24 06:44:54 PM PDT 24
Finished Jun 24 07:15:48 PM PDT 24
Peak memory 282280 kb
Host smart-1dca4666-e750-4011-a90f-34b105c27a07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809742206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3809742206
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3743210929
Short name T556
Test name
Test status
Simulation time 3425686305 ps
CPU time 98.56 seconds
Started Jun 24 06:44:51 PM PDT 24
Finished Jun 24 06:46:34 PM PDT 24
Peak memory 257352 kb
Host smart-c3a82f20-19c4-40ca-92e8-3cfc1564c335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
10929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3743210929
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3462550313
Short name T622
Test name
Test status
Simulation time 545492949 ps
CPU time 6.97 seconds
Started Jun 24 06:44:52 PM PDT 24
Finished Jun 24 06:45:03 PM PDT 24
Peak memory 240968 kb
Host smart-f7c4fedf-3476-4575-9375-6d1bbe384024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625
50313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3462550313
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4184464019
Short name T399
Test name
Test status
Simulation time 31924315315 ps
CPU time 1887.88 seconds
Started Jun 24 06:44:50 PM PDT 24
Finished Jun 24 07:16:21 PM PDT 24
Peak memory 273344 kb
Host smart-2c00f4e8-8d0e-4336-b68d-70417e741d80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184464019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4184464019
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2475154588
Short name T315
Test name
Test status
Simulation time 5836209533 ps
CPU time 67.98 seconds
Started Jun 24 06:44:51 PM PDT 24
Finished Jun 24 06:46:03 PM PDT 24
Peak memory 248836 kb
Host smart-f1772dc1-b4ac-49cc-bc23-9ee2a743853b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475154588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2475154588
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3073292480
Short name T552
Test name
Test status
Simulation time 1484091096 ps
CPU time 49.75 seconds
Started Jun 24 06:44:52 PM PDT 24
Finished Jun 24 06:45:45 PM PDT 24
Peak memory 249120 kb
Host smart-5a882cfc-d888-4313-8e8b-9a5c7f3bdafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30732
92480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3073292480
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.419488508
Short name T453
Test name
Test status
Simulation time 1053489390 ps
CPU time 17.89 seconds
Started Jun 24 06:44:54 PM PDT 24
Finished Jun 24 06:45:16 PM PDT 24
Peak memory 255364 kb
Host smart-07445b4c-94fc-4d76-9bd3-b0d226385b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948
8508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.419488508
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1216894870
Short name T53
Test name
Test status
Simulation time 1306027114 ps
CPU time 34.54 seconds
Started Jun 24 06:44:52 PM PDT 24
Finished Jun 24 06:45:30 PM PDT 24
Peak memory 248908 kb
Host smart-4880b6c8-3074-4d24-9d3f-9716028ef976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12168
94870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1216894870
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.98876645
Short name T652
Test name
Test status
Simulation time 175493728 ps
CPU time 3.93 seconds
Started Jun 24 06:44:33 PM PDT 24
Finished Jun 24 06:44:40 PM PDT 24
Peak memory 240832 kb
Host smart-87917f09-d3d5-4b96-88a2-9b0c57f747c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98876
645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.98876645
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.959338233
Short name T449
Test name
Test status
Simulation time 2730274737 ps
CPU time 165.92 seconds
Started Jun 24 06:44:51 PM PDT 24
Finished Jun 24 06:47:41 PM PDT 24
Peak memory 257340 kb
Host smart-924e019c-d757-4886-a3b9-a6edf99cb467
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959338233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.959338233
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3923232910
Short name T673
Test name
Test status
Simulation time 121622446344 ps
CPU time 1820.59 seconds
Started Jun 24 06:45:10 PM PDT 24
Finished Jun 24 07:15:34 PM PDT 24
Peak memory 273232 kb
Host smart-537b468f-8643-4031-af28-3b4beaa2da3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923232910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3923232910
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2039273548
Short name T451
Test name
Test status
Simulation time 5036133468 ps
CPU time 263.43 seconds
Started Jun 24 06:44:51 PM PDT 24
Finished Jun 24 06:49:19 PM PDT 24
Peak memory 257320 kb
Host smart-fb3ba0b3-03e2-409b-8b6e-fe22c23c061e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20392
73548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2039273548
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1260626830
Short name T614
Test name
Test status
Simulation time 101357492 ps
CPU time 7.08 seconds
Started Jun 24 06:44:52 PM PDT 24
Finished Jun 24 06:45:03 PM PDT 24
Peak memory 250428 kb
Host smart-a036b50b-825c-49e8-9361-6dd9f3052943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12606
26830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1260626830
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2645467371
Short name T531
Test name
Test status
Simulation time 11140441486 ps
CPU time 802.68 seconds
Started Jun 24 06:45:10 PM PDT 24
Finished Jun 24 06:58:36 PM PDT 24
Peak memory 273660 kb
Host smart-8f9910df-2612-4f41-af7f-6d3868dedf66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645467371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2645467371
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2244789069
Short name T417
Test name
Test status
Simulation time 30230080060 ps
CPU time 1942.01 seconds
Started Jun 24 06:45:08 PM PDT 24
Finished Jun 24 07:17:34 PM PDT 24
Peak memory 284868 kb
Host smart-63ddb11c-466a-4649-aff2-3b2c744399f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244789069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2244789069
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3803091780
Short name T318
Test name
Test status
Simulation time 8294228451 ps
CPU time 86.47 seconds
Started Jun 24 06:45:08 PM PDT 24
Finished Jun 24 06:46:39 PM PDT 24
Peak memory 248492 kb
Host smart-bc83fdb1-b1c0-41e1-9ea8-c33f66b08ee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803091780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3803091780
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3805454587
Short name T480
Test name
Test status
Simulation time 723018092 ps
CPU time 19.69 seconds
Started Jun 24 06:44:54 PM PDT 24
Finished Jun 24 06:45:18 PM PDT 24
Peak memory 256660 kb
Host smart-6665995f-7aa2-4287-8760-02e0f707c24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38054
54587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3805454587
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3111928148
Short name T114
Test name
Test status
Simulation time 141400496 ps
CPU time 4.45 seconds
Started Jun 24 06:44:51 PM PDT 24
Finished Jun 24 06:44:58 PM PDT 24
Peak memory 240852 kb
Host smart-a7bf7cd1-628f-460c-b6df-8c2b7a7ff29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31119
28148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3111928148
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2269417968
Short name T534
Test name
Test status
Simulation time 2462730024 ps
CPU time 36.28 seconds
Started Jun 24 06:44:52 PM PDT 24
Finished Jun 24 06:45:33 PM PDT 24
Peak memory 248880 kb
Host smart-f002aa62-e015-4b2e-809f-b8a25c4d337b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22694
17968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2269417968
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.965934773
Short name T455
Test name
Test status
Simulation time 261485530 ps
CPU time 24.79 seconds
Started Jun 24 06:44:53 PM PDT 24
Finished Jun 24 06:45:21 PM PDT 24
Peak memory 249100 kb
Host smart-a2d1c185-5f0e-4a32-b216-274cd447c3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96593
4773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.965934773
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1771869919
Short name T287
Test name
Test status
Simulation time 166128735170 ps
CPU time 2261.15 seconds
Started Jun 24 06:45:07 PM PDT 24
Finished Jun 24 07:22:53 PM PDT 24
Peak memory 286512 kb
Host smart-c21f40bf-9a13-40ae-b1ee-6b105302e01c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771869919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1771869919
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2106651094
Short name T517
Test name
Test status
Simulation time 100259764026 ps
CPU time 1685.82 seconds
Started Jun 24 06:45:08 PM PDT 24
Finished Jun 24 07:13:18 PM PDT 24
Peak memory 285348 kb
Host smart-6c43df24-d494-4e0f-aaf8-569001d3b9a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106651094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2106651094
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3166220521
Short name T514
Test name
Test status
Simulation time 14825108354 ps
CPU time 220.26 seconds
Started Jun 24 06:45:09 PM PDT 24
Finished Jun 24 06:48:53 PM PDT 24
Peak memory 257336 kb
Host smart-9a3ee556-fb67-45e5-ae2d-a945ed17b156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
20521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3166220521
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.314874169
Short name T77
Test name
Test status
Simulation time 663304493 ps
CPU time 41.75 seconds
Started Jun 24 06:45:07 PM PDT 24
Finished Jun 24 06:45:54 PM PDT 24
Peak memory 256624 kb
Host smart-b076920f-29af-4d26-9326-24b7c2cf1256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31487
4169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.314874169
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2905124329
Short name T349
Test name
Test status
Simulation time 18304678717 ps
CPU time 826.34 seconds
Started Jun 24 06:45:13 PM PDT 24
Finished Jun 24 06:59:04 PM PDT 24
Peak memory 273912 kb
Host smart-7e8e1b27-c0a3-4c60-9f0c-fbe1773ba0fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905124329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2905124329
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2589921809
Short name T112
Test name
Test status
Simulation time 6642033555 ps
CPU time 691.3 seconds
Started Jun 24 06:45:07 PM PDT 24
Finished Jun 24 06:56:43 PM PDT 24
Peak memory 265640 kb
Host smart-68fd1adc-114d-4ad4-8ed3-d904d8936342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589921809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2589921809
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2080350973
Short name T230
Test name
Test status
Simulation time 7001208731 ps
CPU time 273.75 seconds
Started Jun 24 06:45:07 PM PDT 24
Finished Jun 24 06:49:46 PM PDT 24
Peak memory 256936 kb
Host smart-bc3bebe0-2df5-4946-8028-30b79c6acb1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080350973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2080350973
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1600460998
Short name T384
Test name
Test status
Simulation time 80250636 ps
CPU time 3.92 seconds
Started Jun 24 06:45:13 PM PDT 24
Finished Jun 24 06:45:22 PM PDT 24
Peak memory 240996 kb
Host smart-2f084121-b0dc-4081-ad0b-cc9f6b025b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
60998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1600460998
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2347365941
Short name T445
Test name
Test status
Simulation time 946742907 ps
CPU time 62.65 seconds
Started Jun 24 06:45:09 PM PDT 24
Finished Jun 24 06:46:16 PM PDT 24
Peak memory 249052 kb
Host smart-327db4fc-613a-47af-8c88-3dc645113ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23473
65941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2347365941
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3322001870
Short name T39
Test name
Test status
Simulation time 70389946 ps
CPU time 3.51 seconds
Started Jun 24 06:45:14 PM PDT 24
Finished Jun 24 06:45:22 PM PDT 24
Peak memory 239856 kb
Host smart-898abb1e-ff24-4292-9749-d5200e2204be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33220
01870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3322001870
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1173436818
Short name T668
Test name
Test status
Simulation time 716283338 ps
CPU time 39.12 seconds
Started Jun 24 06:45:08 PM PDT 24
Finished Jun 24 06:45:52 PM PDT 24
Peak memory 257092 kb
Host smart-5505009b-3b35-45f4-b2e2-9113dfc34544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11734
36818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1173436818
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.104955785
Short name T95
Test name
Test status
Simulation time 229216105996 ps
CPU time 3581.31 seconds
Started Jun 24 06:45:10 PM PDT 24
Finished Jun 24 07:44:55 PM PDT 24
Peak memory 283224 kb
Host smart-c1e83207-b92f-4f63-95c6-9a03c03e2d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104955785 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.104955785
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2950674171
Short name T217
Test name
Test status
Simulation time 236349742 ps
CPU time 3.12 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:40:50 PM PDT 24
Peak memory 249204 kb
Host smart-9c340d3c-13d5-4a66-8061-96ad01267cad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2950674171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2950674171
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3333365066
Short name T675
Test name
Test status
Simulation time 283959879269 ps
CPU time 2496.37 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 07:22:26 PM PDT 24
Peak memory 273644 kb
Host smart-90284e62-7acd-48ad-95bd-e7e60aa7e581
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333365066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3333365066
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3101005328
Short name T590
Test name
Test status
Simulation time 680143660 ps
CPU time 29.26 seconds
Started Jun 24 06:40:41 PM PDT 24
Finished Jun 24 06:41:14 PM PDT 24
Peak memory 240924 kb
Host smart-5718adfb-0d5a-4cd5-a982-602aaa35f848
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3101005328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3101005328
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1048015293
Short name T90
Test name
Test status
Simulation time 4294457884 ps
CPU time 186.58 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:43:53 PM PDT 24
Peak memory 251460 kb
Host smart-3e318f2d-8be8-4e53-bd27-28731f2a7b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
15293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1048015293
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2175440916
Short name T551
Test name
Test status
Simulation time 692222323 ps
CPU time 44.12 seconds
Started Jun 24 06:40:40 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 248220 kb
Host smart-b692ced3-f443-4300-beb8-c15d38ba93ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
40916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2175440916
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1689678460
Short name T666
Test name
Test status
Simulation time 103373311227 ps
CPU time 1372.92 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 07:03:38 PM PDT 24
Peak memory 272920 kb
Host smart-dec23e1e-741e-4136-96c8-547a9fc74406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689678460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1689678460
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3288017166
Short name T311
Test name
Test status
Simulation time 9634189036 ps
CPU time 200.96 seconds
Started Jun 24 06:40:41 PM PDT 24
Finished Jun 24 06:44:05 PM PDT 24
Peak memory 248824 kb
Host smart-c549950a-b309-4336-8115-ba2ec5987b80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288017166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3288017166
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1394966579
Short name T186
Test name
Test status
Simulation time 456490571 ps
CPU time 39.72 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:41:28 PM PDT 24
Peak memory 256228 kb
Host smart-6fb47f53-dca7-4c17-8321-1b328aef1804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
66579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1394966579
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3188893480
Short name T704
Test name
Test status
Simulation time 665931482 ps
CPU time 39.05 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:41:29 PM PDT 24
Peak memory 249040 kb
Host smart-caae6b8e-19c6-4fda-8cc2-08d863b4e397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
93480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3188893480
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2331302966
Short name T111
Test name
Test status
Simulation time 221227062 ps
CPU time 13.14 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:41:00 PM PDT 24
Peak memory 253652 kb
Host smart-e5719bf6-ad5d-46ae-ab3c-411f0d7d4aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
02966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2331302966
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2435078762
Short name T503
Test name
Test status
Simulation time 16479701900 ps
CPU time 55.64 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:41:41 PM PDT 24
Peak memory 249444 kb
Host smart-2dabd6f6-91f7-4693-8c29-927c9cc9ce2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
78762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2435078762
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1836731556
Short name T26
Test name
Test status
Simulation time 94077817496 ps
CPU time 1669.54 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 07:08:37 PM PDT 24
Peak memory 273640 kb
Host smart-7047f46f-2657-41bc-9f86-b990a66c0e5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836731556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1836731556
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1255834805
Short name T213
Test name
Test status
Simulation time 47772618 ps
CPU time 2.75 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:40:49 PM PDT 24
Peak memory 249248 kb
Host smart-a1250e2f-4cfe-4240-8857-57233d5bbc28
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1255834805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1255834805
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3088231246
Short name T115
Test name
Test status
Simulation time 47125202747 ps
CPU time 1240.67 seconds
Started Jun 24 06:40:35 PM PDT 24
Finished Jun 24 07:01:17 PM PDT 24
Peak memory 271860 kb
Host smart-9483e354-9091-482e-9a68-6e653a531837
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088231246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3088231246
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2176238235
Short name T127
Test name
Test status
Simulation time 683002493 ps
CPU time 9.57 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:40:59 PM PDT 24
Peak memory 249116 kb
Host smart-aaba7059-8e9a-480f-a03c-9a0b7d66e580
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2176238235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2176238235
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4032212870
Short name T561
Test name
Test status
Simulation time 1097398038 ps
CPU time 93.79 seconds
Started Jun 24 06:40:41 PM PDT 24
Finished Jun 24 06:42:18 PM PDT 24
Peak memory 250416 kb
Host smart-a62d5e1a-24dd-4ebe-8373-a83df4f66b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322
12870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4032212870
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1447845888
Short name T570
Test name
Test status
Simulation time 3847332883 ps
CPU time 41.02 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:41:26 PM PDT 24
Peak memory 249344 kb
Host smart-7a723fa9-6770-4fa4-8a8b-c1edfc3a8e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478
45888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1447845888
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.719710730
Short name T477
Test name
Test status
Simulation time 137225995811 ps
CPU time 1202.87 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 07:00:51 PM PDT 24
Peak memory 282820 kb
Host smart-0e5c3e98-8ab3-4145-98ba-317aef99d924
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719710730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.719710730
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1051215262
Short name T109
Test name
Test status
Simulation time 77962339183 ps
CPU time 1183.83 seconds
Started Jun 24 06:40:41 PM PDT 24
Finished Jun 24 07:00:28 PM PDT 24
Peak memory 273696 kb
Host smart-80476d56-8e65-453a-8bd1-24aef21840f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051215262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1051215262
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3541189927
Short name T321
Test name
Test status
Simulation time 20214764539 ps
CPU time 220.68 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:44:30 PM PDT 24
Peak memory 248548 kb
Host smart-b26c3be8-6001-4c4d-8790-bee0a3684cfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541189927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3541189927
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3902681795
Short name T660
Test name
Test status
Simulation time 3201626290 ps
CPU time 33.34 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 06:41:25 PM PDT 24
Peak memory 256984 kb
Host smart-661a3874-4225-459f-a298-a8e04cbab3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
81795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3902681795
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3720770985
Short name T494
Test name
Test status
Simulation time 835981405 ps
CPU time 22.3 seconds
Started Jun 24 06:40:44 PM PDT 24
Finished Jun 24 06:41:13 PM PDT 24
Peak memory 248160 kb
Host smart-ca7b2d1d-770e-4df8-9b02-1b310181b70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37207
70985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3720770985
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4017130472
Short name T651
Test name
Test status
Simulation time 189848961 ps
CPU time 19.86 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:41:06 PM PDT 24
Peak memory 256956 kb
Host smart-d70b7384-c146-4499-8079-6f1c5794b1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
30472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4017130472
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1260236034
Short name T404
Test name
Test status
Simulation time 327564751 ps
CPU time 30.58 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:41:20 PM PDT 24
Peak memory 249032 kb
Host smart-e1c9eb01-fa1b-4890-866a-987739a384e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12602
36034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1260236034
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3209198603
Short name T70
Test name
Test status
Simulation time 84264989883 ps
CPU time 2385.12 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 07:20:35 PM PDT 24
Peak memory 290160 kb
Host smart-71a15e94-27b5-4d43-9c63-834a78c2fe86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209198603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3209198603
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1126416067
Short name T222
Test name
Test status
Simulation time 43435394 ps
CPU time 3.54 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 06:40:56 PM PDT 24
Peak memory 249252 kb
Host smart-3c66465a-ae43-4c70-8c69-8548a9ec4d2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1126416067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1126416067
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1815150245
Short name T541
Test name
Test status
Simulation time 19214478978 ps
CPU time 1261.02 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 07:01:49 PM PDT 24
Peak memory 272012 kb
Host smart-12b6ac4c-c9b0-4e78-8353-6b630bfd1d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815150245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1815150245
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1580363614
Short name T548
Test name
Test status
Simulation time 842850491 ps
CPU time 21.36 seconds
Started Jun 24 06:40:46 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 249116 kb
Host smart-006a8889-7fe2-4655-ac8e-37ec5af4a7cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1580363614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1580363614
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1719446708
Short name T544
Test name
Test status
Simulation time 2527911170 ps
CPU time 39.6 seconds
Started Jun 24 06:40:44 PM PDT 24
Finished Jun 24 06:41:30 PM PDT 24
Peak memory 257280 kb
Host smart-949087d0-c29c-49cd-a408-855643594efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
46708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1719446708
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.60450651
Short name T129
Test name
Test status
Simulation time 6131808229 ps
CPU time 47.93 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:41:38 PM PDT 24
Peak memory 249172 kb
Host smart-9264a69b-47d7-4b64-9e1e-0c3aedf7c41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60450
651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.60450651
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3415422998
Short name T317
Test name
Test status
Simulation time 47820166159 ps
CPU time 1133.74 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:59:42 PM PDT 24
Peak memory 273248 kb
Host smart-0444456b-8f67-47d5-a4b7-5e8a51730df0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415422998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3415422998
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1301906233
Short name T452
Test name
Test status
Simulation time 65840256716 ps
CPU time 1384.41 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 07:03:54 PM PDT 24
Peak memory 289900 kb
Host smart-c793b44d-00b5-4ed0-851c-f183cd14d689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301906233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1301906233
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.555299617
Short name T306
Test name
Test status
Simulation time 2301142490 ps
CPU time 102.24 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:42:32 PM PDT 24
Peak memory 248660 kb
Host smart-55a4f5a6-1881-47ce-9f70-a5565a32a621
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555299617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.555299617
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4224690128
Short name T443
Test name
Test status
Simulation time 37929756 ps
CPU time 4.85 seconds
Started Jun 24 06:40:42 PM PDT 24
Finished Jun 24 06:40:53 PM PDT 24
Peak memory 254012 kb
Host smart-faf09b20-0efc-4ea7-89a5-bbeda1c4814a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
90128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4224690128
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.236756616
Short name T118
Test name
Test status
Simulation time 149246033 ps
CPU time 15.8 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 06:41:08 PM PDT 24
Peak memory 255876 kb
Host smart-e55fe9ae-7050-4f3b-9842-71689af38a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
6616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.236756616
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2154734911
Short name T702
Test name
Test status
Simulation time 605627844 ps
CPU time 20.21 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:41:10 PM PDT 24
Peak memory 256408 kb
Host smart-13205d67-3913-40d7-baaa-479cf3d705b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21547
34911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2154734911
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.978832167
Short name T421
Test name
Test status
Simulation time 222756606 ps
CPU time 25.83 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 249028 kb
Host smart-bdd7ec86-ef1b-49db-bf01-809e340cdeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97883
2167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.978832167
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3547209732
Short name T644
Test name
Test status
Simulation time 104030818996 ps
CPU time 2876.44 seconds
Started Jun 24 06:40:46 PM PDT 24
Finished Jun 24 07:28:50 PM PDT 24
Peak memory 289536 kb
Host smart-886913de-86a3-481f-a8e6-9cf59799f94c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547209732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3547209732
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3173256782
Short name T200
Test name
Test status
Simulation time 61128677378 ps
CPU time 1635.05 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 07:08:07 PM PDT 24
Peak memory 289864 kb
Host smart-1b00f060-e0d4-47cb-96e9-751deb9a8acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173256782 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3173256782
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.4245808617
Short name T36
Test name
Test status
Simulation time 46603264 ps
CPU time 3.94 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:09 PM PDT 24
Peak memory 249160 kb
Host smart-ad0da3cd-c222-44bf-b4fd-36c9d011f309
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4245808617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4245808617
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1736769698
Short name T629
Test name
Test status
Simulation time 17054962469 ps
CPU time 717.24 seconds
Started Jun 24 06:40:43 PM PDT 24
Finished Jun 24 06:52:46 PM PDT 24
Peak memory 265548 kb
Host smart-82ac0701-2854-42b6-b6d6-247ef4d219ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736769698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1736769698
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2343613816
Short name T126
Test name
Test status
Simulation time 2605111995 ps
CPU time 26.86 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:41:27 PM PDT 24
Peak memory 249104 kb
Host smart-4c38c7fd-d2a4-4ca1-b806-022b416e3b0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2343613816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2343613816
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1932144256
Short name T612
Test name
Test status
Simulation time 265429222 ps
CPU time 11.11 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 06:41:03 PM PDT 24
Peak memory 256376 kb
Host smart-5500723e-ee1d-4cce-bd88-9db3b9e1552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321
44256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1932144256
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3330045357
Short name T21
Test name
Test status
Simulation time 1039851993 ps
CPU time 56.28 seconds
Started Jun 24 06:40:46 PM PDT 24
Finished Jun 24 06:41:48 PM PDT 24
Peak memory 249112 kb
Host smart-641f4c96-a8d0-4b7a-9ed6-98dd7ae5b1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33300
45357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3330045357
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1733626196
Short name T484
Test name
Test status
Simulation time 77570057126 ps
CPU time 2448.79 seconds
Started Jun 24 06:40:55 PM PDT 24
Finished Jun 24 07:21:52 PM PDT 24
Peak memory 289512 kb
Host smart-7b633151-f7bd-471c-b4c3-69ebd70a403d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733626196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1733626196
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.299665168
Short name T406
Test name
Test status
Simulation time 28798696809 ps
CPU time 1075.88 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:59:04 PM PDT 24
Peak memory 273420 kb
Host smart-2965fcfd-d442-427a-aeaa-05320315b440
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299665168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.299665168
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3026485408
Short name T92
Test name
Test status
Simulation time 29017695125 ps
CPU time 380.51 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:47:26 PM PDT 24
Peak memory 248048 kb
Host smart-9bc034e1-413a-455e-badb-a6c742ccf0a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026485408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3026485408
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.289422160
Short name T568
Test name
Test status
Simulation time 257778474 ps
CPU time 22.72 seconds
Started Jun 24 06:40:46 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 256260 kb
Host smart-7af7e8af-d65e-4ecc-beee-7318c3c8d3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
2160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.289422160
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1951467114
Short name T553
Test name
Test status
Simulation time 1568829562 ps
CPU time 24.67 seconds
Started Jun 24 06:40:45 PM PDT 24
Finished Jun 24 06:41:17 PM PDT 24
Peak memory 256068 kb
Host smart-5564ab5e-690d-403b-86f7-ccaddabc0f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19514
67114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1951467114
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2076989520
Short name T288
Test name
Test status
Simulation time 1298952329 ps
CPU time 40.44 seconds
Started Jun 24 06:40:46 PM PDT 24
Finished Jun 24 06:41:33 PM PDT 24
Peak memory 249040 kb
Host smart-26e863b2-8454-455e-9777-d342778a1964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20769
89520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2076989520
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2748868713
Short name T522
Test name
Test status
Simulation time 152889337 ps
CPU time 6.5 seconds
Started Jun 24 06:40:44 PM PDT 24
Finished Jun 24 06:40:56 PM PDT 24
Peak memory 249148 kb
Host smart-dc944379-54cd-4235-853f-3953f9cafcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
68713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2748868713
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2579831962
Short name T703
Test name
Test status
Simulation time 25204040740 ps
CPU time 858.62 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 06:55:22 PM PDT 24
Peak memory 265500 kb
Host smart-3615e390-9527-41c8-9fc3-03f9e689aff7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579831962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2579831962
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.621855121
Short name T219
Test name
Test status
Simulation time 31724326 ps
CPU time 3.3 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:11 PM PDT 24
Peak memory 248944 kb
Host smart-c85f36dc-61d5-4738-84ae-bc294347afa4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=621855121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.621855121
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1710931420
Short name T50
Test name
Test status
Simulation time 15281798111 ps
CPU time 1239.23 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 07:01:44 PM PDT 24
Peak memory 287672 kb
Host smart-cd783e3e-e305-4878-bcff-956e90d4deaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710931420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1710931420
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1730548741
Short name T405
Test name
Test status
Simulation time 1036270402 ps
CPU time 28.11 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:41:28 PM PDT 24
Peak memory 249068 kb
Host smart-b9ca72f0-a3bc-48aa-97e9-faca8d455187
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1730548741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1730548741
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3163346139
Short name T382
Test name
Test status
Simulation time 2447861619 ps
CPU time 67.97 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:42:08 PM PDT 24
Peak memory 257348 kb
Host smart-2315e86c-990d-4ec5-98a0-22bb3b1df79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31633
46139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3163346139
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2325073500
Short name T290
Test name
Test status
Simulation time 8418659258 ps
CPU time 48.38 seconds
Started Jun 24 06:40:59 PM PDT 24
Finished Jun 24 06:41:56 PM PDT 24
Peak memory 256168 kb
Host smart-8ecf19a8-56d8-4fbc-8b63-bfe72eb91873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
73500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2325073500
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4224122063
Short name T638
Test name
Test status
Simulation time 11665315893 ps
CPU time 1033.34 seconds
Started Jun 24 06:40:55 PM PDT 24
Finished Jun 24 06:58:16 PM PDT 24
Peak memory 273648 kb
Host smart-09151be1-800e-440c-9896-8e43257715b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224122063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4224122063
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2048733010
Short name T435
Test name
Test status
Simulation time 39101461025 ps
CPU time 1067.52 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:58:48 PM PDT 24
Peak memory 289596 kb
Host smart-b0ffd237-4862-4991-b397-32c19de3592f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048733010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2048733010
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2877678509
Short name T331
Test name
Test status
Simulation time 54533262360 ps
CPU time 531.73 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:49:52 PM PDT 24
Peak memory 248724 kb
Host smart-4cd56dad-0c0a-4ae3-8a33-696874776641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877678509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2877678509
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1125910361
Short name T469
Test name
Test status
Simulation time 3664993030 ps
CPU time 52.67 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:59 PM PDT 24
Peak memory 249100 kb
Host smart-80031c3a-754c-4648-bc83-57f8d739a89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
10361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1125910361
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2692664486
Short name T454
Test name
Test status
Simulation time 1357129394 ps
CPU time 44.02 seconds
Started Jun 24 06:40:54 PM PDT 24
Finished Jun 24 06:41:44 PM PDT 24
Peak memory 256096 kb
Host smart-d525b9c4-9dca-4be3-8c76-4f5c55994546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
64486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2692664486
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3228752222
Short name T48
Test name
Test status
Simulation time 1985841270 ps
CPU time 32.15 seconds
Started Jun 24 06:40:58 PM PDT 24
Finished Jun 24 06:41:39 PM PDT 24
Peak memory 256136 kb
Host smart-97b3b707-a82e-4ebd-b306-2a6bdfb333f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
52222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3228752222
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1607520977
Short name T431
Test name
Test status
Simulation time 1114522109 ps
CPU time 12.07 seconds
Started Jun 24 06:41:02 PM PDT 24
Finished Jun 24 06:41:24 PM PDT 24
Peak memory 253424 kb
Host smart-e6ab46f9-4622-4a5d-8b2e-6ce5b31b9cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
20977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1607520977
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.743430014
Short name T582
Test name
Test status
Simulation time 8099144550 ps
CPU time 868.46 seconds
Started Jun 24 06:40:57 PM PDT 24
Finished Jun 24 06:55:34 PM PDT 24
Peak memory 273528 kb
Host smart-7786be55-a906-4805-8a81-859effde0ce8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743430014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.743430014
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2668577342
Short name T625
Test name
Test status
Simulation time 30417470598 ps
CPU time 2230.42 seconds
Started Jun 24 06:40:56 PM PDT 24
Finished Jun 24 07:18:15 PM PDT 24
Peak memory 289468 kb
Host smart-593bdb1a-91e2-421e-843a-ec5047ee0baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668577342 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2668577342
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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