Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	56275	1			T19	319		T25	92		T26	166
class_i[0x1]	23387	1			T47	17		T25	4		T15	19
class_i[0x2]	83834	1			T19	725		T4	11		T26	1964
class_i[0x3]	68583	1			T4	4102		T5	2		T47	11

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	58853	1			T19	255		T4	1006		T5	1
alert[0x1]	56359	1			T19	218		T4	1013		T5	1
alert[0x2]	58504	1			T19	258		T4	1071		T47	2
alert[0x3]	58363	1			T19	313		T4	1023		T47	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

231806

1

T19

1044

T4

4113

T47

28

esc_ping_fail

273

1

T5

2

T8

10

T9

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	58777	1			T19	255		T4	1006		T47	11
esc_integrity_fail	alert[0x1]	56280	1			T19	218		T4	1013		T47	13
esc_integrity_fail	alert[0x2]	58436	1			T19	258		T4	1071		T47	2
esc_integrity_fail	alert[0x3]	58313	1			T19	313		T4	1023		T47	2
esc_ping_fail	alert[0x0]	76	1			T5	1		T8	3		T224	4
esc_ping_fail	alert[0x1]	79	1			T5	1		T8	2		T9	1
esc_ping_fail	alert[0x2]	68	1			T8	3		T224	3		T287	1
esc_ping_fail	alert[0x3]	50	1			T8	2		T9	1		T287	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	56190	1			T19	319		T25	92		T26	166
esc_integrity_fail	class_i[0x1]	23337	1			T47	17		T25	4		T15	19
esc_integrity_fail	class_i[0x2]	83735	1			T19	725		T4	11		T26	1964
esc_integrity_fail	class_i[0x3]	68544	1			T4	4102		T47	11		T25	4113
esc_ping_fail	class_i[0x0]	85	1			T301	1		T288	10		T285	1
esc_ping_fail	class_i[0x1]	50	1			T224	1		T287	3		T245	6
esc_ping_fail	class_i[0x2]	99	1			T8	10		T224	6		T245	2
esc_ping_fail	class_i[0x3]	39	1			T5	2		T9	2		T224	1