Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	675576662	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	675576662	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	675576662	675418211	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	675576662	675418211	0	0
tb.dut.EdnKnownO_A	0	0	675576662	675418211	0	0
tb.dut.EscPKnownO_A	0	0	675576662	675418211	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	675576662	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	675576662	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	675576662	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	675576662	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	675576662	70	0	0
tb.dut.IrqAKnownO_A	0	0	675576662	675418211	0	0
tb.dut.IrqBKnownO_A	0	0	675576662	675418211	0	0
tb.dut.IrqCKnownO_A	0	0	675576662	675418211	0	0
tb.dut.IrqDKnownO_A	0	0	675576662	675418211	0	0
tb.dut.TlAReadyKnownO_A	0	0	675576662	675418211	0	0
tb.dut.TlDValidKnownO_A	0	0	675576662	675418211	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	701426102	2440220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	701426102	16213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	701426102	17375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	701426102	16311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	701426102	18173	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	701426102	15922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	701426102	17289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	701426102	16010	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	701426102	15220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	701426102	17250	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	701426102	18616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	701426102	17153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	701426102	15869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	701426102	17200	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	701426102	18455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	701426102	16165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	701426102	17912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	701426102	17575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	701426102	15787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	701426102	16403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	701426102	16204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	701426102	17743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	701426102	18407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	701426102	17413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	701426102	16168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	701426102	16089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	701426102	17149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	701426102	17558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	701426102	14880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	701426102	16966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	701426102	16056	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	701426102	15059	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	701426102	14839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	701426102	16175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	701426102	16338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	701426102	17569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	701426102	16401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	701426102	15134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	701426102	17270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	701426102	17667	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	701426102	16407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	701426102	18234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	701426102	16245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	701426102	17399	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	701426102	15256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	701426102	18523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	701426102	18475	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	701426102	16174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	701426102	16210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	701426102	16409	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	701426102	15987	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	701426102	17731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	701426102	14985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	701426102	17382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	701426102	17129	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	701426102	17090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	701426102	17268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	701426102	16122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	701426102	17376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	701426102	17813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	701426102	16172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	701426102	15926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	701426102	16345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	701426102	17191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	701426102	16025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	701426102	15790	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	701426102	15055	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	701426102	17423	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	701426102	16138	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	701426102	16233	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	701426102	31015	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	701426102	15996	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	701426102	17228	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	701426102	16304	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	701426102	17390	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	701426102	17366	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	701426102	16032	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	701426102	16013	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	701426102	15738	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	675576662	3610	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	675576662	247726	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	675576662	296037030	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	675576662	274	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	675576662	803	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	675576662	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	675576662	381	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	675401778	225525826	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	675576662	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	675576662	868	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	675576662	853	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	675576662	831	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	675576662	1187	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	675576662	147701	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	675576662	1076	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	675576662	56	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675576662	1224	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	675576662	1014	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	675400228	675331794	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	675576662	675418211	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	675576662	778	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	675576662	147719	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	675576662	416144516	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	675576662	275	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	675576662	475	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	675576662	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	675576662	243	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	675401778	341439011	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	675576662	559	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	675576662	551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	675576662	542	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	675576662	531	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	675576662	1581	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	675576662	199270	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	675576662	1486	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	675576662	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675576662	1293	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	675576662	1083	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	675400228	675331794	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	675576662	675418211	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	675576662	6356	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	675576662	167324	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	675576662	399532914	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	675576662	260	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	675576662	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	675576662	29	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	675576662	240	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	675401778	314722032	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	675576662	589	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	675576662	579	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	675576662	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	675576662	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	675576662	584	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	675576662	87046	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	675576662	494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	675576662	61	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675576662	1255	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	675576662	1045	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	675400228	675331794	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	675576662	675418211	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	675576662	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	675576662	2545	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	675576662	224094	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	675576662	378220254	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	675576662	227	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	675576662	469	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	675576662	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	675576662	197	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	675401778	313244042	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	675576662	533	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	675576662	520	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	675576662	509	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	675576662	499	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	675576662	1054	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	675576662	138383	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	675576662	983	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	675576662	53	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675576662	1267	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	675576662	1057	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	675400228	675331794	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	675576662	675418211	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	701426102	121851079	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	701426102	700752548	0	0
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