Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T25	1		T15	1		T31	1
class_index[0x1]	69	1			T25	1		T31	7		T52	1
class_index[0x2]	61	1			T25	2		T15	1		T31	1
class_index[0x3]	53	1			T25	1		T26	2		T75	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	77	1			T25	2		T26	2		T31	1
intr_timeout_cnt[1]	54	1			T25	1		T15	1		T31	6
intr_timeout_cnt[2]	38	1			T15	1		T75	2		T53	1
intr_timeout_cnt[3]	10	1			T234	1		T262	1		T263	2
intr_timeout_cnt[4]	16	1			T25	1		T31	1		T53	1
intr_timeout_cnt[5]	12	1			T88	1		T231	3		T264	1
intr_timeout_cnt[6]	9	1			T53	1		T84	1		T85	1
intr_timeout_cnt[7]	14	1			T25	1		T53	1		T81	1
intr_timeout_cnt[8]	5	1			T23	1		T61	1		T265	1
intr_timeout_cnt[9]	4	1			T31	1		T84	1		T100	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	21	1			T25	1		T23	2		T83	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T15	1		T80	1		T23	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T57	1		T29	2		T215	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T263	2		T229	1		T266	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T262	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T267	1		T268	1		T269	1
class_index[0x0]	intr_timeout_cnt[6]	4	1			T87	2		T100	1		T270	1
class_index[0x0]	intr_timeout_cnt[7]	5	1			T53	1		T81	1		T228	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T31	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	20	1			T52	1		T80	1		T87	1
class_index[0x1]	intr_timeout_cnt[1]	18	1			T31	6		T23	1		T57	1
class_index[0x1]	intr_timeout_cnt[2]	12	1			T75	1		T23	1		T84	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T271	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	7	1			T25	1		T31	1		T88	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T231	3		T267	1		T268	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T53	1		T264	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T235	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T23	1		T102	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	19	1			T25	1		T31	1		T79	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T79	1		T53	1		T83	1
class_index[0x2]	intr_timeout_cnt[2]	13	1			T15	1		T23	1		T88	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T262	1		T272	1		T273	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T53	1		T233	1		T265	2
class_index[0x2]	intr_timeout_cnt[5]	1	1			T112	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T85	1		T274	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	7	1			T25	1		T275	2		T100	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T61	1		T276	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T84	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T26	2		T277	1		T278	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T25	1		T75	1		T23	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T75	1		T53	1		T33	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T234	1		T279	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T61	1		T247	1		T280	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T88	1		T264	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T84	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T215	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T265	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T100	1		T281	1		-	-