Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339355	1			T1	17		T2	35		T3	1143
all_values[1]	339355	1			T1	17		T2	35		T3	1143
all_values[2]	339355	1			T1	17		T2	35		T3	1143
all_values[3]	339355	1			T1	17		T2	35		T3	1143

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676326

1

T1

29

T2

71

T3

2243

auto[1]

681094

1

T1

39

T2

69

T3

2329

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810645

1

T1

36

T2

74

T3

4068

auto[1]

546775

1

T1

32

T2

66

T3

504

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97975	1			T1	2		T2	12		T3	562
all_values[0]	auto[0]	auto[1]	71247	1			T1	1		T2	11		T6	7
all_values[0]	auto[1]	auto[0]	98971	1			T1	7		T2	6		T3	580
all_values[0]	auto[1]	auto[1]	71162	1			T1	7		T2	6		T3	1
all_values[1]	auto[0]	auto[0]	101837	1			T1	2		T2	10		T3	554
all_values[1]	auto[0]	auto[1]	67009	1			T1	2		T2	8		T6	7
all_values[1]	auto[1]	auto[0]	102998	1			T1	7		T2	10		T3	589
all_values[1]	auto[1]	auto[1]	67511	1			T1	6		T2	7		T6	4
all_values[2]	auto[0]	auto[0]	101859	1			T1	6		T2	7		T3	317
all_values[2]	auto[0]	auto[1]	67637	1			T1	5		T2	7		T3	258
all_values[2]	auto[1]	auto[0]	102452	1			T1	3		T2	11		T3	326
all_values[2]	auto[1]	auto[1]	67407	1			T1	3		T2	10		T3	242
all_values[3]	auto[0]	auto[0]	101474	1			T1	6		T2	8		T3	549
all_values[3]	auto[0]	auto[1]	67288	1			T1	5		T2	8		T3	3
all_values[3]	auto[1]	auto[0]	103079	1			T1	3		T2	10		T3	591
all_values[3]	auto[1]	auto[1]	67514	1			T1	3		T2	9		T6	6