Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	339355	1			T1	17		T2	35		T3	1143
all_pins[1]	339355	1			T1	17		T2	35		T3	1143
all_pins[2]	339355	1			T1	17		T2	35		T3	1143
all_pins[3]	339355	1			T1	17		T2	35		T3	1143

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1083826	1			T1	49		T2	108		T3	4329
values[0x1]	273594	1			T1	19		T2	32		T3	243
transitions[0x0=>0x1]	182504	1			T1	11		T2	18		T3	243
transitions[0x1=>0x0]	182762	1			T1	12		T2	18		T3	243

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	268193	1			T1	10		T2	29		T3	1142
all_pins[0]	values[0x1]	71162	1			T1	7		T2	6		T3	1
all_pins[0]	transitions[0x0=>0x1]	70569	1			T1	6		T2	6		T3	1
all_pins[0]	transitions[0x1=>0x0]	67179	1			T1	3		T2	9		T6	6
all_pins[1]	values[0x0]	271844	1			T1	11		T2	28		T3	1143
all_pins[1]	values[0x1]	67511	1			T1	6		T2	7		T6	4
all_pins[1]	transitions[0x0=>0x1]	36843	1			T1	1		T2	5		T6	1
all_pins[1]	transitions[0x1=>0x0]	40494	1			T1	2		T2	4		T3	1
all_pins[2]	values[0x0]	271948	1			T1	14		T2	25		T3	901
all_pins[2]	values[0x1]	67407	1			T1	3		T2	10		T3	242
all_pins[2]	transitions[0x0=>0x1]	37725	1			T1	1		T2	5		T3	242
all_pins[2]	transitions[0x1=>0x0]	37829	1			T1	4		T2	2		T6	1
all_pins[3]	values[0x0]	271841	1			T1	14		T2	26		T3	1143
all_pins[3]	values[0x1]	67514	1			T1	3		T2	9		T6	6
all_pins[3]	transitions[0x0=>0x1]	37367	1			T1	3		T2	2		T6	3
all_pins[3]	transitions[0x1=>0x0]	37260	1			T1	3		T2	3		T3	242