Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82173	1			T4	371		T13	617		T25	592
accum_cnt_1000	223278	1			T3	733		T19	348		T20	96
accum_cnt_100	26050	1			T3	64		T18	33		T19	114
accum_cnt_50	61087	1			T2	44		T3	54		T6	2
accum_cnt_10	160675	1			T1	17		T2	21		T3	683
accum_cnt_0	404307	1			T1	15		T2	31		T3	1958

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251183	1			T1	8		T2	24		T3	873
class_index[0x1]	251183	1			T1	8		T2	24		T3	873
class_index[0x2]	251183	1			T1	8		T2	24		T3	873
class_index[0x3]	251183	1			T1	8		T2	24		T3	873

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24433	1			T4	371		T13	389		T25	283
class_index[0x0]	accum_cnt_1000	70547	1			T19	70		T4	677		T7	580
class_index[0x0]	accum_cnt_100	8411	1			T19	24		T4	39		T7	118
class_index[0x0]	accum_cnt_50	15736	1			T2	14		T19	42		T4	31
class_index[0x0]	accum_cnt_10	40599	1			T1	3		T2	6		T6	24
class_index[0x0]	accum_cnt_0	77882	1			T1	5		T2	4		T3	873
class_index[0x1]	accum_cnt_2000	16342	1			T13	58		T79	275		T54	323
class_index[0x1]	accum_cnt_1000	48289	1			T19	145		T20	41		T7	489
class_index[0x1]	accum_cnt_100	5438	1			T18	17		T19	45		T20	21
class_index[0x1]	accum_cnt_50	16666	1			T18	19		T19	38		T20	17
class_index[0x1]	accum_cnt_10	39633	1			T6	24		T18	3		T19	10
class_index[0x1]	accum_cnt_0	116937	1			T1	8		T2	24		T3	873
class_index[0x2]	accum_cnt_2000	20258	1			T26	586		T16	516		T17	208
class_index[0x2]	accum_cnt_1000	54242	1			T3	733		T20	55		T13	831
class_index[0x2]	accum_cnt_100	6745	1			T3	64		T18	16		T20	16
class_index[0x2]	accum_cnt_50	14942	1			T2	15		T3	54		T6	2
class_index[0x2]	accum_cnt_10	40559	1			T1	6		T2	8		T3	16
class_index[0x2]	accum_cnt_0	105670	1			T1	2		T2	1		T3	6
class_index[0x3]	accum_cnt_2000	21140	1			T13	170		T25	309		T26	176
class_index[0x3]	accum_cnt_1000	50200	1			T19	133		T13	699		T25	85
class_index[0x3]	accum_cnt_100	5456	1			T19	45		T13	41		T25	15
class_index[0x3]	accum_cnt_50	13743	1			T2	15		T19	46		T13	27
class_index[0x3]	accum_cnt_10	39884	1			T1	8		T2	7		T3	667
class_index[0x3]	accum_cnt_0	103818	1			T2	2		T3	206		T6	20