Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	69	0	69	100.00
Crosses	260	0	260	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_cause_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
alert_cause_cross_class_index	260	0	260	100.00	100	1	1	0

Summary for Variable alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	28347	1			T1	1		T2	7		T6	3
alert[0x1]	28127	1			T2	2		T18	17		T19	42
alert[0x2]	28121	1			T1	4		T2	2		T18	2
alert[0x3]	27686	1			T1	4		T2	8		T6	4
alert[0x4]	26330	1			T1	5		T2	1		T6	7
alert[0x5]	31564	1			T2	5		T6	1		T18	18
alert[0x6]	34106	1			T2	9		T6	8		T18	1
alert[0x7]	32368	1			T1	5		T2	2		T6	8
alert[0x8]	33464	1			T1	5		T2	7		T6	6
alert[0x9]	25793	1			T1	3		T2	9		T6	8
alert[0xa]	35516	1			T1	5		T2	7		T3	285
alert[0xb]	26916	1			T1	4		T2	10		T6	1
alert[0xc]	25622	1			T1	5		T2	2		T6	5
alert[0xd]	27655	1			T1	4		T2	4		T6	6
alert[0xe]	28099	1			T1	2		T2	5		T6	5
alert[0xf]	29323	1			T1	2		T2	2		T6	7
alert[0x10]	29316	1			T2	1		T6	1		T18	2
alert[0x11]	29610	1			T1	4		T2	4		T18	19
alert[0x12]	29420	1			T1	1		T2	3		T6	6
alert[0x13]	32058	1			T2	4		T3	286		T18	21
alert[0x14]	29441	1			T2	6		T6	4		T18	2
alert[0x15]	36689	1			T1	2		T2	5		T3	308
alert[0x16]	31610	1			T1	4		T2	7		T6	1
alert[0x17]	29448	1			T2	1		T6	8		T18	16
alert[0x18]	30823	1			T1	4		T2	1		T6	4
alert[0x19]	27744	1			T1	1		T2	3		T6	3
alert[0x1a]	31224	1			T2	7		T6	6		T18	2
alert[0x1b]	29882	1			T1	2		T18	2		T19	43
alert[0x1c]	26700	1			T2	2		T6	1		T18	1
alert[0x1d]	31088	1			T1	5		T2	5		T6	1
alert[0x1e]	30890	1			T1	6		T2	5		T18	1
alert[0x1f]	34120	1			T6	1		T18	1		T19	49
alert[0x20]	30472	1			T2	1		T18	1		T19	5
alert[0x21]	29006	1			T1	1		T2	1		T6	1
alert[0x22]	32009	1			T2	4		T6	1		T18	16
alert[0x23]	28325	1			T1	2		T2	1		T6	4
alert[0x24]	28427	1			T1	1		T2	8		T18	13
alert[0x25]	27283	1			T1	3		T2	2		T6	7
alert[0x26]	30540	1			T1	3		T2	2		T6	5
alert[0x27]	29379	1			T1	4		T2	2		T6	8
alert[0x28]	31702	1			T1	1		T2	6		T18	22
alert[0x29]	29565	1			T1	2		T2	3		T19	6
alert[0x2a]	32870	1			T2	6		T6	3		T18	2
alert[0x2b]	30233	1			T1	1		T2	2		T6	3
alert[0x2c]	34248	1			T1	4		T2	1		T3	1
alert[0x2d]	33041	1			T2	6		T18	17		T19	53
alert[0x2e]	29468	1			T1	3		T2	5		T6	3
alert[0x2f]	27973	1			T2	2		T6	1		T18	2
alert[0x30]	33613	1			T2	1		T18	18		T19	54
alert[0x31]	30763	1			T1	1		T2	2		T6	3
alert[0x32]	28907	1			T1	1		T2	3		T18	16
alert[0x33]	28595	1			T1	5		T2	6		T6	1
alert[0x34]	29553	1			T1	2		T2	1		T6	3
alert[0x35]	29808	1			T1	2		T2	1		T6	5
alert[0x36]	27491	1			T1	2		T18	1		T19	59
alert[0x37]	30431	1			T2	5		T6	1		T18	3
alert[0x38]	30060	1			T1	7		T2	12		T6	1
alert[0x39]	27765	1			T6	1		T18	1		T19	5
alert[0x3a]	26848	1			T1	2		T2	4		T19	10
alert[0x3b]	29390	1			T1	1		T2	2		T6	9
alert[0x3c]	27019	1			T1	1		T2	7		T6	4
alert[0x3d]	26840	1			T1	1		T2	7		T18	3
alert[0x3e]	30061	1			T1	1		T2	1		T19	55
alert[0x3f]	26908	1			T2	1		T6	5		T19	58
alert[0x40]	27253	1			T1	2		T2	7		T6	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	530430	1			T1	39		T2	75		T3	1
class_i[0x1]	469044	1			T1	24		T2	58		T6	34
class_i[0x2]	455347	1			T1	32		T2	54		T3	879
class_i[0x3]	480125	1			T1	36		T2	61		T6	33

---

Summary for Cross alert_cause_cross_class_index

Samples crossed: alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	260	0	260	100.00

Automatically Generated Cross Bins for alert_cause_cross_class_index

Bins

alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	class_i[0x0]	7721	1			T18	2		T19	10		T20	47
alert[0x0]	class_i[0x1]	5699	1			T2	1		T6	3		T22	1
alert[0x0]	class_i[0x2]	6695	1			T1	1		T18	1		T22	2
alert[0x0]	class_i[0x3]	8232	1			T2	6		T18	2		T19	1
alert[0x1]	class_i[0x0]	8153	1			T18	16		T19	8		T13	301
alert[0x1]	class_i[0x1]	6296	1			T2	2		T19	33		T20	51
alert[0x1]	class_i[0x2]	7805	1			T18	1		T19	1		T21	3
alert[0x1]	class_i[0x3]	5873	1			T49	1		T25	1		T26	176
alert[0x2]	class_i[0x0]	8475	1			T2	1		T19	10		T4	188
alert[0x2]	class_i[0x1]	7443	1			T2	1		T18	1		T20	46
alert[0x2]	class_i[0x2]	5033	1			T1	4		T19	1		T50	1
alert[0x2]	class_i[0x3]	7170	1			T18	1		T25	66		T26	105
alert[0x3]	class_i[0x0]	9270	1			T1	4		T2	5		T19	11
alert[0x3]	class_i[0x1]	5366	1			T6	3		T13	302		T25	288
alert[0x3]	class_i[0x2]	6734	1			T2	2		T22	1		T49	1
alert[0x3]	class_i[0x3]	6316	1			T2	1		T6	1		T18	1
alert[0x4]	class_i[0x0]	7667	1			T1	5		T2	1		T19	8
alert[0x4]	class_i[0x1]	6264	1			T19	36		T22	8		T30	1
alert[0x4]	class_i[0x2]	5446	1			T6	7		T18	17		T22	1
alert[0x4]	class_i[0x3]	6953	1			T21	2		T47	1		T25	4
alert[0x5]	class_i[0x0]	11678	1			T18	18		T19	9		T78	6
alert[0x5]	class_i[0x1]	6178	1			T2	5		T19	1		T25	213
alert[0x5]	class_i[0x2]	6260	1			T6	1		T19	39		T20	48
alert[0x5]	class_i[0x3]	7448	1			T4	176		T22	1		T13	337
alert[0x6]	class_i[0x0]	9011	1			T2	1		T6	8		T19	2
alert[0x6]	class_i[0x1]	10034	1			T2	1		T19	42		T22	5
alert[0x6]	class_i[0x2]	8821	1			T13	1		T30	1		T25	16
alert[0x6]	class_i[0x3]	6240	1			T2	7		T18	1		T19	1
alert[0x7]	class_i[0x0]	8892	1			T6	7		T18	22		T19	3
alert[0x7]	class_i[0x1]	7875	1			T2	1		T19	3		T20	1
alert[0x7]	class_i[0x2]	7487	1			T1	5		T6	1		T19	2
alert[0x7]	class_i[0x3]	8114	1			T2	1		T19	34		T21	2
alert[0x8]	class_i[0x0]	7287	1			T18	1		T21	4		T22	7
alert[0x8]	class_i[0x1]	8268	1			T2	6		T6	1		T19	1
alert[0x8]	class_i[0x2]	9504	1			T1	5		T2	1		T6	5
alert[0x8]	class_i[0x3]	8405	1			T7	303		T25	49		T15	30
alert[0x9]	class_i[0x0]	7161	1			T2	1		T6	8		T18	14
alert[0x9]	class_i[0x1]	5520	1			T1	3		T2	2		T22	1
alert[0x9]	class_i[0x2]	6451	1			T2	6		T21	2		T25	1
alert[0x9]	class_i[0x3]	6661	1			T18	1		T49	1		T25	2
alert[0xa]	class_i[0x0]	10772	1			T1	3		T19	10		T22	1
alert[0xa]	class_i[0x1]	9791	1			T19	32		T21	1		T22	1
alert[0xa]	class_i[0x2]	7451	1			T2	7		T3	285		T6	1
alert[0xa]	class_i[0x3]	7502	1			T1	2		T22	2		T26	2
alert[0xb]	class_i[0x0]	6300	1			T1	1		T2	1		T6	1
alert[0xb]	class_i[0x1]	7448	1			T18	17		T21	1		T22	1
alert[0xb]	class_i[0x2]	6981	1			T1	3		T2	9		T20	1
alert[0xb]	class_i[0x3]	6187	1			T25	129		T26	1		T51	3
alert[0xc]	class_i[0x0]	5776	1			T1	5		T18	1		T19	7
alert[0xc]	class_i[0x1]	6003	1			T6	5		T21	1		T30	2
alert[0xc]	class_i[0x2]	6056	1			T2	2		T18	1		T19	1
alert[0xc]	class_i[0x3]	7787	1			T18	18		T21	1		T47	1
alert[0xd]	class_i[0x0]	9241	1			T2	3		T19	11		T78	9
alert[0xd]	class_i[0x1]	6217	1			T1	4		T18	1		T25	5
alert[0xd]	class_i[0x2]	6547	1			T6	5		T25	1		T26	22
alert[0xd]	class_i[0x3]	5650	1			T2	1		T6	1		T25	274
alert[0xe]	class_i[0x0]	8048	1			T1	1		T19	10		T13	341
alert[0xe]	class_i[0x1]	5674	1			T2	1		T25	66		T26	3
alert[0xe]	class_i[0x2]	5717	1			T2	3		T20	43		T22	2
alert[0xe]	class_i[0x3]	8660	1			T1	1		T2	1		T6	5
alert[0xf]	class_i[0x0]	6116	1			T2	1		T19	10		T47	2
alert[0xf]	class_i[0x1]	8738	1			T1	2		T2	1		T18	1
alert[0xf]	class_i[0x2]	7694	1			T6	7		T19	1		T20	50
alert[0xf]	class_i[0x3]	6775	1			T18	2		T19	1		T13	310
alert[0x10]	class_i[0x0]	8017	1			T2	1		T18	1		T19	10
alert[0x10]	class_i[0x1]	7822	1			T19	45		T20	1		T4	188
alert[0x10]	class_i[0x2]	7849	1			T6	1		T20	51		T22	1
alert[0x10]	class_i[0x3]	5628	1			T18	1		T22	1		T49	1
alert[0x11]	class_i[0x0]	9050	1			T1	4		T19	6		T22	8
alert[0x11]	class_i[0x1]	7024	1			T2	4		T19	34		T20	44
alert[0x11]	class_i[0x2]	6700	1			T18	1		T19	1		T30	1
alert[0x11]	class_i[0x3]	6836	1			T18	18		T19	4		T13	312
alert[0x12]	class_i[0x0]	8139	1			T2	1		T19	50		T20	1
alert[0x12]	class_i[0x1]	7294	1			T2	1		T6	6		T18	19
alert[0x12]	class_i[0x2]	7375	1			T1	1		T2	1		T19	41
alert[0x12]	class_i[0x3]	6612	1			T49	1		T25	5		T26	17
alert[0x13]	class_i[0x0]	10178	1			T18	1		T19	2		T22	2
alert[0x13]	class_i[0x1]	5121	1			T20	1		T4	194		T22	1
alert[0x13]	class_i[0x2]	9615	1			T3	286		T18	1		T19	1
alert[0x13]	class_i[0x3]	7144	1			T2	4		T18	19		T22	2
alert[0x14]	class_i[0x0]	7914	1			T2	6		T18	1		T19	7
alert[0x14]	class_i[0x1]	5285	1			T18	1		T7	1		T13	304
alert[0x14]	class_i[0x2]	7714	1			T6	4		T19	1		T22	4
alert[0x14]	class_i[0x3]	8528	1			T13	1		T25	126		T50	1
alert[0x15]	class_i[0x0]	10349	1			T6	8		T19	1		T21	2
alert[0x15]	class_i[0x1]	9895	1			T1	1		T2	1		T19	2
alert[0x15]	class_i[0x2]	8546	1			T1	1		T3	308		T22	1
alert[0x15]	class_i[0x3]	7899	1			T2	4		T18	14		T19	42
alert[0x16]	class_i[0x0]	6602	1			T2	1		T6	1		T18	17
alert[0x16]	class_i[0x1]	7368	1			T1	3		T25	1		T26	2
alert[0x16]	class_i[0x2]	9694	1			T2	6		T18	1		T19	1
alert[0x16]	class_i[0x3]	7946	1			T1	1		T19	1		T22	1
alert[0x17]	class_i[0x0]	7234	1			T6	8		T19	8		T22	1
alert[0x17]	class_i[0x1]	7786	1			T18	16		T22	3		T13	303
alert[0x17]	class_i[0x2]	5122	1			T2	1		T19	1		T22	2
alert[0x17]	class_i[0x3]	9306	1			T20	1		T49	1		T25	22
alert[0x18]	class_i[0x0]	8232	1			T1	1		T19	6		T4	186
alert[0x18]	class_i[0x1]	7634	1			T22	1		T25	57		T26	2
alert[0x18]	class_i[0x2]	7426	1			T1	3		T2	1		T6	4
alert[0x18]	class_i[0x3]	7531	1			T19	1		T49	3		T30	10
alert[0x19]	class_i[0x0]	8240	1			T19	4		T22	1		T78	15
alert[0x19]	class_i[0x1]	6952	1			T6	1		T18	19		T22	6
alert[0x19]	class_i[0x2]	5741	1			T2	1		T6	1		T20	1
alert[0x19]	class_i[0x3]	6811	1			T1	1		T2	2		T6	1
alert[0x1a]	class_i[0x0]	7542	1			T19	13		T20	1		T13	339
alert[0x1a]	class_i[0x1]	6063	1			T2	6		T20	1		T4	177
alert[0x1a]	class_i[0x2]	9301	1			T2	1		T18	1		T19	1
alert[0x1a]	class_i[0x3]	8318	1			T6	6		T18	1		T19	35
alert[0x1b]	class_i[0x0]	10040	1			T1	1		T18	1		T19	4
alert[0x1b]	class_i[0x1]	6657	1			T19	39		T30	6		T25	29
alert[0x1b]	class_i[0x2]	6178	1			T1	1		T18	1		T22	1
alert[0x1b]	class_i[0x3]	7007	1			T20	1		T25	1		T50	35
alert[0x1c]	class_i[0x0]	8423	1			T19	10		T20	44		T47	2
alert[0x1c]	class_i[0x1]	4231	1			T2	2		T20	1		T25	37
alert[0x1c]	class_i[0x2]	7202	1			T20	2		T22	5		T25	67
alert[0x1c]	class_i[0x3]	6844	1			T6	1		T18	1		T30	7
alert[0x1d]	class_i[0x0]	8965	1			T1	4		T2	5		T19	4
alert[0x1d]	class_i[0x1]	5524	1			T19	39		T22	2		T25	47
alert[0x1d]	class_i[0x2]	7089	1			T19	1		T20	1		T22	1
alert[0x1d]	class_i[0x3]	9510	1			T1	1		T6	1		T18	1
alert[0x1e]	class_i[0x0]	8372	1			T1	6		T2	3		T19	11
alert[0x1e]	class_i[0x1]	5519	1			T49	1		T30	10		T25	2
alert[0x1e]	class_i[0x2]	7509	1			T22	1		T25	6		T14	1
alert[0x1e]	class_i[0x3]	9490	1			T2	2		T18	1		T19	1
alert[0x1f]	class_i[0x0]	8090	1			T6	1		T19	9		T7	2
alert[0x1f]	class_i[0x1]	8708	1			T18	1		T19	37		T22	2
alert[0x1f]	class_i[0x2]	8793	1			T19	2		T21	2		T30	10
alert[0x1f]	class_i[0x3]	8529	1			T19	1		T20	1		T4	187
alert[0x20]	class_i[0x0]	6297	1			T2	1		T19	5		T21	1
alert[0x20]	class_i[0x1]	7149	1			T18	1		T22	2		T25	41
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alert[0x20]	class_i[0x3]	7794	1			T22	1		T13	304		T25	5
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alert[0x22]	class_i[0x2]	7597	1			T2	1		T30	1		T25	25
alert[0x22]	class_i[0x3]	9400	1			T2	3		T6	1		T18	16
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alert[0x23]	class_i[0x3]	9382	1			T19	43		T13	309		T30	1
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alert[0x24]	class_i[0x2]	6826	1			T18	2		T20	1		T4	164
alert[0x24]	class_i[0x3]	7292	1			T20	1		T25	2		T26	196
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