Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	11861	1			T5	1		T35	13		T9	1
alert[0x1]	3857	1			T25	144		T26	120		T15	34
alert[0x2]	3154	1			T47	5		T25	5		T26	41
alert[0x3]	9052	1			T26	8		T8	1		T31	5
alert[0x4]	7751	1			T26	13		T35	4035		T79	20
alert[0x5]	16396	1			T19	2		T25	6		T8	1
alert[0x6]	10337	1			T25	5		T15	1		T17	30
alert[0x7]	5130	1			T19	60		T23	40		T57	211
alert[0x8]	2685	1			T25	11		T26	42		T8	2
alert[0x9]	7325	1			T26	17		T35	218		T79	11
alert[0xa]	6116	1			T3	1		T25	262		T26	3
alert[0xb]	2766	1			T26	508		T15	11		T35	27
alert[0xc]	3405	1			T25	32		T26	22		T8	1
alert[0xd]	10515	1			T25	67		T33	377		T117	107
alert[0xe]	4417	1			T15	178		T79	73		T224	1
alert[0xf]	2592	1			T4	2		T25	71		T15	172
alert[0x10]	3411	1			T25	134		T8	1		T31	26
alert[0x11]	2559	1			T19	12		T75	2		T79	223
alert[0x12]	4275	1			T4	21		T26	143		T8	1
alert[0x13]	5559	1			T3	1		T5	1		T25	43
alert[0x14]	4249	1			T25	24		T15	341		T17	27
alert[0x15]	7636	1			T3	1		T19	491		T25	128
alert[0x16]	3524	1			T4	4		T8	1		T17	1
alert[0x17]	5040	1			T35	223		T79	31		T117	147
alert[0x18]	9766	1			T4	1		T8	1		T79	2321
alert[0x19]	6705	1			T8	1		T53	1		T283	1
alert[0x1a]	6897	1			T15	3		T79	13		T23	1
alert[0x1b]	4532	1			T35	1598		T23	1		T34	43
alert[0x1c]	5313	1			T25	2		T8	1		T15	18
alert[0x1d]	2628	1			T25	22		T15	524		T54	2
alert[0x1e]	9227	1			T26	56		T15	117		T17	719
alert[0x1f]	11707	1			T25	37		T8	1		T15	5
alert[0x20]	6099	1			T25	1		T54	8		T117	324
alert[0x21]	4874	1			T19	771		T5	1		T26	68
alert[0x22]	3115	1			T8	1		T15	3		T224	1
alert[0x23]	1719	1			T5	1		T117	15		T23	8
alert[0x24]	5136	1			T25	21		T17	355		T35	46
alert[0x25]	5556	1			T17	8		T35	1947		T9	1
alert[0x26]	5442	1			T5	1		T25	21		T17	112
alert[0x27]	17319	1			T19	81		T25	31		T17	59
alert[0x28]	4722	1			T25	35		T26	440		T15	4
alert[0x29]	5389	1			T35	25		T79	44		T53	5
alert[0x2a]	5553	1			T19	7		T5	1		T15	1
alert[0x2b]	5754	1			T4	8		T25	620		T17	20
alert[0x2c]	3727	1			T47	5		T8	1		T35	201
alert[0x2d]	9147	1			T17	147		T224	1		T54	13
alert[0x2e]	1398	1			T15	1		T224	1		T33	11
alert[0x2f]	6001	1			T19	38		T47	8		T25	96
alert[0x30]	2817	1			T19	2		T8	1		T15	4
alert[0x31]	5828	1			T19	2		T25	38		T15	19
alert[0x32]	6529	1			T25	64		T15	2		T35	1387
alert[0x33]	3221	1			T5	1		T25	25		T9	1
alert[0x34]	3202	1			T25	330		T15	8		T31	2
alert[0x35]	3684	1			T54	9		T117	230		T57	63
alert[0x36]	3109	1			T8	1		T15	5		T79	159
alert[0x37]	4344	1			T25	55		T26	223		T8	1
alert[0x38]	4048	1			T8	1		T15	83		T35	83
alert[0x39]	1531	1			T25	49		T26	30		T15	30
alert[0x3a]	3728	1			T15	4		T35	26		T79	20
alert[0x3b]	5915	1			T75	1		T33	325		T23	5
alert[0x3c]	7035	1			T26	2		T17	71		T54	1
alert[0x3d]	8502	1			T31	1		T285	1		T286	5519
alert[0x3e]	2912	1			T8	1		T15	89		T17	23
alert[0x3f]	7856	1			T25	560		T15	53		T79	1154
alert[0x40]	9968	1			T5	1		T26	32		T15	25

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	111244	1			T19	1466		T4	27		T5	7
class_i[0x1]	106622	1			T4	9		T25	26		T8	1
class_i[0x2]	60987	1			T5	1		T47	1		T25	71
class_i[0x3]	96714	1			T3	3		T47	17		T8	17

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

374893

1

T19

1466

T4

36

T47

18

alert_ping_fail

674

1

T3

3

T5

8

T8

19

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	11847	1			T35	13		T79	19		T33	362
alert_integrity_fail	alert[0x1]	3835	1			T25	144		T26	120		T15	34
alert_integrity_fail	alert[0x2]	3144	1			T47	5		T25	5		T26	41
alert_integrity_fail	alert[0x3]	9046	1			T26	8		T31	5		T35	75
alert_integrity_fail	alert[0x4]	7745	1			T26	13		T35	4035		T79	20
alert_integrity_fail	alert[0x5]	16385	1			T19	2		T25	6		T15	73
alert_integrity_fail	alert[0x6]	10326	1			T25	5		T15	1		T17	30
alert_integrity_fail	alert[0x7]	5122	1			T19	60		T23	40		T57	211
alert_integrity_fail	alert[0x8]	2661	1			T25	11		T26	42		T15	153
alert_integrity_fail	alert[0x9]	7320	1			T26	17		T35	218		T79	11
alert_integrity_fail	alert[0xa]	6102	1			T25	262		T26	3		T15	22
alert_integrity_fail	alert[0xb]	2760	1			T26	508		T15	11		T35	27
alert_integrity_fail	alert[0xc]	3401	1			T25	32		T26	22		T15	3
alert_integrity_fail	alert[0xd]	10507	1			T25	67		T33	377		T117	107
alert_integrity_fail	alert[0xe]	4404	1			T15	178		T79	73		T90	160
alert_integrity_fail	alert[0xf]	2582	1			T4	2		T25	71		T15	172
alert_integrity_fail	alert[0x10]	3403	1			T25	134		T31	26		T17	869
alert_integrity_fail	alert[0x11]	2546	1			T19	12		T75	2		T79	223
alert_integrity_fail	alert[0x12]	4271	1			T4	21		T26	143		T15	6
alert_integrity_fail	alert[0x13]	5543	1			T25	43		T26	8		T75	3
alert_integrity_fail	alert[0x14]	4236	1			T25	24		T15	341		T17	27
alert_integrity_fail	alert[0x15]	7618	1			T19	491		T25	128		T26	923
alert_integrity_fail	alert[0x16]	3516	1			T4	4		T17	1		T117	15
alert_integrity_fail	alert[0x17]	5026	1			T35	223		T79	31		T117	147
alert_integrity_fail	alert[0x18]	9760	1			T4	1		T79	2321		T53	23
alert_integrity_fail	alert[0x19]	6696	1			T53	1		T57	513		T84	4
alert_integrity_fail	alert[0x1a]	6885	1			T15	3		T79	13		T23	1
alert_integrity_fail	alert[0x1b]	4524	1			T35	1598		T23	1		T34	43
alert_integrity_fail	alert[0x1c]	5306	1			T25	2		T15	18		T54	3
alert_integrity_fail	alert[0x1d]	2617	1			T25	22		T15	524		T54	2
alert_integrity_fail	alert[0x1e]	9213	1			T26	56		T15	117		T17	719
alert_integrity_fail	alert[0x1f]	11691	1			T25	37		T15	5		T79	19
alert_integrity_fail	alert[0x20]	6090	1			T25	1		T54	8		T117	324
alert_integrity_fail	alert[0x21]	4861	1			T19	771		T26	68		T15	9
alert_integrity_fail	alert[0x22]	3104	1			T15	3		T81	1		T33	150
alert_integrity_fail	alert[0x23]	1710	1			T117	15		T23	8		T57	162
alert_integrity_fail	alert[0x24]	5128	1			T25	21		T17	355		T35	46
alert_integrity_fail	alert[0x25]	5547	1			T17	8		T35	1947		T53	3
alert_integrity_fail	alert[0x26]	5433	1			T25	21		T17	112		T53	7
alert_integrity_fail	alert[0x27]	17308	1			T19	81		T25	31		T17	59
alert_integrity_fail	alert[0x28]	4704	1			T25	35		T26	440		T15	4
alert_integrity_fail	alert[0x29]	5382	1			T35	25		T79	44		T53	5
alert_integrity_fail	alert[0x2a]	5542	1			T19	7		T15	1		T35	31
alert_integrity_fail	alert[0x2b]	5744	1			T4	8		T25	620		T17	20
alert_integrity_fail	alert[0x2c]	3712	1			T47	5		T35	201		T117	28
alert_integrity_fail	alert[0x2d]	9131	1			T17	147		T54	13		T84	1
alert_integrity_fail	alert[0x2e]	1390	1			T15	1		T33	11		T34	127
alert_integrity_fail	alert[0x2f]	5992	1			T19	38		T47	8		T25	96
alert_integrity_fail	alert[0x30]	2811	1			T19	2		T15	4		T79	761
alert_integrity_fail	alert[0x31]	5821	1			T19	2		T25	38		T15	19
alert_integrity_fail	alert[0x32]	6518	1			T25	64		T15	2		T35	1387
alert_integrity_fail	alert[0x33]	3214	1			T25	25		T79	399		T117	3
alert_integrity_fail	alert[0x34]	3197	1			T25	330		T15	8		T31	2
alert_integrity_fail	alert[0x35]	3677	1			T54	9		T117	230		T57	63
alert_integrity_fail	alert[0x36]	3099	1			T15	5		T79	159		T54	9
alert_integrity_fail	alert[0x37]	4334	1			T25	55		T26	223		T15	10
alert_integrity_fail	alert[0x38]	4041	1			T15	83		T35	83		T79	519
alert_integrity_fail	alert[0x39]	1523	1			T25	49		T26	30		T15	30
alert_integrity_fail	alert[0x3a]	3717	1			T15	4		T35	26		T79	20
alert_integrity_fail	alert[0x3b]	5901	1			T75	1		T33	325		T23	5
alert_integrity_fail	alert[0x3c]	7022	1			T26	2		T17	71		T54	1
alert_integrity_fail	alert[0x3d]	8492	1			T31	1		T286	5519		T88	19
alert_integrity_fail	alert[0x3e]	2899	1			T15	89		T17	23		T35	89
alert_integrity_fail	alert[0x3f]	7849	1			T25	560		T15	53		T79	1154
alert_integrity_fail	alert[0x40]	9962	1			T26	32		T15	25		T35	1227
alert_ping_fail	alert[0x0]	14	1			T5	1		T9	1		T287	1
alert_ping_fail	alert[0x1]	22	1			T287	1		T288	2		T289	3
alert_ping_fail	alert[0x2]	10	1			T224	1		T289	1		T290	1
alert_ping_fail	alert[0x3]	6	1			T8	1		T291	1		T292	1
alert_ping_fail	alert[0x4]	6	1			T289	1		T293	1		T44	1
alert_ping_fail	alert[0x5]	11	1			T8	1		T288	2		T294	1
alert_ping_fail	alert[0x6]	11	1			T224	1		T287	1		T295	1
alert_ping_fail	alert[0x7]	8	1			T287	1		T288	1		T289	1
alert_ping_fail	alert[0x8]	24	1			T8	2		T287	1		T248	1
alert_ping_fail	alert[0x9]	5	1			T224	1		T287	1		T296	1
alert_ping_fail	alert[0xa]	14	1			T3	1		T248	1		T239	1
alert_ping_fail	alert[0xb]	6	1			T287	1		T297	1		T292	2
alert_ping_fail	alert[0xc]	4	1			T8	1		T298	1		T299	1
alert_ping_fail	alert[0xd]	8	1			T285	1		T297	1		T300	1
alert_ping_fail	alert[0xe]	13	1			T224	1		T297	2		T44	1
alert_ping_fail	alert[0xf]	10	1			T245	1		T301	1		T288	2
alert_ping_fail	alert[0x10]	8	1			T8	1		T302	1		T303	1
alert_ping_fail	alert[0x11]	13	1			T290	1		T304	1		T298	1
alert_ping_fail	alert[0x12]	4	1			T8	1		T224	1		T305	1
alert_ping_fail	alert[0x13]	16	1			T3	1		T5	1		T287	1
alert_ping_fail	alert[0x14]	13	1			T96	1		T306	1		T307	1
alert_ping_fail	alert[0x15]	18	1			T3	1		T254	1		T96	1
alert_ping_fail	alert[0x16]	8	1			T8	1		T295	1		T239	1
alert_ping_fail	alert[0x17]	14	1			T245	1		T308	1		T44	2
alert_ping_fail	alert[0x18]	6	1			T8	1		T224	1		T289	1
alert_ping_fail	alert[0x19]	9	1			T8	1		T283	1		T301	1
alert_ping_fail	alert[0x1a]	12	1			T297	1		T294	1		T300	1
alert_ping_fail	alert[0x1b]	8	1			T295	1		T294	1		T309	2
alert_ping_fail	alert[0x1c]	7	1			T8	1		T288	1		T308	1
alert_ping_fail	alert[0x1d]	11	1			T254	1		T282	1		T302	1
alert_ping_fail	alert[0x1e]	14	1			T245	1		T40	1		T303	1
alert_ping_fail	alert[0x1f]	16	1			T8	1		T224	1		T295	2
alert_ping_fail	alert[0x20]	9	1			T287	1		T295	1		T288	1
alert_ping_fail	alert[0x21]	13	1			T5	1		T224	1		T287	1
alert_ping_fail	alert[0x22]	11	1			T8	1		T224	1		T310	1
alert_ping_fail	alert[0x23]	9	1			T5	1		T245	2		T288	1
alert_ping_fail	alert[0x24]	8	1			T285	1		T308	1		T291	1
alert_ping_fail	alert[0x25]	9	1			T9	1		T245	1		T289	1
alert_ping_fail	alert[0x26]	9	1			T5	1		T289	1		T290	1
alert_ping_fail	alert[0x27]	11	1			T245	1		T301	1		T293	3
alert_ping_fail	alert[0x28]	18	1			T9	1		T224	1		T285	1
alert_ping_fail	alert[0x29]	7	1			T245	1		T289	1		T294	1
alert_ping_fail	alert[0x2a]	11	1			T5	1		T245	1		T306	1
alert_ping_fail	alert[0x2b]	10	1			T290	1		T294	1		T306	1
alert_ping_fail	alert[0x2c]	15	1			T8	1		T96	1		T288	1
alert_ping_fail	alert[0x2d]	16	1			T224	1		T287	2		T244	1
alert_ping_fail	alert[0x2e]	8	1			T224	1		T301	1		T290	1
alert_ping_fail	alert[0x2f]	9	1			T9	1		T297	1		T293	1
alert_ping_fail	alert[0x30]	6	1			T8	1		T311	1		T298	1
alert_ping_fail	alert[0x31]	7	1			T285	1		T289	1		T290	1
alert_ping_fail	alert[0x32]	11	1			T224	1		T301	1		T297	1
alert_ping_fail	alert[0x33]	7	1			T5	1		T9	1		T245	1
alert_ping_fail	alert[0x34]	5	1			T224	1		T300	1		T311	2
alert_ping_fail	alert[0x35]	7	1			T300	1		T309	1		T291	1
alert_ping_fail	alert[0x36]	10	1			T8	1		T245	1		T301	1
alert_ping_fail	alert[0x37]	10	1			T8	1		T224	1		T301	1
alert_ping_fail	alert[0x38]	7	1			T8	1		T9	1		T288	1
alert_ping_fail	alert[0x39]	8	1			T245	1		T288	1		T294	1
alert_ping_fail	alert[0x3a]	11	1			T287	2		T309	1		T311	1
alert_ping_fail	alert[0x3b]	14	1			T287	1		T288	1		T302	1
alert_ping_fail	alert[0x3c]	13	1			T287	1		T285	1		T309	2
alert_ping_fail	alert[0x3d]	10	1			T285	1		T293	1		T306	1
alert_ping_fail	alert[0x3e]	13	1			T8	1		T224	1		T245	1
alert_ping_fail	alert[0x3f]	7	1			T224	1		T289	1		T303	1
alert_ping_fail	alert[0x40]	6	1			T5	1		T306	1		T312	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	111106	1			T19	1466		T4	27		T25	2842
alert_integrity_fail	class_i[0x1]	106386	1			T4	9		T25	26		T15	644
alert_integrity_fail	class_i[0x2]	60832	1			T47	1		T25	71		T26	2672
alert_integrity_fail	class_i[0x3]	96569	1			T47	17		T31	37		T75	3
alert_ping_fail	class_i[0x0]	138	1			T5	7		T9	1		T282	1
alert_ping_fail	class_i[0x1]	236	1			T8	1		T224	17		T287	1
alert_ping_fail	class_i[0x2]	155	1			T5	1		T8	1		T9	5
alert_ping_fail	class_i[0x3]	145	1			T3	3		T8	17		T248	2