Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.38 99.52


Total test records in report: 824
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T774 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1432238710 Jun 25 07:12:03 PM PDT 24 Jun 25 07:12:23 PM PDT 24 10038441 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3213309414 Jun 25 07:11:24 PM PDT 24 Jun 25 07:24:40 PM PDT 24 4533441152 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1401085577 Jun 25 07:11:01 PM PDT 24 Jun 25 07:11:17 PM PDT 24 27669334 ps
T776 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1857425714 Jun 25 07:11:57 PM PDT 24 Jun 25 07:12:20 PM PDT 24 233627156 ps
T777 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.972525489 Jun 25 07:12:07 PM PDT 24 Jun 25 07:12:30 PM PDT 24 24505930 ps
T145 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2611012585 Jun 25 07:11:59 PM PDT 24 Jun 25 07:14:15 PM PDT 24 3461929158 ps
T155 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.963287147 Jun 25 07:11:55 PM PDT 24 Jun 25 07:31:06 PM PDT 24 16104770986 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1479129748 Jun 25 07:10:39 PM PDT 24 Jun 25 07:10:48 PM PDT 24 22303321 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3402568605 Jun 25 07:12:06 PM PDT 24 Jun 25 07:12:46 PM PDT 24 262681819 ps
T137 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3118233592 Jun 25 07:11:25 PM PDT 24 Jun 25 07:16:40 PM PDT 24 13951512237 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4048647422 Jun 25 07:10:52 PM PDT 24 Jun 25 07:11:30 PM PDT 24 659842228 ps
T781 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3166828064 Jun 25 07:10:39 PM PDT 24 Jun 25 07:10:45 PM PDT 24 9916125 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1702196410 Jun 25 07:11:54 PM PDT 24 Jun 25 07:12:12 PM PDT 24 134693391 ps
T783 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1269423414 Jun 25 07:12:04 PM PDT 24 Jun 25 07:12:37 PM PDT 24 159912305 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1724932862 Jun 25 07:11:13 PM PDT 24 Jun 25 07:11:36 PM PDT 24 75061313 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1686992715 Jun 25 07:11:54 PM PDT 24 Jun 25 07:29:02 PM PDT 24 172942098451 ps
T785 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2597594362 Jun 25 07:12:02 PM PDT 24 Jun 25 07:12:33 PM PDT 24 352229296 ps
T786 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3300108706 Jun 25 07:11:27 PM PDT 24 Jun 25 07:11:36 PM PDT 24 10586871 ps
T787 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3314153911 Jun 25 07:11:27 PM PDT 24 Jun 25 07:11:43 PM PDT 24 119109290 ps
T788 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.73691885 Jun 25 07:12:14 PM PDT 24 Jun 25 07:12:46 PM PDT 24 342465895 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2113167774 Jun 25 07:12:04 PM PDT 24 Jun 25 07:12:28 PM PDT 24 47904372 ps
T151 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1816436280 Jun 25 07:11:58 PM PDT 24 Jun 25 07:14:07 PM PDT 24 1071113705 ps
T138 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1630626499 Jun 25 07:10:42 PM PDT 24 Jun 25 07:16:11 PM PDT 24 9777881952 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3043408740 Jun 25 07:11:57 PM PDT 24 Jun 25 07:13:02 PM PDT 24 1046487173 ps
T791 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.927598904 Jun 25 07:12:09 PM PDT 24 Jun 25 07:12:32 PM PDT 24 7560071 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2072384028 Jun 25 07:10:40 PM PDT 24 Jun 25 07:10:53 PM PDT 24 114729302 ps
T792 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2119459632 Jun 25 07:12:06 PM PDT 24 Jun 25 07:12:34 PM PDT 24 83362087 ps
T793 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3088343144 Jun 25 07:11:53 PM PDT 24 Jun 25 07:12:16 PM PDT 24 257740248 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2043823412 Jun 25 07:11:59 PM PDT 24 Jun 25 07:12:23 PM PDT 24 216476494 ps
T795 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3688712969 Jun 25 07:10:42 PM PDT 24 Jun 25 07:10:57 PM PDT 24 137297885 ps
T796 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3964778649 Jun 25 07:12:12 PM PDT 24 Jun 25 07:12:42 PM PDT 24 479490373 ps
T168 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4175096266 Jun 25 07:11:14 PM PDT 24 Jun 25 07:11:31 PM PDT 24 231521157 ps
T341 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3883525358 Jun 25 07:10:40 PM PDT 24 Jun 25 07:15:57 PM PDT 24 3104886877 ps
T146 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.609474645 Jun 25 07:11:52 PM PDT 24 Jun 25 07:23:16 PM PDT 24 4465491474 ps
T797 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1087134824 Jun 25 07:12:14 PM PDT 24 Jun 25 07:12:40 PM PDT 24 9628469 ps
T173 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1462866505 Jun 25 07:11:55 PM PDT 24 Jun 25 07:12:52 PM PDT 24 410757972 ps
T798 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2539904086 Jun 25 07:12:15 PM PDT 24 Jun 25 07:12:41 PM PDT 24 7512918 ps
T182 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3455430754 Jun 25 07:12:03 PM PDT 24 Jun 25 07:12:56 PM PDT 24 589925927 ps
T799 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3710952430 Jun 25 07:11:54 PM PDT 24 Jun 25 07:12:09 PM PDT 24 35115669 ps
T800 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1295833734 Jun 25 07:12:07 PM PDT 24 Jun 25 07:12:28 PM PDT 24 8477234 ps
T801 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.406706363 Jun 25 07:11:27 PM PDT 24 Jun 25 07:11:46 PM PDT 24 1021427071 ps
T802 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.219941426 Jun 25 07:11:26 PM PDT 24 Jun 25 07:11:47 PM PDT 24 343448548 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1176691112 Jun 25 07:12:07 PM PDT 24 Jun 25 07:12:31 PM PDT 24 32355512 ps
T804 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.42148090 Jun 25 07:10:51 PM PDT 24 Jun 25 07:19:41 PM PDT 24 8905992649 ps
T805 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3316605046 Jun 25 07:12:12 PM PDT 24 Jun 25 07:12:36 PM PDT 24 24059871 ps
T174 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2989218107 Jun 25 07:12:06 PM PDT 24 Jun 25 07:13:16 PM PDT 24 622735045 ps
T806 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2385962237 Jun 25 07:12:07 PM PDT 24 Jun 25 07:12:56 PM PDT 24 1875051691 ps
T158 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.879543226 Jun 25 07:11:24 PM PDT 24 Jun 25 07:14:16 PM PDT 24 8528623101 ps
T171 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4104997324 Jun 25 07:10:40 PM PDT 24 Jun 25 07:10:49 PM PDT 24 48702931 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1421995781 Jun 25 07:11:27 PM PDT 24 Jun 25 07:12:01 PM PDT 24 158180570 ps
T808 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.987056609 Jun 25 07:11:59 PM PDT 24 Jun 25 07:12:15 PM PDT 24 14789762 ps
T809 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3169287210 Jun 25 07:12:11 PM PDT 24 Jun 25 07:12:34 PM PDT 24 15644008 ps
T810 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.50157406 Jun 25 07:11:10 PM PDT 24 Jun 25 07:11:29 PM PDT 24 108972874 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3835752961 Jun 25 07:10:41 PM PDT 24 Jun 25 07:10:52 PM PDT 24 26786203 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1172130448 Jun 25 07:11:55 PM PDT 24 Jun 25 07:12:19 PM PDT 24 359848969 ps
T132 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2742580733 Jun 25 07:11:26 PM PDT 24 Jun 25 07:21:16 PM PDT 24 21740204682 ps
T813 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.685494999 Jun 25 07:12:10 PM PDT 24 Jun 25 07:12:33 PM PDT 24 55468547 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3488070111 Jun 25 07:11:25 PM PDT 24 Jun 25 07:11:42 PM PDT 24 66532002 ps
T815 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1856196627 Jun 25 07:12:17 PM PDT 24 Jun 25 07:12:44 PM PDT 24 13727459 ps
T816 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2497949798 Jun 25 07:12:07 PM PDT 24 Jun 25 07:12:34 PM PDT 24 69129659 ps
T817 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.551491514 Jun 25 07:12:13 PM PDT 24 Jun 25 07:12:37 PM PDT 24 24313370 ps
T818 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1344502111 Jun 25 07:11:24 PM PDT 24 Jun 25 07:11:43 PM PDT 24 481992203 ps
T157 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1105901720 Jun 25 07:11:12 PM PDT 24 Jun 25 07:29:08 PM PDT 24 24635283007 ps
T819 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.115017272 Jun 25 07:12:04 PM PDT 24 Jun 25 07:12:52 PM PDT 24 174860991 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1018878416 Jun 25 07:11:00 PM PDT 24 Jun 25 07:11:21 PM PDT 24 271648057 ps
T148 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.445986338 Jun 25 07:11:55 PM PDT 24 Jun 25 07:17:34 PM PDT 24 4033558261 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.231544593 Jun 25 07:10:50 PM PDT 24 Jun 25 07:13:46 PM PDT 24 8688477129 ps
T166 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1658387634 Jun 25 07:11:54 PM PDT 24 Jun 25 07:12:37 PM PDT 24 1801143501 ps
T156 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1349051759 Jun 25 07:11:56 PM PDT 24 Jun 25 07:16:06 PM PDT 24 1745367024 ps
T822 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1196936146 Jun 25 07:12:14 PM PDT 24 Jun 25 07:12:38 PM PDT 24 7619534 ps
T823 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4150161648 Jun 25 07:12:06 PM PDT 24 Jun 25 07:12:28 PM PDT 24 23229643 ps
T147 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3747358638 Jun 25 07:11:53 PM PDT 24 Jun 25 07:18:26 PM PDT 24 22789949018 ps
T152 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1436582307 Jun 25 07:12:03 PM PDT 24 Jun 25 07:23:25 PM PDT 24 9083042614 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2834184121 Jun 25 07:10:59 PM PDT 24 Jun 25 07:11:23 PM PDT 24 1776154198 ps

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2903731696
Short name T19
Test name
Test status
Simulation time 142772288804 ps
CPU time 1681.51 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:41:28 PM PDT 24
Peak memory 282212 kb
Host smart-b3d88f95-b70f-4377-85b2-48cecc386994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903731696 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2903731696
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1676203696
Short name T25
Test name
Test status
Simulation time 365363474364 ps
CPU time 6901.81 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 09:08:27 PM PDT 24
Peak memory 337172 kb
Host smart-3960c32c-1a13-4194-a9bf-43a5bb47fc09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676203696 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1676203696
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4145219239
Short name T10
Test name
Test status
Simulation time 467679573 ps
CPU time 27.44 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:13:38 PM PDT 24
Peak memory 271280 kb
Host smart-3e8b7843-b874-4db1-9869-8982ab3b211f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4145219239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4145219239
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.941389692
Short name T15
Test name
Test status
Simulation time 148082035971 ps
CPU time 4659.15 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 08:32:35 PM PDT 24
Peak memory 290520 kb
Host smart-234c2f72-3792-40f7-9d4f-31c05087da86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941389692 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.941389692
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.265759989
Short name T161
Test name
Test status
Simulation time 5981218201 ps
CPU time 74.8 seconds
Started Jun 25 07:12:00 PM PDT 24
Finished Jun 25 07:13:29 PM PDT 24
Peak memory 248828 kb
Host smart-891092aa-92fc-4734-a769-a6262f6dfdf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=265759989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.265759989
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2948794320
Short name T34
Test name
Test status
Simulation time 167780099976 ps
CPU time 2190.18 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:53:53 PM PDT 24
Peak memory 284704 kb
Host smart-e4156b1d-87e7-4088-9452-e039f4469eb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948794320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2948794320
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.878434923
Short name T55
Test name
Test status
Simulation time 105348154805 ps
CPU time 3721.19 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 08:15:56 PM PDT 24
Peak memory 298736 kb
Host smart-49dbdedd-7cb8-48c0-88b4-4cdcdf7dff17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878434923 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.878434923
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3564791771
Short name T96
Test name
Test status
Simulation time 208219527595 ps
CPU time 3450.41 seconds
Started Jun 25 07:13:18 PM PDT 24
Finished Jun 25 08:10:58 PM PDT 24
Peak memory 289768 kb
Host smart-9028314a-74b6-4b9c-9d77-92cc8249b7f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564791771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3564791771
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1413784654
Short name T129
Test name
Test status
Simulation time 22751295824 ps
CPU time 318.74 seconds
Started Jun 25 07:10:41 PM PDT 24
Finished Jun 25 07:16:10 PM PDT 24
Peak memory 265636 kb
Host smart-9022b381-9936-4d2e-ab26-346fd097aed8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1413784654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1413784654
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.787147966
Short name T93
Test name
Test status
Simulation time 32538268078 ps
CPU time 1714.91 seconds
Started Jun 25 07:14:34 PM PDT 24
Finished Jun 25 07:43:14 PM PDT 24
Peak memory 290304 kb
Host smart-8fd289a4-5498-4eab-90f7-f10f2aa84786
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787147966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.787147966
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2076288943
Short name T142
Test name
Test status
Simulation time 60729114691 ps
CPU time 1262.35 seconds
Started Jun 25 07:10:50 PM PDT 24
Finished Jun 25 07:32:09 PM PDT 24
Peak memory 272388 kb
Host smart-d66303aa-4c4e-4d40-bb53-420737a46c7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076288943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2076288943
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3203806844
Short name T119
Test name
Test status
Simulation time 148234319595 ps
CPU time 2221.97 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:54:13 PM PDT 24
Peak memory 274056 kb
Host smart-4a92c7a0-d95e-4f52-87d6-2eff4bd03593
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203806844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3203806844
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2836709663
Short name T123
Test name
Test status
Simulation time 6211594041 ps
CPU time 437.02 seconds
Started Jun 25 07:11:00 PM PDT 24
Finished Jun 25 07:18:33 PM PDT 24
Peak memory 269544 kb
Host smart-a406a323-21fb-4523-bf31-40321c506512
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836709663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2836709663
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2713687056
Short name T35
Test name
Test status
Simulation time 15476973941 ps
CPU time 1655.95 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 07:41:44 PM PDT 24
Peak memory 288512 kb
Host smart-85df320b-0916-4b58-8839-d8cedcf13066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713687056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2713687056
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3051205332
Short name T281
Test name
Test status
Simulation time 189970002969 ps
CPU time 3262.04 seconds
Started Jun 25 07:13:25 PM PDT 24
Finished Jun 25 08:07:57 PM PDT 24
Peak memory 289812 kb
Host smart-4ac0aa7a-03fe-4625-ade5-12878a940ec5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051205332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3051205332
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.132089911
Short name T102
Test name
Test status
Simulation time 49414033076 ps
CPU time 2699.94 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:59:46 PM PDT 24
Peak memory 289908 kb
Host smart-3f8443f5-4168-403c-a8b5-23ba161de08e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132089911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.132089911
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1436582307
Short name T152
Test name
Test status
Simulation time 9083042614 ps
CPU time 663.97 seconds
Started Jun 25 07:12:03 PM PDT 24
Finished Jun 25 07:23:25 PM PDT 24
Peak memory 265436 kb
Host smart-2b263e9f-058b-4451-a6da-31d1a408e875
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436582307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1436582307
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2562946210
Short name T8
Test name
Test status
Simulation time 22880184113 ps
CPU time 469.98 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:22:06 PM PDT 24
Peak memory 249424 kb
Host smart-9d60e690-9d28-4fe0-b6ca-4fcedfd91df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562946210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2562946210
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4138903070
Short name T144
Test name
Test status
Simulation time 4474036985 ps
CPU time 321.52 seconds
Started Jun 25 07:12:08 PM PDT 24
Finished Jun 25 07:17:50 PM PDT 24
Peak memory 265488 kb
Host smart-8c4e4aec-43bf-4221-afa4-44020251e894
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4138903070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4138903070
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2306187286
Short name T334
Test name
Test status
Simulation time 8590548 ps
CPU time 1.5 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:12:42 PM PDT 24
Peak memory 236672 kb
Host smart-62a2f200-9c3f-41b6-b11e-9d36e44d17f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306187286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2306187286
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1686992715
Short name T153
Test name
Test status
Simulation time 172942098451 ps
CPU time 1018.13 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:29:02 PM PDT 24
Peak memory 265432 kb
Host smart-fda288c2-86bd-4715-8d1f-591f9f6c2045
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686992715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1686992715
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4156615348
Short name T227
Test name
Test status
Simulation time 1556096706 ps
CPU time 19.5 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:13:59 PM PDT 24
Peak memory 249300 kb
Host smart-5073dd35-98b8-47aa-b25e-ec801a8a497e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4156615348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4156615348
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3374358158
Short name T3
Test name
Test status
Simulation time 47843530118 ps
CPU time 1636.28 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:42:24 PM PDT 24
Peak memory 273960 kb
Host smart-e817428b-6348-49de-af6c-da7ca7a370b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374358158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3374358158
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1349051759
Short name T156
Test name
Test status
Simulation time 1745367024 ps
CPU time 239.51 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:16:06 PM PDT 24
Peak memory 272152 kb
Host smart-ac974f8b-783b-41ee-b8af-6782551b9111
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1349051759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1349051759
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2386398946
Short name T289
Test name
Test status
Simulation time 14662176370 ps
CPU time 549.1 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 07:23:43 PM PDT 24
Peak memory 249408 kb
Host smart-17e27428-ea19-4bf0-aa50-f0794fa86ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386398946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2386398946
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4280802382
Short name T314
Test name
Test status
Simulation time 214193480416 ps
CPU time 3422.19 seconds
Started Jun 25 07:15:45 PM PDT 24
Finished Jun 25 08:12:53 PM PDT 24
Peak memory 282112 kb
Host smart-914f1e4b-c7a8-4093-9b63-0e5e488d51e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280802382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4280802382
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1021869427
Short name T287
Test name
Test status
Simulation time 17528071004 ps
CPU time 368.81 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 07:23:37 PM PDT 24
Peak memory 257316 kb
Host smart-4bc5a28c-a774-4869-b173-70a6d0a594f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021869427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1021869427
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3402985015
Short name T135
Test name
Test status
Simulation time 153833452277 ps
CPU time 1119.31 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:31:06 PM PDT 24
Peak memory 265428 kb
Host smart-37552f08-f2fd-4685-b435-5eabd18d14be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402985015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3402985015
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1688944425
Short name T645
Test name
Test status
Simulation time 13914751641 ps
CPU time 519.46 seconds
Started Jun 25 07:14:20 PM PDT 24
Finished Jun 25 07:23:08 PM PDT 24
Peak memory 249424 kb
Host smart-8886ffe3-20da-4e42-924a-cc2186c189c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688944425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1688944425
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1630626499
Short name T138
Test name
Test status
Simulation time 9777881952 ps
CPU time 318.84 seconds
Started Jun 25 07:10:42 PM PDT 24
Finished Jun 25 07:16:11 PM PDT 24
Peak memory 265480 kb
Host smart-4f70963d-0f80-4e49-895c-9a97db728d7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630626499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1630626499
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1782792016
Short name T320
Test name
Test status
Simulation time 149338362296 ps
CPU time 2971.69 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 08:02:33 PM PDT 24
Peak memory 289904 kb
Host smart-e6d6a4a9-0c97-4e75-9836-a87bd9410f44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782792016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1782792016
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.385927547
Short name T90
Test name
Test status
Simulation time 28812064900 ps
CPU time 1445.53 seconds
Started Jun 25 07:17:04 PM PDT 24
Finished Jun 25 07:41:15 PM PDT 24
Peak memory 290296 kb
Host smart-c02c1646-c757-4dc2-ade2-ccb477553fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385927547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.385927547
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3101012875
Short name T332
Test name
Test status
Simulation time 13468212 ps
CPU time 1.44 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:11:27 PM PDT 24
Peak memory 236672 kb
Host smart-eb4047aa-8794-462e-bde3-6cbe4e44efdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3101012875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3101012875
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1256840302
Short name T254
Test name
Test status
Simulation time 56473626673 ps
CPU time 3255.08 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 08:08:01 PM PDT 24
Peak memory 290324 kb
Host smart-48a6d2fd-1dde-424f-bfa9-fbead6e3ccee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256840302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1256840302
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2926335581
Short name T53
Test name
Test status
Simulation time 48902241279 ps
CPU time 462.5 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:21:18 PM PDT 24
Peak memory 265784 kb
Host smart-5a97986b-9807-4fea-a251-890ae24bf081
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926335581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2926335581
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1062871228
Short name T122
Test name
Test status
Simulation time 6041206851 ps
CPU time 491.17 seconds
Started Jun 25 07:10:53 PM PDT 24
Finished Jun 25 07:19:20 PM PDT 24
Peak memory 265424 kb
Host smart-ef00ae16-f4a3-45fd-97a2-300957786e0d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062871228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1062871228
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2250242823
Short name T300
Test name
Test status
Simulation time 75284886074 ps
CPU time 284.01 seconds
Started Jun 25 07:15:04 PM PDT 24
Finished Jun 25 07:19:55 PM PDT 24
Peak memory 249428 kb
Host smart-ed530097-54dd-48a4-a8c0-55fd22bc566c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250242823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2250242823
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2619288713
Short name T240
Test name
Test status
Simulation time 201684201504 ps
CPU time 2774.58 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 08:03:43 PM PDT 24
Peak memory 322880 kb
Host smart-8c3a62f5-3ccd-4cc4-8016-0b290423251a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619288713 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2619288713
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.889605218
Short name T31
Test name
Test status
Simulation time 171217240596 ps
CPU time 5374.11 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 08:43:42 PM PDT 24
Peak memory 306060 kb
Host smart-aa76d86e-e8dd-4815-ba01-97b3368d1de0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889605218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.889605218
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3029927762
Short name T260
Test name
Test status
Simulation time 6031799074 ps
CPU time 245.33 seconds
Started Jun 25 07:14:53 PM PDT 24
Finished Jun 25 07:19:05 PM PDT 24
Peak memory 249432 kb
Host smart-20aaf1ad-77a3-47be-ae61-45612d09fbaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029927762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3029927762
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.445986338
Short name T148
Test name
Test status
Simulation time 4033558261 ps
CPU time 327.38 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:17:34 PM PDT 24
Peak memory 265544 kb
Host smart-c19be4d2-6146-420b-b3d7-f3999a702ace
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=445986338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.445986338
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2242988405
Short name T139
Test name
Test status
Simulation time 3522997824 ps
CPU time 110.16 seconds
Started Jun 25 07:10:52 PM PDT 24
Finished Jun 25 07:12:58 PM PDT 24
Peak memory 265480 kb
Host smart-40fcf060-d623-43a1-a381-05de17d04e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2242988405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2242988405
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1998986604
Short name T301
Test name
Test status
Simulation time 13245623400 ps
CPU time 279.66 seconds
Started Jun 25 07:13:36 PM PDT 24
Finished Jun 25 07:18:28 PM PDT 24
Peak memory 249424 kb
Host smart-cbb6d760-84fc-4d89-a561-e114441f1da7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998986604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1998986604
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1701817055
Short name T268
Test name
Test status
Simulation time 651201396 ps
CPU time 22.48 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:14:41 PM PDT 24
Peak memory 256840 kb
Host smart-ad4fe74a-525f-45a5-81d4-bffe74ca42d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17018
17055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1701817055
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1138960105
Short name T13
Test name
Test status
Simulation time 79620843206 ps
CPU time 2600.65 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:57:48 PM PDT 24
Peak memory 273164 kb
Host smart-7709c13e-6d7b-44a5-ac03-8e99f70c0e2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138960105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1138960105
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3158324773
Short name T271
Test name
Test status
Simulation time 2178890102 ps
CPU time 61.28 seconds
Started Jun 25 07:15:21 PM PDT 24
Finished Jun 25 07:16:27 PM PDT 24
Peak memory 257480 kb
Host smart-6f7383e0-4e8f-4a3c-8a8b-a7a9f11bdaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31583
24773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3158324773
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3400184118
Short name T239
Test name
Test status
Simulation time 35170136114 ps
CPU time 2686.87 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 08:00:51 PM PDT 24
Peak memory 289108 kb
Host smart-4ce2f971-3905-4ea5-b035-cd66ec3f9b7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400184118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3400184118
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2161130103
Short name T167
Test name
Test status
Simulation time 96610296 ps
CPU time 3.8 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:11:11 PM PDT 24
Peak memory 238648 kb
Host smart-014e2b99-1b3e-423a-bda2-31593e65a12c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2161130103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2161130103
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3722831244
Short name T7
Test name
Test status
Simulation time 13038787519 ps
CPU time 998.21 seconds
Started Jun 25 07:15:21 PM PDT 24
Finished Jun 25 07:32:04 PM PDT 24
Peak memory 273804 kb
Host smart-5c7d9f4d-1971-41fd-914f-69093d24d220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722831244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3722831244
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1216224760
Short name T179
Test name
Test status
Simulation time 501975975 ps
CPU time 23.4 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:11:08 PM PDT 24
Peak memory 245824 kb
Host smart-d9797995-f8d7-4417-bc0b-21693d965e4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1216224760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1216224760
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.296822030
Short name T196
Test name
Test status
Simulation time 14392073 ps
CPU time 2.4 seconds
Started Jun 25 07:12:19 PM PDT 24
Finished Jun 25 07:12:45 PM PDT 24
Peak memory 249568 kb
Host smart-98aff83c-46c0-43ce-b764-ef0b6412f65a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=296822030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.296822030
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1759559167
Short name T209
Test name
Test status
Simulation time 35284014 ps
CPU time 2.7 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 07:12:54 PM PDT 24
Peak memory 249544 kb
Host smart-52658b49-68f3-403a-a67b-04d66c4e953f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1759559167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1759559167
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.575488594
Short name T198
Test name
Test status
Simulation time 101240802 ps
CPU time 2.94 seconds
Started Jun 25 07:13:30 PM PDT 24
Finished Jun 25 07:13:43 PM PDT 24
Peak memory 249760 kb
Host smart-0fbd565e-5016-4300-9f8f-3ed87491751b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=575488594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.575488594
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2718166273
Short name T207
Test name
Test status
Simulation time 43683792 ps
CPU time 3.8 seconds
Started Jun 25 07:13:11 PM PDT 24
Finished Jun 25 07:13:25 PM PDT 24
Peak memory 249588 kb
Host smart-ccb94c6c-8f5d-4250-8a2c-a7e66f7a5488
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2718166273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2718166273
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1593029973
Short name T100
Test name
Test status
Simulation time 1603296871 ps
CPU time 47.66 seconds
Started Jun 25 07:12:20 PM PDT 24
Finished Jun 25 07:13:33 PM PDT 24
Peak memory 257296 kb
Host smart-19fa4aca-2e33-4f9b-b6ee-0e6c2a36befc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
29973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1593029973
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3400085758
Short name T651
Test name
Test status
Simulation time 6775801918 ps
CPU time 290.11 seconds
Started Jun 25 07:13:38 PM PDT 24
Finished Jun 25 07:18:40 PM PDT 24
Peak memory 255560 kb
Host smart-46d0a54f-2616-448d-bba0-2aa337f85558
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400085758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3400085758
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1090303154
Short name T318
Test name
Test status
Simulation time 54980573115 ps
CPU time 3327.35 seconds
Started Jun 25 07:13:38 PM PDT 24
Finished Jun 25 08:09:17 PM PDT 24
Peak memory 289504 kb
Host smart-684622e0-8aa2-4abc-800e-f64bcf5ef712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090303154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1090303154
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.680285123
Short name T243
Test name
Test status
Simulation time 71437080690 ps
CPU time 1117.46 seconds
Started Jun 25 07:14:52 PM PDT 24
Finished Jun 25 07:33:37 PM PDT 24
Peak memory 273736 kb
Host smart-cbebc283-1e25-43f3-9927-977327801199
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680285123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.680285123
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1845991519
Short name T215
Test name
Test status
Simulation time 236134457141 ps
CPU time 4795.73 seconds
Started Jun 25 07:12:42 PM PDT 24
Finished Jun 25 08:32:58 PM PDT 24
Peak memory 306824 kb
Host smart-c678c07d-e7e7-4be1-b172-94215040e2c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845991519 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1845991519
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3481516948
Short name T262
Test name
Test status
Simulation time 44308111740 ps
CPU time 2541.62 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:58:02 PM PDT 24
Peak memory 289628 kb
Host smart-f37582a0-0e4e-4ee8-a400-cc752a2bab28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481516948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3481516948
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1975064239
Short name T84
Test name
Test status
Simulation time 472859364 ps
CPU time 35.52 seconds
Started Jun 25 07:16:17 PM PDT 24
Finished Jun 25 07:16:56 PM PDT 24
Peak memory 256780 kb
Host smart-ec323a7d-320c-440b-b65e-b558a8546e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
64239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1975064239
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1442956299
Short name T276
Test name
Test status
Simulation time 271189315158 ps
CPU time 3857 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 08:21:42 PM PDT 24
Peak memory 306428 kb
Host smart-1b1ac467-534a-42c4-abfe-e55f64d6fbe1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442956299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1442956299
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1462866505
Short name T173
Test name
Test status
Simulation time 410757972 ps
CPU time 46.96 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:12:52 PM PDT 24
Peak memory 248660 kb
Host smart-d1cd4cd3-853c-4b3c-a658-8d08abe5c5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1462866505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1462866505
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.591323423
Short name T316
Test name
Test status
Simulation time 149296215106 ps
CPU time 1782.19 seconds
Started Jun 25 07:12:29 PM PDT 24
Finished Jun 25 07:42:35 PM PDT 24
Peak memory 273528 kb
Host smart-bbb3c43c-fde3-4f11-bbde-8faab5ad5e20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591323423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.591323423
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.61800472
Short name T291
Test name
Test status
Simulation time 12002128658 ps
CPU time 511.97 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:22:30 PM PDT 24
Peak memory 249412 kb
Host smart-84c598f6-f476-4881-8809-ad0b9d6bb82b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61800472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.61800472
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1392716006
Short name T283
Test name
Test status
Simulation time 45881514307 ps
CPU time 1489.74 seconds
Started Jun 25 07:12:36 PM PDT 24
Finished Jun 25 07:37:49 PM PDT 24
Peak memory 274012 kb
Host smart-df109c49-5945-45d1-b30c-579e6d061422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392716006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1392716006
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2942042172
Short name T88
Test name
Test status
Simulation time 84640873999 ps
CPU time 7150.18 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 09:13:28 PM PDT 24
Peak memory 335048 kb
Host smart-e629c159-14ce-49bd-b9ae-ecf876869b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942042172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2942042172
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3385763454
Short name T259
Test name
Test status
Simulation time 122763807009 ps
CPU time 5123.46 seconds
Started Jun 25 07:14:18 PM PDT 24
Finished Jun 25 08:39:51 PM PDT 24
Peak memory 354936 kb
Host smart-48b6156c-fac1-4a3f-bc42-f6a54e531e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385763454 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3385763454
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1615001798
Short name T274
Test name
Test status
Simulation time 45228698843 ps
CPU time 3019.68 seconds
Started Jun 25 07:14:18 PM PDT 24
Finished Jun 25 08:04:46 PM PDT 24
Peak memory 289744 kb
Host smart-60410b3a-2ba0-45f0-9661-588bddba743d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615001798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1615001798
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2834422668
Short name T238
Test name
Test status
Simulation time 37594895982 ps
CPU time 1022.66 seconds
Started Jun 25 07:15:35 PM PDT 24
Finished Jun 25 07:32:45 PM PDT 24
Peak memory 265736 kb
Host smart-453ac206-e551-42eb-834d-3e8d1f1274f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834422668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2834422668
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.590662392
Short name T112
Test name
Test status
Simulation time 309699250450 ps
CPU time 5716.44 seconds
Started Jun 25 07:15:33 PM PDT 24
Finished Jun 25 08:50:57 PM PDT 24
Peak memory 322880 kb
Host smart-1b228f36-f2fa-4504-ad5f-552f05aa48a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590662392 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.590662392
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3996235289
Short name T263
Test name
Test status
Simulation time 3035413717 ps
CPU time 11.23 seconds
Started Jun 25 07:15:43 PM PDT 24
Finished Jun 25 07:16:00 PM PDT 24
Peak memory 255496 kb
Host smart-07065950-e500-4c7e-bd10-bbf643992219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
35289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3996235289
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3192717905
Short name T235
Test name
Test status
Simulation time 51421910712 ps
CPU time 3241.41 seconds
Started Jun 25 07:12:56 PM PDT 24
Finished Jun 25 08:07:14 PM PDT 24
Peak memory 289900 kb
Host smart-534f9f3d-9050-4af3-a284-8efca3e2790f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192717905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3192717905
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2528272265
Short name T321
Test name
Test status
Simulation time 177738666344 ps
CPU time 2696.93 seconds
Started Jun 25 07:16:21 PM PDT 24
Finished Jun 25 08:01:22 PM PDT 24
Peak memory 290316 kb
Host smart-06ba2e71-0509-4765-9a39-2e8012c27517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528272265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2528272265
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1642319620
Short name T234
Test name
Test status
Simulation time 100432405572 ps
CPU time 2115.49 seconds
Started Jun 25 07:16:40 PM PDT 24
Finished Jun 25 07:52:00 PM PDT 24
Peak memory 289992 kb
Host smart-d5b4857c-1dda-4d28-8684-53ea83a3192d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642319620 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1642319620
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2441008896
Short name T265
Test name
Test status
Simulation time 579017648 ps
CPU time 34.23 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:18:04 PM PDT 24
Peak memory 248768 kb
Host smart-186a2c68-bcc4-4ea1-afe8-8a0b896f53d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24410
08896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2441008896
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3118233592
Short name T137
Test name
Test status
Simulation time 13951512237 ps
CPU time 306.67 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:16:40 PM PDT 24
Peak memory 272856 kb
Host smart-660c2de8-fe0a-4e7f-9e6e-bb62a1c788a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3118233592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3118233592
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3747358638
Short name T147
Test name
Test status
Simulation time 22789949018 ps
CPU time 386.11 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:18:26 PM PDT 24
Peak memory 265504 kb
Host smart-0811d6b0-379f-4f87-b72a-f254abd80719
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3747358638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3747358638
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2157588130
Short name T172
Test name
Test status
Simulation time 906472835 ps
CPU time 66.16 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:13:15 PM PDT 24
Peak memory 248856 kb
Host smart-ff49e96b-dd22-47d0-8c6b-b51ebed757d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2157588130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2157588130
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.661136724
Short name T130
Test name
Test status
Simulation time 6104554261 ps
CPU time 432.42 seconds
Started Jun 25 07:11:14 PM PDT 24
Finished Jun 25 07:18:40 PM PDT 24
Peak memory 265480 kb
Host smart-5b751ffd-b5a0-4c5a-b872-af6e542f6c81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=661136724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.661136724
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2072384028
Short name T169
Test name
Test status
Simulation time 114729302 ps
CPU time 6.61 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:10:53 PM PDT 24
Peak memory 236596 kb
Host smart-3a2aa2f6-9e31-4e90-99ab-9b63e65f0e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2072384028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2072384028
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1388493055
Short name T176
Test name
Test status
Simulation time 111371464 ps
CPU time 3.4 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:07 PM PDT 24
Peak memory 237592 kb
Host smart-df447ddd-e8b0-4133-a0ba-b6bdbf2068ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1388493055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1388493055
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1816436280
Short name T151
Test name
Test status
Simulation time 1071113705 ps
CPU time 115.4 seconds
Started Jun 25 07:11:58 PM PDT 24
Finished Jun 25 07:14:07 PM PDT 24
Peak memory 265428 kb
Host smart-8ab53434-1622-431d-ac5f-3da524badb2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1816436280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1816436280
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2989218107
Short name T174
Test name
Test status
Simulation time 622735045 ps
CPU time 49.6 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:13:16 PM PDT 24
Peak memory 248772 kb
Host smart-7cd6d986-d689-4c23-a6d0-a97ef9587833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2989218107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2989218107
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1133066912
Short name T180
Test name
Test status
Simulation time 3705955437 ps
CPU time 65.95 seconds
Started Jun 25 07:10:59 PM PDT 24
Finished Jun 25 07:12:21 PM PDT 24
Peak memory 246936 kb
Host smart-93422280-e819-4ce3-82a6-054cce900271
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1133066912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1133066912
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1515046463
Short name T175
Test name
Test status
Simulation time 111320642 ps
CPU time 5.97 seconds
Started Jun 25 07:11:09 PM PDT 24
Finished Jun 25 07:11:30 PM PDT 24
Peak memory 238064 kb
Host smart-1535f7b4-48bc-4fcb-b59d-3430202f63b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1515046463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1515046463
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2808407376
Short name T165
Test name
Test status
Simulation time 2408467416 ps
CPU time 67.4 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:12:42 PM PDT 24
Peak memory 245972 kb
Host smart-f77b1f2e-954c-4d8c-8e2d-80e9e1d7185d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2808407376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2808407376
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4104997324
Short name T171
Test name
Test status
Simulation time 48702931 ps
CPU time 2.38 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:10:49 PM PDT 24
Peak memory 237824 kb
Host smart-dd9bcde6-076e-4364-809d-f105e2dfe18e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4104997324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4104997324
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1658387634
Short name T166
Test name
Test status
Simulation time 1801143501 ps
CPU time 33.17 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:37 PM PDT 24
Peak memory 240564 kb
Host smart-bc618a96-b8f4-4cf8-a98a-ac4093abf3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1658387634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1658387634
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1716930019
Short name T159
Test name
Test status
Simulation time 75850938 ps
CPU time 2.24 seconds
Started Jun 25 07:11:58 PM PDT 24
Finished Jun 25 07:12:15 PM PDT 24
Peak memory 237904 kb
Host smart-029edcec-4776-4cb9-aec0-41e4f7eff29f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1716930019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1716930019
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3455430754
Short name T182
Test name
Test status
Simulation time 589925927 ps
CPU time 32.86 seconds
Started Jun 25 07:12:03 PM PDT 24
Finished Jun 25 07:12:56 PM PDT 24
Peak memory 240540 kb
Host smart-9debd765-667c-4e33-a17d-01bd1bcc61f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3455430754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3455430754
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.183122297
Short name T160
Test name
Test status
Simulation time 427555426 ps
CPU time 3.61 seconds
Started Jun 25 07:12:08 PM PDT 24
Finished Jun 25 07:12:32 PM PDT 24
Peak memory 237868 kb
Host smart-065d0b51-d328-4c48-b8b2-92bab4670850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=183122297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.183122297
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3571188496
Short name T181
Test name
Test status
Simulation time 59511758 ps
CPU time 3.8 seconds
Started Jun 25 07:11:09 PM PDT 24
Finished Jun 25 07:11:28 PM PDT 24
Peak memory 237272 kb
Host smart-86bed6f7-14f4-4e0f-9cb4-a8defaa56b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3571188496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3571188496
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4175096266
Short name T168
Test name
Test status
Simulation time 231521157 ps
CPU time 4.16 seconds
Started Jun 25 07:11:14 PM PDT 24
Finished Jun 25 07:11:31 PM PDT 24
Peak memory 237612 kb
Host smart-06d4505c-7357-4642-aa89-ffe5948584eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4175096266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4175096266
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2194535912
Short name T24
Test name
Test status
Simulation time 53234874667 ps
CPU time 1480.1 seconds
Started Jun 25 07:12:30 PM PDT 24
Finished Jun 25 07:37:34 PM PDT 24
Peak memory 273888 kb
Host smart-b8c3973a-0693-4f16-939c-8c84ca35ce0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194535912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2194535912
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4127389513
Short name T29
Test name
Test status
Simulation time 39308670963 ps
CPU time 2341.66 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:52:03 PM PDT 24
Peak memory 282208 kb
Host smart-8bf815b5-af52-48c3-9616-c74391dda4d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127389513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4127389513
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2319770893
Short name T23
Test name
Test status
Simulation time 392061774380 ps
CPU time 2603.19 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:58:51 PM PDT 24
Peak memory 289448 kb
Host smart-e2c78890-9110-433c-95dd-be7983ba029e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319770893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2319770893
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.408867910
Short name T723
Test name
Test status
Simulation time 16937782668 ps
CPU time 327.2 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:16:14 PM PDT 24
Peak memory 241680 kb
Host smart-177190d2-131e-4262-8ef2-65c8ffd6d87a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=408867910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.408867910
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2372039124
Short name T338
Test name
Test status
Simulation time 6531466394 ps
CPU time 226.37 seconds
Started Jun 25 07:10:41 PM PDT 24
Finished Jun 25 07:14:36 PM PDT 24
Peak memory 237676 kb
Host smart-e38729b4-6cc2-4822-9c3d-501758c64866
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2372039124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2372039124
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1479129748
Short name T778
Test name
Test status
Simulation time 22303321 ps
CPU time 4.24 seconds
Started Jun 25 07:10:39 PM PDT 24
Finished Jun 25 07:10:48 PM PDT 24
Peak memory 240576 kb
Host smart-ed6201cd-97c5-4d3d-b5e7-c3ccea250adc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1479129748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1479129748
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.366837526
Short name T746
Test name
Test status
Simulation time 122490403 ps
CPU time 5.72 seconds
Started Jun 25 07:10:41 PM PDT 24
Finished Jun 25 07:10:55 PM PDT 24
Peak memory 256908 kb
Host smart-50bf7295-f9ae-4376-adcb-37cffc6d8991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366837526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.366837526
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3309599526
Short name T724
Test name
Test status
Simulation time 1365771266 ps
CPU time 8.34 seconds
Started Jun 25 07:10:42 PM PDT 24
Finished Jun 25 07:11:01 PM PDT 24
Peak memory 236456 kb
Host smart-67eda7dc-5de9-4ab5-a952-fd5c2b9f76aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3309599526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3309599526
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2223819017
Short name T751
Test name
Test status
Simulation time 30393785 ps
CPU time 1.36 seconds
Started Jun 25 07:10:39 PM PDT 24
Finished Jun 25 07:10:43 PM PDT 24
Peak memory 237616 kb
Host smart-3ef9d1aa-3ee1-4978-a98b-ff370eddf1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223819017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2223819017
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4234918893
Short name T128
Test name
Test status
Simulation time 6592685831 ps
CPU time 464.55 seconds
Started Jun 25 07:10:31 PM PDT 24
Finished Jun 25 07:18:18 PM PDT 24
Peak memory 269272 kb
Host smart-57ad6b81-244f-41cf-a46a-6b16ef428b85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234918893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4234918893
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3688712969
Short name T795
Test name
Test status
Simulation time 137297885 ps
CPU time 4.63 seconds
Started Jun 25 07:10:42 PM PDT 24
Finished Jun 25 07:10:57 PM PDT 24
Peak memory 251748 kb
Host smart-8719e02d-5b75-416c-8dc4-be3b117932b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3688712969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3688712969
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1610844415
Short name T744
Test name
Test status
Simulation time 4031944058 ps
CPU time 160.34 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:13:27 PM PDT 24
Peak memory 240612 kb
Host smart-3c8564ac-9d1a-47b4-820f-8542dc4dcfe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1610844415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1610844415
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3945694951
Short name T186
Test name
Test status
Simulation time 3271167494 ps
CPU time 106.8 seconds
Started Jun 25 07:10:39 PM PDT 24
Finished Jun 25 07:12:31 PM PDT 24
Peak memory 237672 kb
Host smart-6372d84a-253e-4d61-a70b-d4bf0ea45a2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3945694951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3945694951
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1003396659
Short name T184
Test name
Test status
Simulation time 46685069 ps
CPU time 6.3 seconds
Started Jun 25 07:10:41 PM PDT 24
Finished Jun 25 07:10:55 PM PDT 24
Peak memory 248768 kb
Host smart-4ca94fe6-5dea-44f9-918b-a63cb4f4ce12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1003396659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1003396659
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1499586456
Short name T709
Test name
Test status
Simulation time 138898968 ps
CPU time 11.08 seconds
Started Jun 25 07:10:50 PM PDT 24
Finished Jun 25 07:11:17 PM PDT 24
Peak memory 240628 kb
Host smart-8a33e99f-d68a-475d-bf70-b976b8e8061e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499586456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1499586456
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3835752961
Short name T811
Test name
Test status
Simulation time 26786203 ps
CPU time 3.58 seconds
Started Jun 25 07:10:41 PM PDT 24
Finished Jun 25 07:10:52 PM PDT 24
Peak memory 240504 kb
Host smart-47febfdf-93b7-4b1e-941a-f644e009999a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3835752961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3835752961
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3166828064
Short name T781
Test name
Test status
Simulation time 9916125 ps
CPU time 1.58 seconds
Started Jun 25 07:10:39 PM PDT 24
Finished Jun 25 07:10:45 PM PDT 24
Peak memory 237616 kb
Host smart-34343681-5966-4933-b318-7031bc5c12f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3166828064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3166828064
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3498397723
Short name T706
Test name
Test status
Simulation time 1065952457 ps
CPU time 18.77 seconds
Started Jun 25 07:10:50 PM PDT 24
Finished Jun 25 07:11:26 PM PDT 24
Peak memory 248700 kb
Host smart-584c7ec3-4c4b-4495-adcf-e50668ccdc5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3498397723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3498397723
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3883525358
Short name T341
Test name
Test status
Simulation time 3104886877 ps
CPU time 309.33 seconds
Started Jun 25 07:10:40 PM PDT 24
Finished Jun 25 07:15:57 PM PDT 24
Peak memory 265440 kb
Host smart-d2df0e7f-d071-4062-94e8-a1b41bc0e15f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883525358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3883525358
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3140177750
Short name T742
Test name
Test status
Simulation time 426458128 ps
CPU time 12.81 seconds
Started Jun 25 07:10:39 PM PDT 24
Finished Jun 25 07:10:57 PM PDT 24
Peak memory 248308 kb
Host smart-4eb4248c-d37d-437d-af83-011e8f7361b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3140177750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3140177750
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1702196410
Short name T782
Test name
Test status
Simulation time 134693391 ps
CPU time 9.38 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:12 PM PDT 24
Peak memory 240596 kb
Host smart-b31052ed-69eb-4491-aee8-409d0d62f069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702196410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1702196410
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2711852280
Short name T342
Test name
Test status
Simulation time 37857761 ps
CPU time 5.36 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:11:40 PM PDT 24
Peak memory 236676 kb
Host smart-b282d5b9-e092-4c43-98cc-9cbca8886617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2711852280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2711852280
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4266919775
Short name T758
Test name
Test status
Simulation time 14567845 ps
CPU time 1.37 seconds
Started Jun 25 07:11:24 PM PDT 24
Finished Jun 25 07:11:34 PM PDT 24
Peak memory 237616 kb
Host smart-efad2854-1027-4d28-8764-38c77ad25b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4266919775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4266919775
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3774070429
Short name T177
Test name
Test status
Simulation time 1411743026 ps
CPU time 29.35 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:12:30 PM PDT 24
Peak memory 245820 kb
Host smart-43622ce5-62f5-4421-9788-804c7fdf0b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3774070429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3774070429
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2459764631
Short name T127
Test name
Test status
Simulation time 4442124504 ps
CPU time 314.11 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:16:48 PM PDT 24
Peak memory 265432 kb
Host smart-93ae29e2-a8fc-48c0-be44-0f782dba1a3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459764631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2459764631
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2575363364
Short name T747
Test name
Test status
Simulation time 195816288 ps
CPU time 11.33 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:45 PM PDT 24
Peak memory 248896 kb
Host smart-29c617fb-d6ad-4152-94ad-4202bfa71dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575363364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2575363364
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3456746409
Short name T739
Test name
Test status
Simulation time 796049597 ps
CPU time 22.71 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:11:57 PM PDT 24
Peak memory 245828 kb
Host smart-961df222-3301-43a7-b0d1-1eac456861ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3456746409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3456746409
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3088343144
Short name T793
Test name
Test status
Simulation time 257740248 ps
CPU time 13.79 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:12:16 PM PDT 24
Peak memory 251852 kb
Host smart-b526ff78-2b28-4c23-801d-803f4f65e3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088343144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3088343144
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3090324005
Short name T188
Test name
Test status
Simulation time 244678235 ps
CPU time 9.61 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:12:17 PM PDT 24
Peak memory 237616 kb
Host smart-ff660b79-9149-4641-baa3-a5eb3866967f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3090324005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3090324005
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3994476647
Short name T733
Test name
Test status
Simulation time 45979480 ps
CPU time 1.6 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:12:09 PM PDT 24
Peak memory 236600 kb
Host smart-dd0c47e2-5882-4f92-83ad-016c93265cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3994476647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3994476647
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.573369960
Short name T734
Test name
Test status
Simulation time 5077586464 ps
CPU time 49.61 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:52 PM PDT 24
Peak memory 248836 kb
Host smart-0465efa4-eada-4756-99d3-db1cfcf843aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=573369960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.573369960
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3956313523
Short name T704
Test name
Test status
Simulation time 1173065963 ps
CPU time 15.12 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:12:23 PM PDT 24
Peak memory 247728 kb
Host smart-f5878609-eea8-4248-9aea-7445491b10de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3956313523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3956313523
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1013615398
Short name T713
Test name
Test status
Simulation time 59214253 ps
CPU time 5.18 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:12:08 PM PDT 24
Peak memory 248832 kb
Host smart-0b25b954-c6fe-4711-ae18-e102940d9181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013615398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1013615398
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3710952430
Short name T799
Test name
Test status
Simulation time 35115669 ps
CPU time 5.11 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:09 PM PDT 24
Peak memory 236676 kb
Host smart-b3da8dc4-3cb6-45de-a569-9604b440692a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3710952430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3710952430
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3088592500
Short name T749
Test name
Test status
Simulation time 7943519 ps
CPU time 1.55 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:12:07 PM PDT 24
Peak memory 236592 kb
Host smart-46bfbb10-b99d-4182-95d4-678bc675b91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3088592500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3088592500
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2558968763
Short name T770
Test name
Test status
Simulation time 356336136 ps
CPU time 13.47 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:12:20 PM PDT 24
Peak memory 245760 kb
Host smart-e22b908d-6aa7-4251-8950-faaa59cabd80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2558968763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2558968763
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.811874157
Short name T126
Test name
Test status
Simulation time 713052483 ps
CPU time 80.28 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:13:22 PM PDT 24
Peak memory 257176 kb
Host smart-9ef171d5-8a5e-4f8c-8990-5263608f6a01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=811874157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.811874157
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.609474645
Short name T146
Test name
Test status
Simulation time 4465491474 ps
CPU time 677.03 seconds
Started Jun 25 07:11:52 PM PDT 24
Finished Jun 25 07:23:16 PM PDT 24
Peak memory 265416 kb
Host smart-9ddfeffe-a5ae-4755-b1c8-24bdf6eb9495
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609474645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.609474645
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2245437799
Short name T710
Test name
Test status
Simulation time 607381819 ps
CPU time 12.07 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:16 PM PDT 24
Peak memory 253616 kb
Host smart-f46b9e53-c2be-4f4d-aacc-64e46fb549fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2245437799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2245437799
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2659838517
Short name T773
Test name
Test status
Simulation time 135006215 ps
CPU time 11.68 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:12:13 PM PDT 24
Peak memory 252148 kb
Host smart-26ba0844-9f5c-4398-84a8-6d4a25d99a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659838517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2659838517
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3327453604
Short name T340
Test name
Test status
Simulation time 187238047 ps
CPU time 4.75 seconds
Started Jun 25 07:11:53 PM PDT 24
Finished Jun 25 07:12:05 PM PDT 24
Peak memory 236668 kb
Host smart-a5bb02e1-c2e0-4fb5-8e81-24bf52d185bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3327453604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3327453604
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2987441543
Short name T743
Test name
Test status
Simulation time 14891676 ps
CPU time 1.42 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:12:04 PM PDT 24
Peak memory 236672 kb
Host smart-092ed97b-ae40-471e-806e-7b094a536f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2987441543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2987441543
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1172130448
Short name T812
Test name
Test status
Simulation time 359848969 ps
CPU time 12.6 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:12:19 PM PDT 24
Peak memory 245820 kb
Host smart-d7ea6ee8-36fd-4e40-b44d-08251d1f5aba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1172130448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1172130448
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3904156797
Short name T143
Test name
Test status
Simulation time 5048570576 ps
CPU time 667.61 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:23:12 PM PDT 24
Peak memory 265432 kb
Host smart-7691fcca-3559-4f12-8046-308276a37271
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904156797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3904156797
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2034054243
Short name T714
Test name
Test status
Simulation time 41336918 ps
CPU time 6.01 seconds
Started Jun 25 07:11:52 PM PDT 24
Finished Jun 25 07:12:05 PM PDT 24
Peak memory 248356 kb
Host smart-14b4eb08-b36d-4b6a-a5e7-8eebf1e883cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034054243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2034054243
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1857425714
Short name T776
Test name
Test status
Simulation time 233627156 ps
CPU time 9.73 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:12:20 PM PDT 24
Peak memory 254396 kb
Host smart-91edb7a8-79ca-4663-beeb-2e801f8ac45a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857425714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1857425714
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3010355268
Short name T731
Test name
Test status
Simulation time 70828363 ps
CPU time 6.24 seconds
Started Jun 25 07:11:58 PM PDT 24
Finished Jun 25 07:12:18 PM PDT 24
Peak memory 240576 kb
Host smart-e83dd47f-37f6-48d4-94c8-a2f41e09b0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3010355268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3010355268
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1196231298
Short name T735
Test name
Test status
Simulation time 7881349 ps
CPU time 1.36 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:12:11 PM PDT 24
Peak memory 237636 kb
Host smart-d9ce6c49-dd96-4c50-844f-3344ae7f1c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1196231298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1196231298
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3043408740
Short name T790
Test name
Test status
Simulation time 1046487173 ps
CPU time 51.63 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:13:02 PM PDT 24
Peak memory 245816 kb
Host smart-90b15491-2e86-4042-88d8-dae68c77c633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3043408740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3043408740
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.963287147
Short name T155
Test name
Test status
Simulation time 16104770986 ps
CPU time 1139.16 seconds
Started Jun 25 07:11:55 PM PDT 24
Finished Jun 25 07:31:06 PM PDT 24
Peak memory 265420 kb
Host smart-14fd630d-f4ac-4d93-be40-f26e6635bd45
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963287147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.963287147
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1737915162
Short name T768
Test name
Test status
Simulation time 1237347842 ps
CPU time 19.64 seconds
Started Jun 25 07:11:59 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 248300 kb
Host smart-ac18926f-8357-4834-8250-c696f3f1db99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1737915162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1737915162
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2283659934
Short name T740
Test name
Test status
Simulation time 115027571 ps
CPU time 4.92 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:12:15 PM PDT 24
Peak memory 248896 kb
Host smart-a8a028a8-04be-4309-b724-12adf5cb3a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283659934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2283659934
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2043823412
Short name T794
Test name
Test status
Simulation time 216476494 ps
CPU time 9.1 seconds
Started Jun 25 07:11:59 PM PDT 24
Finished Jun 25 07:12:23 PM PDT 24
Peak memory 236652 kb
Host smart-52be67f2-c8e1-46be-92e6-519baef6b9d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2043823412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2043823412
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.987056609
Short name T808
Test name
Test status
Simulation time 14789762 ps
CPU time 1.32 seconds
Started Jun 25 07:11:59 PM PDT 24
Finished Jun 25 07:12:15 PM PDT 24
Peak memory 236756 kb
Host smart-8160c46a-527b-4147-9486-7c914dd94ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=987056609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.987056609
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3822614362
Short name T738
Test name
Test status
Simulation time 513779703 ps
CPU time 19.83 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:12:28 PM PDT 24
Peak memory 244860 kb
Host smart-a70672a2-3a14-4b88-8dbc-92a14d202a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3822614362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3822614362
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2611012585
Short name T145
Test name
Test status
Simulation time 3461929158 ps
CPU time 122.26 seconds
Started Jun 25 07:11:59 PM PDT 24
Finished Jun 25 07:14:15 PM PDT 24
Peak memory 265468 kb
Host smart-ea774ed6-08c9-43bc-a3e2-2d727e0e909d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2611012585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2611012585
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.289706651
Short name T149
Test name
Test status
Simulation time 4293846259 ps
CPU time 389.91 seconds
Started Jun 25 07:11:57 PM PDT 24
Finished Jun 25 07:18:41 PM PDT 24
Peak memory 270500 kb
Host smart-6b173980-6c36-4b9f-9f73-beda8b26785f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289706651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.289706651
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.981797833
Short name T707
Test name
Test status
Simulation time 925757967 ps
CPU time 24.8 seconds
Started Jun 25 07:11:56 PM PDT 24
Finished Jun 25 07:12:32 PM PDT 24
Peak memory 248828 kb
Host smart-7c5a2dc0-66bb-4e39-aa19-847f95e3419c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=981797833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.981797833
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2597594362
Short name T785
Test name
Test status
Simulation time 352229296 ps
CPU time 12.21 seconds
Started Jun 25 07:12:02 PM PDT 24
Finished Jun 25 07:12:33 PM PDT 24
Peak memory 243772 kb
Host smart-22474122-03df-401b-88f2-c703bdd727f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597594362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2597594362
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3340882703
Short name T753
Test name
Test status
Simulation time 34530704 ps
CPU time 5.74 seconds
Started Jun 25 07:12:03 PM PDT 24
Finished Jun 25 07:12:29 PM PDT 24
Peak memory 237516 kb
Host smart-0e5aa290-7695-47b3-bdf8-964973ceb22d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3340882703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3340882703
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.189484154
Short name T331
Test name
Test status
Simulation time 9915173 ps
CPU time 1.25 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:12:38 PM PDT 24
Peak memory 235528 kb
Host smart-425532da-37ad-41f8-9613-7a312c437ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=189484154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.189484154
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1339678447
Short name T189
Test name
Test status
Simulation time 331010394 ps
CPU time 22.63 seconds
Started Jun 25 07:12:04 PM PDT 24
Finished Jun 25 07:12:46 PM PDT 24
Peak memory 245820 kb
Host smart-2b2a3acc-8c10-4fe1-a4b8-0aa0dae48b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1339678447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1339678447
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1541787966
Short name T134
Test name
Test status
Simulation time 32160304844 ps
CPU time 567.33 seconds
Started Jun 25 07:11:54 PM PDT 24
Finished Jun 25 07:21:31 PM PDT 24
Peak memory 269300 kb
Host smart-b21576d0-f3be-41c7-88c3-53784127a115
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541787966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1541787966
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.544581594
Short name T752
Test name
Test status
Simulation time 63325487 ps
CPU time 4.02 seconds
Started Jun 25 07:11:59 PM PDT 24
Finished Jun 25 07:12:18 PM PDT 24
Peak memory 251208 kb
Host smart-7f1082f2-7fc9-433c-9852-314d7060fe77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=544581594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.544581594
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3964778649
Short name T796
Test name
Test status
Simulation time 479490373 ps
CPU time 8.04 seconds
Started Jun 25 07:12:12 PM PDT 24
Finished Jun 25 07:12:42 PM PDT 24
Peak memory 256916 kb
Host smart-f7bd0d55-3473-40a4-a0bc-0c16a96a6ef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964778649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3964778649
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2113167774
Short name T789
Test name
Test status
Simulation time 47904372 ps
CPU time 4.53 seconds
Started Jun 25 07:12:04 PM PDT 24
Finished Jun 25 07:12:28 PM PDT 24
Peak memory 237768 kb
Host smart-995e2922-53b9-4515-8e62-7ac1836e354b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2113167774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2113167774
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1432238710
Short name T774
Test name
Test status
Simulation time 10038441 ps
CPU time 1.29 seconds
Started Jun 25 07:12:03 PM PDT 24
Finished Jun 25 07:12:23 PM PDT 24
Peak memory 236676 kb
Host smart-08fccdd6-b1e9-461d-bfdc-4d3760662f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1432238710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1432238710
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2007117333
Short name T718
Test name
Test status
Simulation time 716175288 ps
CPU time 51.2 seconds
Started Jun 25 07:12:05 PM PDT 24
Finished Jun 25 07:13:16 PM PDT 24
Peak memory 248732 kb
Host smart-966cc2d5-8c52-4ff5-aaf4-0fd140da231d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2007117333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2007117333
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1269423414
Short name T783
Test name
Test status
Simulation time 159912305 ps
CPU time 13.9 seconds
Started Jun 25 07:12:04 PM PDT 24
Finished Jun 25 07:12:37 PM PDT 24
Peak memory 248836 kb
Host smart-ec10c08b-7e84-49bc-a7b2-527a7a15d60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1269423414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1269423414
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2119459632
Short name T792
Test name
Test status
Simulation time 83362087 ps
CPU time 7.71 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 241272 kb
Host smart-749b6d67-cd11-4c46-9653-a53c92cb0870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119459632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2119459632
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.368552997
Short name T759
Test name
Test status
Simulation time 70266260 ps
CPU time 5.4 seconds
Started Jun 25 07:12:08 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 237620 kb
Host smart-3320c69f-723b-4729-b9fb-cc083b51c4f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=368552997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.368552997
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3871252729
Short name T164
Test name
Test status
Simulation time 8190334 ps
CPU time 1.55 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:30 PM PDT 24
Peak memory 236688 kb
Host smart-f3c323f0-a263-4380-900c-d020e49a36df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3871252729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3871252729
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.115017272
Short name T819
Test name
Test status
Simulation time 174860991 ps
CPU time 27.11 seconds
Started Jun 25 07:12:04 PM PDT 24
Finished Jun 25 07:12:52 PM PDT 24
Peak memory 245820 kb
Host smart-ef6ed100-c9af-4d82-af22-fda18926c026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=115017272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.115017272
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1026197817
Short name T154
Test name
Test status
Simulation time 1442595464 ps
CPU time 94.26 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:14:11 PM PDT 24
Peak memory 256932 kb
Host smart-29e2e729-f280-4ea5-a5e8-9f7f82071a75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1026197817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1026197817
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1018088033
Short name T125
Test name
Test status
Simulation time 4718059427 ps
CPU time 711.93 seconds
Started Jun 25 07:12:04 PM PDT 24
Finished Jun 25 07:24:17 PM PDT 24
Peak memory 273272 kb
Host smart-1a618ec1-3341-466e-a1b9-45f1789b7a58
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018088033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1018088033
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.73691885
Short name T788
Test name
Test status
Simulation time 342465895 ps
CPU time 9.46 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:12:46 PM PDT 24
Peak memory 248904 kb
Host smart-25ac3f3d-4b40-4b38-bc9c-c817f7f0af8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=73691885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.73691885
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2497949798
Short name T816
Test name
Test status
Simulation time 69129659 ps
CPU time 5.98 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 240588 kb
Host smart-58bd7b8a-a1ea-4829-896d-dd4b910c7b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497949798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2497949798
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1176691112
Short name T803
Test name
Test status
Simulation time 32355512 ps
CPU time 3.34 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:31 PM PDT 24
Peak memory 237612 kb
Host smart-ac99d3ee-c754-4aee-a9c5-b56cf05138ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1176691112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1176691112
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3417878345
Short name T732
Test name
Test status
Simulation time 17244883 ps
CPU time 1.32 seconds
Started Jun 25 07:12:12 PM PDT 24
Finished Jun 25 07:12:36 PM PDT 24
Peak memory 237616 kb
Host smart-24779918-fd90-4959-a905-9daf449b900e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3417878345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3417878345
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3402568605
Short name T779
Test name
Test status
Simulation time 262681819 ps
CPU time 20.16 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:12:46 PM PDT 24
Peak memory 248760 kb
Host smart-0abbe8d9-26f8-41de-b743-2c8c9aa11df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3402568605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3402568605
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1143868800
Short name T124
Test name
Test status
Simulation time 816383854 ps
CPU time 94.68 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:14:02 PM PDT 24
Peak memory 265404 kb
Host smart-ddf06490-5b08-4fae-a7db-2039b10ecd70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1143868800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1143868800
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2385962237
Short name T806
Test name
Test status
Simulation time 1875051691 ps
CPU time 27.46 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:56 PM PDT 24
Peak memory 248960 kb
Host smart-a6b880bd-2401-4acd-913f-e79334a0a557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2385962237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2385962237
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1355642459
Short name T712
Test name
Test status
Simulation time 2230130421 ps
CPU time 160.71 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:13:48 PM PDT 24
Peak memory 240632 kb
Host smart-9a0a7240-a85e-4d2e-a8df-db2ab69b9725
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1355642459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1355642459
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.42148090
Short name T804
Test name
Test status
Simulation time 8905992649 ps
CPU time 513.07 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:19:41 PM PDT 24
Peak memory 237680 kb
Host smart-a1754b28-08ef-4b8c-8579-f78aa1d5041e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=42148090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.42148090
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1439248090
Short name T191
Test name
Test status
Simulation time 133910440 ps
CPU time 9.78 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:11:17 PM PDT 24
Peak memory 248780 kb
Host smart-bdb9fc32-7b8f-45f8-8b6b-609d4f62b149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1439248090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1439248090
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1312152129
Short name T339
Test name
Test status
Simulation time 602345220 ps
CPU time 13.53 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:11:21 PM PDT 24
Peak memory 256460 kb
Host smart-97c68116-6a38-484e-9860-4b491059337f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312152129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1312152129
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1836570388
Short name T717
Test name
Test status
Simulation time 39538338 ps
CPU time 3.14 seconds
Started Jun 25 07:10:51 PM PDT 24
Finished Jun 25 07:11:10 PM PDT 24
Peak memory 236668 kb
Host smart-3b41cae6-4e36-45ad-a4b9-939a2595ceb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1836570388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1836570388
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3916919950
Short name T741
Test name
Test status
Simulation time 22286915 ps
CPU time 1.43 seconds
Started Jun 25 07:10:49 PM PDT 24
Finished Jun 25 07:11:08 PM PDT 24
Peak memory 236668 kb
Host smart-16ee9b3c-bdfa-498a-aae4-83ba3f8bf2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3916919950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3916919950
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4048647422
Short name T780
Test name
Test status
Simulation time 659842228 ps
CPU time 21.62 seconds
Started Jun 25 07:10:52 PM PDT 24
Finished Jun 25 07:11:30 PM PDT 24
Peak memory 248768 kb
Host smart-2ac7305b-e541-46a4-b49d-177c206320d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048647422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4048647422
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.231544593
Short name T821
Test name
Test status
Simulation time 8688477129 ps
CPU time 159.4 seconds
Started Jun 25 07:10:50 PM PDT 24
Finished Jun 25 07:13:46 PM PDT 24
Peak memory 264780 kb
Host smart-02c4ebbf-4cd5-4af0-994f-3ff76ae6769d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=231544593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.231544593
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2405506097
Short name T703
Test name
Test status
Simulation time 82594819 ps
CPU time 6.01 seconds
Started Jun 25 07:10:50 PM PDT 24
Finished Jun 25 07:11:12 PM PDT 24
Peak memory 249704 kb
Host smart-dd5f7454-e278-4d93-b5d6-0d8e857ce274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2405506097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2405506097
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.651502884
Short name T222
Test name
Test status
Simulation time 15214930 ps
CPU time 1.5 seconds
Started Jun 25 07:12:10 PM PDT 24
Finished Jun 25 07:12:32 PM PDT 24
Peak memory 237640 kb
Host smart-86e1e358-fa33-4d6a-9b25-15ca5c3a6640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651502884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.651502884
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.927598904
Short name T791
Test name
Test status
Simulation time 7560071 ps
CPU time 1.49 seconds
Started Jun 25 07:12:09 PM PDT 24
Finished Jun 25 07:12:32 PM PDT 24
Peak memory 237640 kb
Host smart-652000da-d46a-4cde-95b9-0edc77b3136f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=927598904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.927598904
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1196936146
Short name T822
Test name
Test status
Simulation time 7619534 ps
CPU time 1.48 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:12:38 PM PDT 24
Peak memory 236744 kb
Host smart-704eac66-82fe-4b9b-bbe7-9bf8b1e0a3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1196936146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1196936146
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.791708847
Short name T730
Test name
Test status
Simulation time 11706494 ps
CPU time 1.66 seconds
Started Jun 25 07:12:08 PM PDT 24
Finished Jun 25 07:12:30 PM PDT 24
Peak memory 236664 kb
Host smart-74c29309-7243-48b1-8654-594f2ab3bb04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=791708847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.791708847
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3169287210
Short name T809
Test name
Test status
Simulation time 15644008 ps
CPU time 1.36 seconds
Started Jun 25 07:12:11 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 237568 kb
Host smart-b51687f4-f525-4462-9258-95d02346116a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3169287210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3169287210
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.972525489
Short name T777
Test name
Test status
Simulation time 24505930 ps
CPU time 1.43 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:30 PM PDT 24
Peak memory 236736 kb
Host smart-50d778d4-af24-470f-bfff-760f0e0e67df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=972525489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.972525489
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3316605046
Short name T805
Test name
Test status
Simulation time 24059871 ps
CPU time 1.51 seconds
Started Jun 25 07:12:12 PM PDT 24
Finished Jun 25 07:12:36 PM PDT 24
Peak memory 236700 kb
Host smart-eaaa201b-ec65-46ef-be76-7ea589fc9472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316605046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3316605046
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4125757247
Short name T163
Test name
Test status
Simulation time 9632978 ps
CPU time 1.32 seconds
Started Jun 25 07:12:13 PM PDT 24
Finished Jun 25 07:12:37 PM PDT 24
Peak memory 235724 kb
Host smart-4f55cda9-6a21-466f-a5c1-b3391af045e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4125757247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4125757247
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1118325978
Short name T721
Test name
Test status
Simulation time 14253452 ps
CPU time 1.31 seconds
Started Jun 25 07:12:11 PM PDT 24
Finished Jun 25 07:12:34 PM PDT 24
Peak memory 235688 kb
Host smart-f1d41fef-7254-4970-9d4d-e36e4435febe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118325978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1118325978
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2881863473
Short name T335
Test name
Test status
Simulation time 26808452 ps
CPU time 1.48 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:30 PM PDT 24
Peak memory 237592 kb
Host smart-3ea48c7e-8897-4976-81ba-3acd9f47ceb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2881863473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2881863473
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3248356996
Short name T760
Test name
Test status
Simulation time 18551774238 ps
CPU time 356.38 seconds
Started Jun 25 07:11:00 PM PDT 24
Finished Jun 25 07:17:12 PM PDT 24
Peak memory 242716 kb
Host smart-9398cbf4-b5ef-4df3-971b-baa349d9298e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3248356996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3248356996
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4158527087
Short name T745
Test name
Test status
Simulation time 3270621775 ps
CPU time 131.49 seconds
Started Jun 25 07:11:01 PM PDT 24
Finished Jun 25 07:13:27 PM PDT 24
Peak memory 240632 kb
Host smart-af5b7b91-dc96-4f7e-bd96-9517e07f5b5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4158527087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4158527087
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3857743211
Short name T708
Test name
Test status
Simulation time 81611472 ps
CPU time 5.37 seconds
Started Jun 25 07:11:01 PM PDT 24
Finished Jun 25 07:11:22 PM PDT 24
Peak memory 248760 kb
Host smart-c7467f71-98dc-4d88-9e24-2d1c812a8846
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3857743211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3857743211
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1018878416
Short name T820
Test name
Test status
Simulation time 271648057 ps
CPU time 4.97 seconds
Started Jun 25 07:11:00 PM PDT 24
Finished Jun 25 07:11:21 PM PDT 24
Peak memory 240044 kb
Host smart-68641662-2e4c-43b3-ac2c-31b21e81c3d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018878416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1018878416
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2834184121
Short name T824
Test name
Test status
Simulation time 1776154198 ps
CPU time 8.75 seconds
Started Jun 25 07:10:59 PM PDT 24
Finished Jun 25 07:11:23 PM PDT 24
Peak memory 237464 kb
Host smart-b4cad947-98e3-4002-a73b-6517a3b26e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2834184121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2834184121
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1401085577
Short name T775
Test name
Test status
Simulation time 27669334 ps
CPU time 1.33 seconds
Started Jun 25 07:11:01 PM PDT 24
Finished Jun 25 07:11:17 PM PDT 24
Peak memory 237484 kb
Host smart-d553e1fe-46aa-40fb-a2fa-25baf39cbbce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1401085577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1401085577
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.173841957
Short name T185
Test name
Test status
Simulation time 361363496 ps
CPU time 11.13 seconds
Started Jun 25 07:11:02 PM PDT 24
Finished Jun 25 07:11:28 PM PDT 24
Peak memory 248784 kb
Host smart-b324ee37-f9a3-4d0a-9cf0-195546904c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=173841957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.173841957
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4086931723
Short name T754
Test name
Test status
Simulation time 416843969 ps
CPU time 18 seconds
Started Jun 25 07:11:00 PM PDT 24
Finished Jun 25 07:11:34 PM PDT 24
Peak memory 248908 kb
Host smart-f9757f8a-2d40-4b36-aef4-2a10da3af8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4086931723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4086931723
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.551491514
Short name T817
Test name
Test status
Simulation time 24313370 ps
CPU time 1.39 seconds
Started Jun 25 07:12:13 PM PDT 24
Finished Jun 25 07:12:37 PM PDT 24
Peak memory 237616 kb
Host smart-ad119bc1-e892-4965-b25a-d60f582a4f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=551491514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.551491514
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4150161648
Short name T823
Test name
Test status
Simulation time 23229643 ps
CPU time 2.09 seconds
Started Jun 25 07:12:06 PM PDT 24
Finished Jun 25 07:12:28 PM PDT 24
Peak memory 236840 kb
Host smart-3e06047f-52bf-4786-9470-7a37d855934c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4150161648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4150161648
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3330894102
Short name T761
Test name
Test status
Simulation time 7122452 ps
CPU time 1.27 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:12:38 PM PDT 24
Peak memory 236676 kb
Host smart-86d21a57-9a69-4499-9811-574fb9b59230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330894102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3330894102
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.277253441
Short name T719
Test name
Test status
Simulation time 21076087 ps
CPU time 1.35 seconds
Started Jun 25 07:12:08 PM PDT 24
Finished Jun 25 07:12:31 PM PDT 24
Peak memory 236672 kb
Host smart-f3e10f22-d2cb-4254-b3d0-5f1a01c02771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=277253441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.277253441
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1295833734
Short name T800
Test name
Test status
Simulation time 8477234 ps
CPU time 1.58 seconds
Started Jun 25 07:12:07 PM PDT 24
Finished Jun 25 07:12:28 PM PDT 24
Peak memory 236660 kb
Host smart-30d7de94-9b75-4636-bfcc-5243d6cbd914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295833734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1295833734
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2619900161
Short name T766
Test name
Test status
Simulation time 16389839 ps
CPU time 1.33 seconds
Started Jun 25 07:12:10 PM PDT 24
Finished Jun 25 07:12:33 PM PDT 24
Peak memory 235636 kb
Host smart-d9833b36-4f04-4d47-bae0-7debb9daa0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2619900161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2619900161
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.685494999
Short name T813
Test name
Test status
Simulation time 55468547 ps
CPU time 1.22 seconds
Started Jun 25 07:12:10 PM PDT 24
Finished Jun 25 07:12:33 PM PDT 24
Peak memory 237504 kb
Host smart-ccd516b6-4ee9-4763-adf6-0d81656f48b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=685494999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.685494999
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.814184872
Short name T762
Test name
Test status
Simulation time 23069439 ps
CPU time 1.52 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:43 PM PDT 24
Peak memory 236672 kb
Host smart-b9c13b81-c6a6-4c3d-9a99-973ab2f42a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=814184872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.814184872
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.581412052
Short name T729
Test name
Test status
Simulation time 6902378 ps
CPU time 1.37 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:42 PM PDT 24
Peak memory 237624 kb
Host smart-a678ac39-e088-401f-9270-f5b14f47ff7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=581412052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.581412052
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1517931451
Short name T767
Test name
Test status
Simulation time 2347422447 ps
CPU time 85.91 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:12:51 PM PDT 24
Peak memory 240608 kb
Host smart-3fa6ec04-9053-4b61-80bd-3e5ac9cb0164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1517931451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1517931451
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1401067505
Short name T726
Test name
Test status
Simulation time 17842137862 ps
CPU time 250.92 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:15:36 PM PDT 24
Peak memory 237688 kb
Host smart-780e403b-032a-447b-80ab-c9c111b3ef7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1401067505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1401067505
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2232859504
Short name T715
Test name
Test status
Simulation time 24094299 ps
CPU time 3.62 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:11:29 PM PDT 24
Peak memory 252364 kb
Host smart-1c202521-53cd-45c2-a25b-152633871a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2232859504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2232859504
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1724932862
Short name T784
Test name
Test status
Simulation time 75061313 ps
CPU time 9.44 seconds
Started Jun 25 07:11:13 PM PDT 24
Finished Jun 25 07:11:36 PM PDT 24
Peak memory 256784 kb
Host smart-2cbc81aa-8226-4b14-85fa-b6e4ad73ffff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724932862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1724932862
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.147662985
Short name T720
Test name
Test status
Simulation time 133023718 ps
CPU time 12.13 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:11:36 PM PDT 24
Peak memory 237604 kb
Host smart-835ae389-7333-4bc7-b422-f38998ac7ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=147662985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.147662985
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1430109077
Short name T750
Test name
Test status
Simulation time 20775107 ps
CPU time 1.39 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:11:26 PM PDT 24
Peak memory 236664 kb
Host smart-7582d89f-9469-487f-a291-6efa99dc5d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1430109077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1430109077
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3893796127
Short name T756
Test name
Test status
Simulation time 271680888 ps
CPU time 20.01 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:11:44 PM PDT 24
Peak memory 244872 kb
Host smart-e5d8c405-c6b8-433b-857d-91a2a2b18794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3893796127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3893796127
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1990236421
Short name T141
Test name
Test status
Simulation time 3637239234 ps
CPU time 203.28 seconds
Started Jun 25 07:11:09 PM PDT 24
Finished Jun 25 07:14:47 PM PDT 24
Peak memory 265576 kb
Host smart-6ffa8eac-8d22-4234-b6c8-cd46b85b555f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1990236421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1990236421
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1960894115
Short name T705
Test name
Test status
Simulation time 90455778 ps
CPU time 10.71 seconds
Started Jun 25 07:11:13 PM PDT 24
Finished Jun 25 07:11:37 PM PDT 24
Peak memory 248844 kb
Host smart-9ad7ec26-6f62-4f3d-a632-cf6b5e19ef34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1960894115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1960894115
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1087134824
Short name T797
Test name
Test status
Simulation time 9628469 ps
CPU time 1.6 seconds
Started Jun 25 07:12:14 PM PDT 24
Finished Jun 25 07:12:40 PM PDT 24
Peak memory 236672 kb
Host smart-2d2f903b-8530-406d-894e-5b2f0974d0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1087134824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1087134824
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1534894528
Short name T757
Test name
Test status
Simulation time 7428233 ps
CPU time 1.34 seconds
Started Jun 25 07:12:22 PM PDT 24
Finished Jun 25 07:12:48 PM PDT 24
Peak memory 235724 kb
Host smart-816eeecb-7402-49e4-86af-fc33c6825a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1534894528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1534894528
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3747990497
Short name T337
Test name
Test status
Simulation time 8535801 ps
CPU time 1.54 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:43 PM PDT 24
Peak memory 237612 kb
Host smart-c4238806-7e40-4bd8-881c-ae5b84d4ef6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747990497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3747990497
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3589415600
Short name T736
Test name
Test status
Simulation time 8756926 ps
CPU time 1.48 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:43 PM PDT 24
Peak memory 237620 kb
Host smart-d287a1ce-ea52-4ba3-bf15-f817f5fc9ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3589415600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3589415600
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.329787255
Short name T333
Test name
Test status
Simulation time 12205882 ps
CPU time 1.72 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:12:45 PM PDT 24
Peak memory 236716 kb
Host smart-84ce7805-06f6-49c8-83b5-48d41ca6680f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=329787255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.329787255
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3902740115
Short name T763
Test name
Test status
Simulation time 76511856 ps
CPU time 1.58 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:12:42 PM PDT 24
Peak memory 237620 kb
Host smart-75ecbed8-095e-42f6-ae7b-6ccc4e9e8bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902740115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3902740115
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.957156144
Short name T162
Test name
Test status
Simulation time 6183073 ps
CPU time 1.39 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:12:44 PM PDT 24
Peak memory 237620 kb
Host smart-fd82852f-3a87-4d77-9c54-280cc781cb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=957156144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.957156144
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2539904086
Short name T798
Test name
Test status
Simulation time 7512918 ps
CPU time 1.36 seconds
Started Jun 25 07:12:15 PM PDT 24
Finished Jun 25 07:12:41 PM PDT 24
Peak memory 235648 kb
Host smart-1ba8529a-357a-46f1-a252-61b71c0017c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2539904086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2539904086
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1856196627
Short name T815
Test name
Test status
Simulation time 13727459 ps
CPU time 1.24 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:44 PM PDT 24
Peak memory 236672 kb
Host smart-09925418-4028-40ec-9d1c-a7960c8eef05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1856196627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1856196627
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2042193417
Short name T725
Test name
Test status
Simulation time 19666030 ps
CPU time 1.95 seconds
Started Jun 25 07:12:20 PM PDT 24
Finished Jun 25 07:12:47 PM PDT 24
Peak memory 237652 kb
Host smart-295de44b-d1c0-4ccb-8187-800e8f8337e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2042193417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2042193417
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.50157406
Short name T810
Test name
Test status
Simulation time 108972874 ps
CPU time 4.4 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:11:29 PM PDT 24
Peak memory 241500 kb
Host smart-dda4dba6-e3f7-4c1c-88c8-c82c86e76613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50157406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.alert_handler_csr_mem_rw_with_rand_reset.50157406
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2491206488
Short name T178
Test name
Test status
Simulation time 24892127 ps
CPU time 3.99 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:11:29 PM PDT 24
Peak memory 236696 kb
Host smart-bd5db218-cdf8-4f74-baaf-83c7a777246d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2491206488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2491206488
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1433530290
Short name T737
Test name
Test status
Simulation time 10292673 ps
CPU time 1.42 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:11:27 PM PDT 24
Peak memory 237620 kb
Host smart-c2a0af03-e5f7-43f4-b89a-49d8cb8f476d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1433530290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1433530290
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.932937873
Short name T755
Test name
Test status
Simulation time 327085242 ps
CPU time 22.1 seconds
Started Jun 25 07:11:12 PM PDT 24
Finished Jun 25 07:11:48 PM PDT 24
Peak memory 244876 kb
Host smart-e9f306d9-9035-48e3-af54-a3b6a93fcf7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=932937873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.932937873
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3845769984
Short name T133
Test name
Test status
Simulation time 45596357038 ps
CPU time 964.05 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:27:29 PM PDT 24
Peak memory 265436 kb
Host smart-7f0e2287-0489-4d4b-b6e4-42245ac07d92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845769984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3845769984
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2640357353
Short name T769
Test name
Test status
Simulation time 824924042 ps
CPU time 11.6 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:11:37 PM PDT 24
Peak memory 248860 kb
Host smart-0878ef93-a672-4288-9acd-8d658ce556a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2640357353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2640357353
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.219941426
Short name T802
Test name
Test status
Simulation time 343448548 ps
CPU time 12.87 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:11:47 PM PDT 24
Peak memory 252028 kb
Host smart-46f1d3e4-856e-4dfe-a6e9-3a3e2b7866c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219941426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.219941426
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3207016187
Short name T771
Test name
Test status
Simulation time 183855386 ps
CPU time 7.22 seconds
Started Jun 25 07:11:12 PM PDT 24
Finished Jun 25 07:11:33 PM PDT 24
Peak memory 236664 kb
Host smart-4612114c-4a3f-4305-92bc-bc028b0886c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3207016187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3207016187
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.119532599
Short name T187
Test name
Test status
Simulation time 2585533848 ps
CPU time 45.32 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:12:11 PM PDT 24
Peak memory 245892 kb
Host smart-f206114f-cd6f-4150-ac7b-0f5700acb80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=119532599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.119532599
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3164220718
Short name T121
Test name
Test status
Simulation time 4206521296 ps
CPU time 217.89 seconds
Started Jun 25 07:11:10 PM PDT 24
Finished Jun 25 07:15:02 PM PDT 24
Peak memory 265480 kb
Host smart-0f5cd9b9-d281-40b4-8c84-a8e96c8cbe49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3164220718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3164220718
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1105901720
Short name T157
Test name
Test status
Simulation time 24635283007 ps
CPU time 1061.56 seconds
Started Jun 25 07:11:12 PM PDT 24
Finished Jun 25 07:29:08 PM PDT 24
Peak memory 265652 kb
Host smart-a660fa36-d0dd-414c-8428-d5979e15076c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105901720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1105901720
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1179768252
Short name T765
Test name
Test status
Simulation time 65217347 ps
CPU time 8.03 seconds
Started Jun 25 07:11:11 PM PDT 24
Finished Jun 25 07:11:33 PM PDT 24
Peak memory 253552 kb
Host smart-b5100617-1ef8-42cf-afbd-c13fcfa49c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1179768252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1179768252
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2978014154
Short name T772
Test name
Test status
Simulation time 530733559 ps
CPU time 5.96 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:41 PM PDT 24
Peak memory 239144 kb
Host smart-0be29043-7644-4c1d-8320-889aff741900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978014154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2978014154
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2668280249
Short name T230
Test name
Test status
Simulation time 1329933639 ps
CPU time 9.75 seconds
Started Jun 25 07:11:28 PM PDT 24
Finished Jun 25 07:11:45 PM PDT 24
Peak memory 237624 kb
Host smart-0f12f6c3-fd3e-4d27-a617-a3fddc2997c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2668280249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2668280249
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3260123367
Short name T336
Test name
Test status
Simulation time 20250939 ps
CPU time 1.95 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:36 PM PDT 24
Peak memory 237612 kb
Host smart-ef074e8d-cd2d-4482-ab2d-ba95e399e95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260123367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3260123367
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3652344244
Short name T748
Test name
Test status
Simulation time 624663355 ps
CPU time 23.26 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:57 PM PDT 24
Peak memory 244888 kb
Host smart-9ed01b50-aea7-4f85-8a73-14375e352234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652344244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3652344244
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.879543226
Short name T158
Test name
Test status
Simulation time 8528623101 ps
CPU time 162.53 seconds
Started Jun 25 07:11:24 PM PDT 24
Finished Jun 25 07:14:16 PM PDT 24
Peak memory 265572 kb
Host smart-f6370214-ef3b-4861-886d-4a4c53bcc4d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=879543226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.879543226
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2742580733
Short name T132
Test name
Test status
Simulation time 21740204682 ps
CPU time 581.53 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:21:16 PM PDT 24
Peak memory 265408 kb
Host smart-e156c38e-f109-4625-9e48-2f1affce0133
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742580733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2742580733
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3314153911
Short name T787
Test name
Test status
Simulation time 119109290 ps
CPU time 8.42 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:43 PM PDT 24
Peak memory 253792 kb
Host smart-97b0f508-a770-455b-b148-3a4f79e9f3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3314153911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3314153911
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.406706363
Short name T801
Test name
Test status
Simulation time 1021427071 ps
CPU time 11.05 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:46 PM PDT 24
Peak memory 239912 kb
Host smart-e31aa095-2f0c-49b4-b55e-dff9fe11bba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406706363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.406706363
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1344502111
Short name T818
Test name
Test status
Simulation time 481992203 ps
CPU time 9.96 seconds
Started Jun 25 07:11:24 PM PDT 24
Finished Jun 25 07:11:43 PM PDT 24
Peak memory 237552 kb
Host smart-b00567f4-de57-4b5b-a9df-d92645797f68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1344502111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1344502111
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1017649702
Short name T764
Test name
Test status
Simulation time 18645615 ps
CPU time 1.4 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:35 PM PDT 24
Peak memory 236688 kb
Host smart-8a26bd67-f44b-4858-9230-a8e90aaa81b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1017649702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1017649702
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1468379588
Short name T716
Test name
Test status
Simulation time 1602432837 ps
CPU time 22.23 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:56 PM PDT 24
Peak memory 248788 kb
Host smart-880ada6f-77c5-4787-b557-34243318e31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1468379588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1468379588
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3373497096
Short name T131
Test name
Test status
Simulation time 1005066350 ps
CPU time 99.43 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:13:14 PM PDT 24
Peak memory 265356 kb
Host smart-2b0b8e25-9a78-4a70-a355-4b3e22ca4cff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3373497096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3373497096
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3213309414
Short name T150
Test name
Test status
Simulation time 4533441152 ps
CPU time 786.06 seconds
Started Jun 25 07:11:24 PM PDT 24
Finished Jun 25 07:24:40 PM PDT 24
Peak memory 265440 kb
Host smart-f77cd352-b6d3-493b-b469-ea8bc199b493
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213309414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3213309414
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3488070111
Short name T814
Test name
Test status
Simulation time 66532002 ps
CPU time 8.29 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:42 PM PDT 24
Peak memory 248820 kb
Host smart-9420edca-1c08-4c6c-acf3-349bf8f1f51c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3488070111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3488070111
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1421995781
Short name T807
Test name
Test status
Simulation time 158180570 ps
CPU time 26.5 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:12:01 PM PDT 24
Peak memory 240296 kb
Host smart-60824772-f3f7-45e5-b19f-6b749ae557cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1421995781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1421995781
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1457833878
Short name T722
Test name
Test status
Simulation time 226933172 ps
CPU time 4.83 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:39 PM PDT 24
Peak memory 237332 kb
Host smart-266a5b71-56d2-454b-9db0-f0d5331e9f11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457833878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1457833878
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2193966237
Short name T727
Test name
Test status
Simulation time 123381913 ps
CPU time 4.98 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:40 PM PDT 24
Peak memory 237636 kb
Host smart-b47a93da-2ca5-4bbf-850e-7438b7abbdce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2193966237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2193966237
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3300108706
Short name T786
Test name
Test status
Simulation time 10586871 ps
CPU time 1.55 seconds
Started Jun 25 07:11:27 PM PDT 24
Finished Jun 25 07:11:36 PM PDT 24
Peak memory 236128 kb
Host smart-660407f0-dc74-4973-8cc7-52d96f7f82b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300108706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3300108706
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2569043935
Short name T728
Test name
Test status
Simulation time 250184501 ps
CPU time 17.12 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:11:51 PM PDT 24
Peak memory 240528 kb
Host smart-21809f7b-e400-4b44-86c0-1e383c660ee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2569043935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2569043935
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1886646189
Short name T136
Test name
Test status
Simulation time 9672642162 ps
CPU time 167.32 seconds
Started Jun 25 07:11:25 PM PDT 24
Finished Jun 25 07:14:21 PM PDT 24
Peak memory 265488 kb
Host smart-6712bda2-19bd-4bb1-b02a-33d7cada6813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1886646189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1886646189
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2303963311
Short name T140
Test name
Test status
Simulation time 78068846576 ps
CPU time 1315.46 seconds
Started Jun 25 07:11:26 PM PDT 24
Finished Jun 25 07:33:30 PM PDT 24
Peak memory 265424 kb
Host smart-1a8e9d90-f6ae-4a98-9e33-a1bb98ffdf74
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303963311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2303963311
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2721085783
Short name T711
Test name
Test status
Simulation time 978920557 ps
CPU time 16.78 seconds
Started Jun 25 07:11:28 PM PDT 24
Finished Jun 25 07:11:52 PM PDT 24
Peak memory 248792 kb
Host smart-b0445680-c113-46bc-9e0f-24b9ee4e08c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2721085783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2721085783
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1657735521
Short name T170
Test name
Test status
Simulation time 89385929 ps
CPU time 4.11 seconds
Started Jun 25 07:11:24 PM PDT 24
Finished Jun 25 07:11:38 PM PDT 24
Peak memory 237620 kb
Host smart-4d9d8294-e298-490c-a502-aede7d7be777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1657735521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1657735521
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3899835850
Short name T4
Test name
Test status
Simulation time 28173120330 ps
CPU time 1682.74 seconds
Started Jun 25 07:12:20 PM PDT 24
Finished Jun 25 07:40:48 PM PDT 24
Peak memory 282136 kb
Host smart-644daeff-26cd-46e9-a012-608e0fc0481d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899835850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3899835850
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2866849946
Short name T686
Test name
Test status
Simulation time 8791309812 ps
CPU time 42.37 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:13:25 PM PDT 24
Peak memory 249388 kb
Host smart-2e76719f-f920-4799-ba31-3a86597328fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2866849946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2866849946
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3319749409
Short name T485
Test name
Test status
Simulation time 2072629300 ps
CPU time 124.59 seconds
Started Jun 25 07:12:22 PM PDT 24
Finished Jun 25 07:14:51 PM PDT 24
Peak memory 256984 kb
Host smart-7adea5af-4fb4-419d-97d9-8a3252d5b76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
49409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3319749409
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3148283599
Short name T486
Test name
Test status
Simulation time 771739288 ps
CPU time 24.05 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:13:07 PM PDT 24
Peak memory 256176 kb
Host smart-9adafe4b-0ee2-49fc-8857-8d320d880910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
83599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3148283599
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3298868066
Short name T672
Test name
Test status
Simulation time 147331050561 ps
CPU time 1782.15 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:42:23 PM PDT 24
Peak memory 273912 kb
Host smart-97d64c9d-4712-4e59-bf7a-22faa1c80cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298868066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3298868066
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2185961541
Short name T634
Test name
Test status
Simulation time 20152172900 ps
CPU time 1324.21 seconds
Started Jun 25 07:12:22 PM PDT 24
Finished Jun 25 07:34:51 PM PDT 24
Peak memory 266816 kb
Host smart-c6311889-41ea-4091-b88b-95694cd1996c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185961541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2185961541
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3633868296
Short name T44
Test name
Test status
Simulation time 9958534674 ps
CPU time 210.66 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:16:11 PM PDT 24
Peak memory 249428 kb
Host smart-7d475eb1-6ba9-472e-b0c8-a202e1ea747a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633868296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3633868296
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1013816412
Short name T674
Test name
Test status
Simulation time 492003159 ps
CPU time 19.54 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:13:00 PM PDT 24
Peak memory 249340 kb
Host smart-68aaa7dc-941d-407c-9e99-254c4f24579c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10138
16412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1013816412
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.573976352
Short name T429
Test name
Test status
Simulation time 436731329 ps
CPU time 28.19 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:13:09 PM PDT 24
Peak memory 248816 kb
Host smart-10a8446b-a55e-4ba7-b0d4-efd94c925875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57397
6352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.573976352
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2753826316
Short name T38
Test name
Test status
Simulation time 1572845149 ps
CPU time 14.11 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:12:55 PM PDT 24
Peak memory 270784 kb
Host smart-1f5b8a65-b00c-4019-90fd-27665fc6ee94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2753826316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2753826316
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3895297810
Short name T694
Test name
Test status
Simulation time 61971313 ps
CPU time 5.34 seconds
Started Jun 25 07:12:17 PM PDT 24
Finished Jun 25 07:12:46 PM PDT 24
Peak memory 249276 kb
Host smart-12c74bab-ea87-4364-8774-ae61fe42b170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
97810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3895297810
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1861542542
Short name T619
Test name
Test status
Simulation time 11557436280 ps
CPU time 100.66 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:14:21 PM PDT 24
Peak memory 257648 kb
Host smart-3bd40c63-d52d-4a10-93ac-272bcc4cb115
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861542542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1861542542
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1817116296
Short name T702
Test name
Test status
Simulation time 18179897261 ps
CPU time 2225.76 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:49:49 PM PDT 24
Peak memory 298572 kb
Host smart-71792ce7-20af-4fa6-b077-985286f43995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817116296 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1817116296
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1959414669
Short name T431
Test name
Test status
Simulation time 46940870414 ps
CPU time 2881.09 seconds
Started Jun 25 07:12:35 PM PDT 24
Finished Jun 25 08:00:59 PM PDT 24
Peak memory 290100 kb
Host smart-2f204902-ce23-4333-ba5e-27f14c4c80f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959414669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1959414669
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1556241491
Short name T609
Test name
Test status
Simulation time 564129729 ps
CPU time 25.07 seconds
Started Jun 25 07:12:31 PM PDT 24
Finished Jun 25 07:13:19 PM PDT 24
Peak memory 249224 kb
Host smart-b8b2d118-6fe7-440b-86fa-a1a8174deac3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1556241491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1556241491
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3324174158
Short name T389
Test name
Test status
Simulation time 2886024900 ps
CPU time 72.02 seconds
Started Jun 25 07:12:19 PM PDT 24
Finished Jun 25 07:13:55 PM PDT 24
Peak memory 257100 kb
Host smart-f0f26ced-cf74-4038-92f6-1b1a27d99002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
74158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3324174158
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.357514200
Short name T691
Test name
Test status
Simulation time 4732850629 ps
CPU time 67.18 seconds
Started Jun 25 07:12:15 PM PDT 24
Finished Jun 25 07:13:46 PM PDT 24
Peak memory 257636 kb
Host smart-29efc02c-8b1f-4182-8178-0abecb65e158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
4200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.357514200
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3673006113
Short name T36
Test name
Test status
Simulation time 59781988318 ps
CPU time 1392.61 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 07:36:04 PM PDT 24
Peak memory 290196 kb
Host smart-28ac01b2-9fe5-46ba-afbe-5cce209f3c8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673006113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3673006113
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.517106266
Short name T299
Test name
Test status
Simulation time 44685503711 ps
CPU time 400.12 seconds
Started Jun 25 07:12:29 PM PDT 24
Finished Jun 25 07:19:33 PM PDT 24
Peak memory 249380 kb
Host smart-0ce0bb1a-8cce-4fe8-b21a-011955b79f98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517106266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.517106266
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.926462961
Short name T669
Test name
Test status
Simulation time 137976723 ps
CPU time 13.28 seconds
Started Jun 25 07:12:21 PM PDT 24
Finished Jun 25 07:12:59 PM PDT 24
Peak memory 249344 kb
Host smart-6b8714b6-8311-45a7-9776-9171335ae7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92646
2961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.926462961
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1382474271
Short name T62
Test name
Test status
Simulation time 1167522082 ps
CPU time 65.68 seconds
Started Jun 25 07:12:16 PM PDT 24
Finished Jun 25 07:13:47 PM PDT 24
Peak memory 248828 kb
Host smart-f24b3a6d-d1fd-4c8f-8bad-4ef4d72cdebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13824
74271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1382474271
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4269002169
Short name T37
Test name
Test status
Simulation time 652891219 ps
CPU time 31.62 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 07:13:23 PM PDT 24
Peak memory 275044 kb
Host smart-7d7cf8d8-170c-4880-9f85-dc6cd0c07c28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4269002169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4269002169
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3750416793
Short name T524
Test name
Test status
Simulation time 325707695 ps
CPU time 40.51 seconds
Started Jun 25 07:12:18 PM PDT 24
Finished Jun 25 07:13:24 PM PDT 24
Peak memory 256628 kb
Host smart-c8133356-0e62-4026-831c-a45a5dad92cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
16793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3750416793
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.848264446
Short name T364
Test name
Test status
Simulation time 412085930 ps
CPU time 27.68 seconds
Started Jun 25 07:12:15 PM PDT 24
Finished Jun 25 07:13:07 PM PDT 24
Peak memory 249232 kb
Host smart-0a00636c-372c-4906-a6ae-837047921cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84826
4446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.848264446
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3310588165
Short name T685
Test name
Test status
Simulation time 15402302164 ps
CPU time 337.77 seconds
Started Jun 25 07:12:32 PM PDT 24
Finished Jun 25 07:18:32 PM PDT 24
Peak memory 265752 kb
Host smart-730f9257-f3d3-420a-b940-859fbd3c72df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310588165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3310588165
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4019231384
Short name T204
Test name
Test status
Simulation time 46408140 ps
CPU time 3.7 seconds
Started Jun 25 07:13:36 PM PDT 24
Finished Jun 25 07:13:52 PM PDT 24
Peak memory 249592 kb
Host smart-1c7223a3-708e-4e33-8f2a-8a014ecdace9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4019231384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4019231384
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.507904517
Short name T548
Test name
Test status
Simulation time 32951526556 ps
CPU time 2129.42 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:48:56 PM PDT 24
Peak memory 273264 kb
Host smart-16256b6c-02ff-440f-adf8-a32e0b629000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507904517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.507904517
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3476312787
Short name T563
Test name
Test status
Simulation time 1278212908 ps
CPU time 47.07 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:14:26 PM PDT 24
Peak memory 249304 kb
Host smart-bc3db5d4-15ce-43bd-8c82-175c1c904999
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3476312787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3476312787
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4010971727
Short name T569
Test name
Test status
Simulation time 25523429733 ps
CPU time 248.87 seconds
Started Jun 25 07:13:18 PM PDT 24
Finished Jun 25 07:17:36 PM PDT 24
Peak memory 257484 kb
Host smart-531b00ba-083d-481f-9fc8-9502bf70e221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
71727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4010971727
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1009337796
Short name T516
Test name
Test status
Simulation time 296587608 ps
CPU time 8.97 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:13:33 PM PDT 24
Peak memory 248780 kb
Host smart-c084fe87-dac1-4496-9932-2cfe98626421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
37796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1009337796
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.301423127
Short name T40
Test name
Test status
Simulation time 201655128811 ps
CPU time 1581.1 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:39:48 PM PDT 24
Peak memory 281988 kb
Host smart-eb9cf764-bab7-4070-8e66-9c7b89742513
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301423127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.301423127
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.499377243
Short name T77
Test name
Test status
Simulation time 12387880875 ps
CPU time 698.98 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:25:18 PM PDT 24
Peak memory 274012 kb
Host smart-3a6368a3-2c9c-4719-8780-139a4fc0a294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499377243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.499377243
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3898410386
Short name T308
Test name
Test status
Simulation time 7747826598 ps
CPU time 89.11 seconds
Started Jun 25 07:13:21 PM PDT 24
Finished Jun 25 07:14:58 PM PDT 24
Peak memory 249456 kb
Host smart-5fd0c233-d6d4-4008-9ff7-4c0b295cb639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898410386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3898410386
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.948798022
Short name T535
Test name
Test status
Simulation time 281230721 ps
CPU time 9.29 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:13:35 PM PDT 24
Peak memory 249316 kb
Host smart-274f139a-07c7-4f7f-814b-88a64828a684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94879
8022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.948798022
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2809753963
Short name T250
Test name
Test status
Simulation time 767043083 ps
CPU time 35.5 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:14:01 PM PDT 24
Peak memory 248816 kb
Host smart-05a71372-c737-42c1-9141-bd2e2a72af96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
53963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2809753963
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2261622218
Short name T509
Test name
Test status
Simulation time 121833264 ps
CPU time 8.8 seconds
Started Jun 25 07:13:23 PM PDT 24
Finished Jun 25 07:13:41 PM PDT 24
Peak memory 254964 kb
Host smart-9da5576e-f0b8-4686-ae91-ccdc3f1d4e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
22218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2261622218
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2166858727
Short name T402
Test name
Test status
Simulation time 416373332 ps
CPU time 25.77 seconds
Started Jun 25 07:13:19 PM PDT 24
Finished Jun 25 07:13:53 PM PDT 24
Peak memory 249252 kb
Host smart-59036817-be2d-48d2-9ee1-2692e12d7083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21668
58727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2166858727
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.135717691
Short name T97
Test name
Test status
Simulation time 46083683026 ps
CPU time 2200.77 seconds
Started Jun 25 07:13:30 PM PDT 24
Finished Jun 25 07:50:21 PM PDT 24
Peak memory 302800 kb
Host smart-ddb80ee2-6a02-4a7b-8bbd-b6accb08eba9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135717691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.135717691
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3712515227
Short name T68
Test name
Test status
Simulation time 102860714 ps
CPU time 3.12 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:13:39 PM PDT 24
Peak memory 249604 kb
Host smart-9c3a2390-d746-4678-8c15-52cebd0296b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3712515227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3712515227
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2366199955
Short name T581
Test name
Test status
Simulation time 9260215334 ps
CPU time 853.25 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:27:49 PM PDT 24
Peak memory 273460 kb
Host smart-bec37d4a-49b8-46cb-8914-9b3920385616
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366199955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2366199955
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.31614592
Short name T407
Test name
Test status
Simulation time 616336363 ps
CPU time 29.16 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:14:04 PM PDT 24
Peak memory 249308 kb
Host smart-2a084f54-9f31-4e69-96a9-9a703008c03a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=31614592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.31614592
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1880926815
Short name T598
Test name
Test status
Simulation time 6369327576 ps
CPU time 123.47 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:15:39 PM PDT 24
Peak memory 256956 kb
Host smart-a0e29743-5317-41ef-953c-1948e71bd64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18809
26815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1880926815
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1127966942
Short name T546
Test name
Test status
Simulation time 64048643 ps
CPU time 4.61 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:13:40 PM PDT 24
Peak memory 241052 kb
Host smart-4e4aa2c8-32e4-49bb-9252-a13d4bb85d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
66942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1127966942
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1766610389
Short name T679
Test name
Test status
Simulation time 26742592161 ps
CPU time 1625.46 seconds
Started Jun 25 07:13:37 PM PDT 24
Finished Jun 25 07:40:55 PM PDT 24
Peak memory 273172 kb
Host smart-fe512417-804c-4a1e-a69f-cdb6e0fcc02b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766610389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1766610389
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3803464347
Short name T46
Test name
Test status
Simulation time 8768290281 ps
CPU time 1042.49 seconds
Started Jun 25 07:13:25 PM PDT 24
Finished Jun 25 07:30:57 PM PDT 24
Peak memory 273812 kb
Host smart-a8b0e572-1d29-4237-9542-3527cbb3a952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803464347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3803464347
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3731672919
Short name T9
Test name
Test status
Simulation time 3793384395 ps
CPU time 153.84 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 07:16:11 PM PDT 24
Peak memory 249244 kb
Host smart-82c2b373-91d1-425b-b115-2affa151fa5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731672919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3731672919
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3002600766
Short name T345
Test name
Test status
Simulation time 2231658760 ps
CPU time 26.52 seconds
Started Jun 25 07:13:30 PM PDT 24
Finished Jun 25 07:14:06 PM PDT 24
Peak memory 256848 kb
Host smart-27f50486-2422-4af0-922c-f0ff00cbced4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30026
00766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3002600766
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.680704107
Short name T418
Test name
Test status
Simulation time 692416606 ps
CPU time 46.62 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:14:21 PM PDT 24
Peak memory 257380 kb
Host smart-b4a36ba9-c6d0-40b3-b0bb-f74d99e0a61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68070
4107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.680704107
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.111878554
Short name T543
Test name
Test status
Simulation time 263500721 ps
CPU time 10.93 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:13:47 PM PDT 24
Peak memory 249268 kb
Host smart-35a4d7bf-00b0-40fb-851c-1e39435e74c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187
8554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.111878554
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1165897495
Short name T531
Test name
Test status
Simulation time 7593826825 ps
CPU time 38.76 seconds
Started Jun 25 07:13:34 PM PDT 24
Finished Jun 25 07:14:24 PM PDT 24
Peak memory 257296 kb
Host smart-43ac9f36-a078-4346-8d16-825bc5a9b421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11658
97495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1165897495
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1343636348
Short name T200
Test name
Test status
Simulation time 15857370 ps
CPU time 2.38 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:13:41 PM PDT 24
Peak memory 249604 kb
Host smart-894bd75d-572e-4e7b-acb7-c12635ad572c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1343636348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1343636348
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2736045890
Short name T512
Test name
Test status
Simulation time 85521798500 ps
CPU time 2825.15 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 08:00:53 PM PDT 24
Peak memory 282132 kb
Host smart-901ca5c9-e85a-4fa5-895d-2daefe3f507c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736045890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2736045890
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1793925768
Short name T513
Test name
Test status
Simulation time 367479052 ps
CPU time 10.72 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 07:13:56 PM PDT 24
Peak memory 249220 kb
Host smart-7d42acf2-1980-4083-861f-0056bb469816
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1793925768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1793925768
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3052546025
Short name T236
Test name
Test status
Simulation time 32507088852 ps
CPU time 297.57 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:18:32 PM PDT 24
Peak memory 257144 kb
Host smart-902004d5-c16a-4941-ad44-1bb38391a97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
46025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3052546025
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1254439101
Short name T369
Test name
Test status
Simulation time 382790171 ps
CPU time 30.21 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:14:06 PM PDT 24
Peak memory 257472 kb
Host smart-ffed8d17-937c-4028-981e-ca3f5357a2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12544
39101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1254439101
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3569117724
Short name T661
Test name
Test status
Simulation time 141725129431 ps
CPU time 2837.03 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 08:00:55 PM PDT 24
Peak memory 290416 kb
Host smart-bc69b761-3b40-49b8-a9ab-8dcdf7dd43c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569117724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3569117724
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.732025811
Short name T482
Test name
Test status
Simulation time 1060114375 ps
CPU time 23.34 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 07:14:01 PM PDT 24
Peak memory 256716 kb
Host smart-361da590-fbd0-473f-a072-63e531097647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73202
5811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.732025811
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1091000623
Short name T51
Test name
Test status
Simulation time 511599671 ps
CPU time 16.77 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:13:53 PM PDT 24
Peak memory 248816 kb
Host smart-9dfa381b-0fce-4834-bbf8-a09da5c48751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
00623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1091000623
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.656529571
Short name T237
Test name
Test status
Simulation time 153771052 ps
CPU time 10.7 seconds
Started Jun 25 07:13:26 PM PDT 24
Finished Jun 25 07:13:46 PM PDT 24
Peak memory 248848 kb
Host smart-55c7d250-7edb-46f3-b259-f88ecaf0c3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65652
9571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.656529571
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2535471844
Short name T48
Test name
Test status
Simulation time 2217662258 ps
CPU time 35.06 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 07:14:12 PM PDT 24
Peak memory 257580 kb
Host smart-cbea0562-25bf-4e50-94a6-a03c47879821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25354
71844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2535471844
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4268709333
Short name T108
Test name
Test status
Simulation time 16568546459 ps
CPU time 1751.97 seconds
Started Jun 25 07:13:27 PM PDT 24
Finished Jun 25 07:42:49 PM PDT 24
Peak memory 290524 kb
Host smart-70828c3c-65ba-4cd7-940c-cec89ef0c5e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268709333 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4268709333
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3689000714
Short name T99
Test name
Test status
Simulation time 71830600208 ps
CPU time 1612.88 seconds
Started Jun 25 07:13:34 PM PDT 24
Finished Jun 25 07:40:39 PM PDT 24
Peak memory 284868 kb
Host smart-7bbc5bde-f8cb-470a-86f0-87b5e88403b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689000714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3689000714
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3140822837
Short name T219
Test name
Test status
Simulation time 3893106607 ps
CPU time 169.26 seconds
Started Jun 25 07:13:34 PM PDT 24
Finished Jun 25 07:16:34 PM PDT 24
Peak memory 252544 kb
Host smart-3e829618-d154-4852-8428-67c2e52741e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31408
22837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3140822837
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3323561173
Short name T693
Test name
Test status
Simulation time 444373987 ps
CPU time 16.87 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 07:14:02 PM PDT 24
Peak memory 256964 kb
Host smart-0526ca84-4aea-433e-a748-da35990c5f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
61173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3323561173
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1734706883
Short name T284
Test name
Test status
Simulation time 9189104355 ps
CPU time 914.47 seconds
Started Jun 25 07:13:31 PM PDT 24
Finished Jun 25 07:28:56 PM PDT 24
Peak memory 274112 kb
Host smart-ed894afd-3c86-4740-83aa-b836ebf9b12d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734706883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1734706883
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1031413034
Short name T487
Test name
Test status
Simulation time 157213697814 ps
CPU time 2735.08 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 07:59:22 PM PDT 24
Peak memory 290324 kb
Host smart-71a8badb-9224-47bb-ab8c-6c2005f0eafb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031413034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1031413034
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2805203159
Short name T681
Test name
Test status
Simulation time 46442656492 ps
CPU time 269.78 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:18:08 PM PDT 24
Peak memory 249220 kb
Host smart-4fff79a9-a0a1-453d-a5a1-a890e8eb90a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805203159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2805203159
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1766798317
Short name T614
Test name
Test status
Simulation time 681521283 ps
CPU time 41.68 seconds
Started Jun 25 07:13:29 PM PDT 24
Finished Jun 25 07:14:20 PM PDT 24
Peak memory 256756 kb
Host smart-45470057-5d05-405d-99a5-f10fec183d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
98317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1766798317
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1543649029
Short name T101
Test name
Test status
Simulation time 753138968 ps
CPU time 14.11 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 07:14:01 PM PDT 24
Peak memory 256016 kb
Host smart-e1484505-d8bb-40f4-bf49-8d3c791a741c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
49029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1543649029
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.131722195
Short name T269
Test name
Test status
Simulation time 243220121 ps
CPU time 21.1 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 07:13:59 PM PDT 24
Peak memory 248784 kb
Host smart-9958f693-8cac-4c0d-8301-59fd39afb05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172
2195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.131722195
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1707556299
Short name T613
Test name
Test status
Simulation time 59467548 ps
CPU time 4.99 seconds
Started Jun 25 07:13:28 PM PDT 24
Finished Jun 25 07:13:43 PM PDT 24
Peak memory 241032 kb
Host smart-6f52aa18-b312-4f27-9170-108c183b7c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
56299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1707556299
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3145815173
Short name T379
Test name
Test status
Simulation time 2759281995 ps
CPU time 61.86 seconds
Started Jun 25 07:13:30 PM PDT 24
Finished Jun 25 07:14:42 PM PDT 24
Peak memory 257844 kb
Host smart-01057910-3cb9-4eb7-bd15-9870b3388142
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145815173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3145815173
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2368736880
Short name T197
Test name
Test status
Simulation time 20869480 ps
CPU time 2.16 seconds
Started Jun 25 07:13:45 PM PDT 24
Finished Jun 25 07:13:58 PM PDT 24
Peak memory 249608 kb
Host smart-c910c9b1-6946-4468-a408-b7abee2f1c9c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2368736880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2368736880
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2224261802
Short name T439
Test name
Test status
Simulation time 20297626345 ps
CPU time 1211.39 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:34:06 PM PDT 24
Peak memory 265740 kb
Host smart-ef0bb060-c60c-4f70-8754-67967b2d76a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224261802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2224261802
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1087037843
Short name T449
Test name
Test status
Simulation time 106333581 ps
CPU time 7.75 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:14:03 PM PDT 24
Peak memory 249284 kb
Host smart-fa163ba1-d88f-4595-b246-1e92ed3b6add
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1087037843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1087037843
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2687760624
Short name T678
Test name
Test status
Simulation time 4848713222 ps
CPU time 150.19 seconds
Started Jun 25 07:13:40 PM PDT 24
Finished Jun 25 07:16:21 PM PDT 24
Peak memory 257620 kb
Host smart-2d1639f8-5593-4c18-9aef-f2c8a6f77b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26877
60624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2687760624
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1154134386
Short name T462
Test name
Test status
Simulation time 569949901 ps
CPU time 19.13 seconds
Started Jun 25 07:13:39 PM PDT 24
Finished Jun 25 07:14:09 PM PDT 24
Peak memory 257144 kb
Host smart-a5194177-f890-4090-909c-58c4b1c4da82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
34386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1154134386
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2289591908
Short name T244
Test name
Test status
Simulation time 42613373198 ps
CPU time 1427.9 seconds
Started Jun 25 07:13:38 PM PDT 24
Finished Jun 25 07:37:37 PM PDT 24
Peak memory 273356 kb
Host smart-e8bdb0eb-0f9c-406c-8c94-9901b75ffd7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289591908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2289591908
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3553468858
Short name T221
Test name
Test status
Simulation time 36591508355 ps
CPU time 1270.36 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:35:10 PM PDT 24
Peak memory 273396 kb
Host smart-47ea3c92-d7bf-4896-abd9-7ae9bd9b500f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553468858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3553468858
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3184942117
Short name T363
Test name
Test status
Simulation time 637825925 ps
CPU time 26.43 seconds
Started Jun 25 07:13:37 PM PDT 24
Finished Jun 25 07:14:15 PM PDT 24
Peak memory 256692 kb
Host smart-3fcb248b-3fca-423f-854f-94e2ce0ba527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
42117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3184942117
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.940934581
Short name T558
Test name
Test status
Simulation time 2824738872 ps
CPU time 57.71 seconds
Started Jun 25 07:13:37 PM PDT 24
Finished Jun 25 07:14:47 PM PDT 24
Peak memory 257368 kb
Host smart-36c96b13-2bce-4801-9d29-dc3375751982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94093
4581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.940934581
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1294169864
Short name T628
Test name
Test status
Simulation time 10702085618 ps
CPU time 43.85 seconds
Started Jun 25 07:13:37 PM PDT 24
Finished Jun 25 07:14:33 PM PDT 24
Peak memory 249416 kb
Host smart-99460827-3706-4562-96a7-bf0ef3b26efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
69864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1294169864
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.678194694
Short name T394
Test name
Test status
Simulation time 1786426415 ps
CPU time 29.74 seconds
Started Jun 25 07:13:35 PM PDT 24
Finished Jun 25 07:14:16 PM PDT 24
Peak memory 255808 kb
Host smart-8b387675-29ac-447c-85b1-e0a6e897a152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67819
4694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.678194694
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1427029846
Short name T654
Test name
Test status
Simulation time 5501458918 ps
CPU time 155.84 seconds
Started Jun 25 07:13:46 PM PDT 24
Finished Jun 25 07:16:33 PM PDT 24
Peak memory 257632 kb
Host smart-a7d1f900-71d1-418c-b514-fc4d4ec4118d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427029846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1427029846
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2595767420
Short name T201
Test name
Test status
Simulation time 47600214 ps
CPU time 3.88 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:13:58 PM PDT 24
Peak memory 249540 kb
Host smart-436bb025-4d82-4f42-89dc-81d4606b35c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2595767420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2595767420
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1056636043
Short name T54
Test name
Test status
Simulation time 114741833597 ps
CPU time 3559.47 seconds
Started Jun 25 07:13:39 PM PDT 24
Finished Jun 25 08:13:10 PM PDT 24
Peak memory 290300 kb
Host smart-52fde899-ee75-490b-a330-0e0af9c7d743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056636043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1056636043
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.464436275
Short name T583
Test name
Test status
Simulation time 1328200929 ps
CPU time 32.96 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:14:31 PM PDT 24
Peak memory 249208 kb
Host smart-6293d1a4-205e-4f6f-ad18-2b30e1ff4064
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=464436275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.464436275
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.73026988
Short name T396
Test name
Test status
Simulation time 815224582 ps
CPU time 79.11 seconds
Started Jun 25 07:13:36 PM PDT 24
Finished Jun 25 07:15:07 PM PDT 24
Peak memory 250312 kb
Host smart-f098ba69-c69b-42b2-8207-fe5446bb9adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73026
988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.73026988
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.483953531
Short name T542
Test name
Test status
Simulation time 2410109433 ps
CPU time 32.27 seconds
Started Jun 25 07:13:41 PM PDT 24
Finished Jun 25 07:14:24 PM PDT 24
Peak memory 249984 kb
Host smart-d3986dab-9fa8-45bf-a9b4-579e25bd6dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48395
3531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.483953531
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3506381530
Short name T367
Test name
Test status
Simulation time 159217126757 ps
CPU time 2549.39 seconds
Started Jun 25 07:13:40 PM PDT 24
Finished Jun 25 07:56:21 PM PDT 24
Peak memory 285052 kb
Host smart-c07b2a63-f6cc-4290-986d-df3c1d7ba0ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506381530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3506381530
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3331071269
Short name T629
Test name
Test status
Simulation time 474663325 ps
CPU time 15.08 seconds
Started Jun 25 07:13:38 PM PDT 24
Finished Jun 25 07:14:05 PM PDT 24
Peak memory 249328 kb
Host smart-e4a7a214-78fc-43e3-9992-bde759f3ba2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
71269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3331071269
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4059461918
Short name T544
Test name
Test status
Simulation time 311602442 ps
CPU time 12.32 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:14:06 PM PDT 24
Peak memory 254080 kb
Host smart-7ab87fd7-3ef1-43f1-9846-212cc41a85aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
61918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4059461918
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2486261004
Short name T641
Test name
Test status
Simulation time 222262109 ps
CPU time 4.85 seconds
Started Jun 25 07:13:44 PM PDT 24
Finished Jun 25 07:14:00 PM PDT 24
Peak memory 241120 kb
Host smart-8665fdae-6c63-494e-981d-48619ec21571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24862
61004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2486261004
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2103859928
Short name T536
Test name
Test status
Simulation time 514497414 ps
CPU time 25.03 seconds
Started Jun 25 07:13:46 PM PDT 24
Finished Jun 25 07:14:22 PM PDT 24
Peak memory 257456 kb
Host smart-5010c880-5f5a-4e7d-ae11-2dc06a25de43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
59928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2103859928
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3579489065
Short name T213
Test name
Test status
Simulation time 122123288889 ps
CPU time 596.12 seconds
Started Jun 25 07:13:36 PM PDT 24
Finished Jun 25 07:23:44 PM PDT 24
Peak memory 265760 kb
Host smart-ae6716e6-b0c7-4a0a-9c9c-5c9869c5bb5e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579489065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3579489065
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.803157273
Short name T210
Test name
Test status
Simulation time 113103779 ps
CPU time 3.17 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:14:01 PM PDT 24
Peak memory 249608 kb
Host smart-36943b31-9a6b-4b77-ba86-2b6f9e4b317c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=803157273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.803157273
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2868483245
Short name T527
Test name
Test status
Simulation time 57642297212 ps
CPU time 867.21 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:28:25 PM PDT 24
Peak memory 272056 kb
Host smart-262ebab3-c6ce-47fa-b97d-899e039a67cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868483245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2868483245
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1623164950
Short name T424
Test name
Test status
Simulation time 7084765026 ps
CPU time 73.22 seconds
Started Jun 25 07:13:45 PM PDT 24
Finished Jun 25 07:15:09 PM PDT 24
Peak memory 249404 kb
Host smart-4ee61584-c0eb-4118-9983-c62933b09360
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1623164950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1623164950
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3643025817
Short name T413
Test name
Test status
Simulation time 6225380003 ps
CPU time 123.8 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:16:01 PM PDT 24
Peak memory 256888 kb
Host smart-c00ecf18-6ef2-4ce2-bbc3-f7c9e0d86b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36430
25817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3643025817
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2028687348
Short name T508
Test name
Test status
Simulation time 239780724 ps
CPU time 5.94 seconds
Started Jun 25 07:13:50 PM PDT 24
Finished Jun 25 07:14:06 PM PDT 24
Peak memory 248852 kb
Host smart-ed9fab46-f505-4a88-bef2-6a190b367235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
87348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2028687348
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2833603380
Short name T698
Test name
Test status
Simulation time 106895674675 ps
CPU time 1584.39 seconds
Started Jun 25 07:13:41 PM PDT 24
Finished Jun 25 07:40:17 PM PDT 24
Peak memory 273872 kb
Host smart-8669e9dd-4002-4d23-8320-6268acd45070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833603380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2833603380
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1619350885
Short name T615
Test name
Test status
Simulation time 41378871196 ps
CPU time 2683.84 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:58:39 PM PDT 24
Peak memory 289372 kb
Host smart-7ff82ea9-6232-4919-8b91-b43c74c09d1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619350885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1619350885
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1894552744
Short name T595
Test name
Test status
Simulation time 47721719439 ps
CPU time 477.38 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:21:56 PM PDT 24
Peak memory 249384 kb
Host smart-4749f678-c4e3-48d4-99b9-f68db71f1dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894552744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1894552744
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.536801411
Short name T385
Test name
Test status
Simulation time 130905575 ps
CPU time 10.04 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:14:08 PM PDT 24
Peak memory 249272 kb
Host smart-bd7947b4-b6a1-4437-ba10-476aefe6161e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53680
1411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.536801411
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3562937080
Short name T636
Test name
Test status
Simulation time 1572209601 ps
CPU time 10.92 seconds
Started Jun 25 07:13:41 PM PDT 24
Finished Jun 25 07:14:03 PM PDT 24
Peak memory 248696 kb
Host smart-fa429431-9ffd-4ab7-854a-5ab166bea30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35629
37080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3562937080
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3125593737
Short name T346
Test name
Test status
Simulation time 1776623229 ps
CPU time 46.26 seconds
Started Jun 25 07:13:37 PM PDT 24
Finished Jun 25 07:14:35 PM PDT 24
Peak memory 257512 kb
Host smart-e903397b-feb2-4445-adc7-3f1d4b754fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31255
93737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3125593737
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4064451620
Short name T384
Test name
Test status
Simulation time 713217522 ps
CPU time 37.22 seconds
Started Jun 25 07:13:43 PM PDT 24
Finished Jun 25 07:14:32 PM PDT 24
Peak memory 249300 kb
Host smart-ac08d233-d220-480a-ab0a-7a1fe7c8538d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40644
51620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4064451620
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2108291741
Short name T247
Test name
Test status
Simulation time 15588955879 ps
CPU time 1753.57 seconds
Started Jun 25 07:13:47 PM PDT 24
Finished Jun 25 07:43:11 PM PDT 24
Peak memory 290440 kb
Host smart-b6ad0a6d-37fe-4e04-96d8-95a30df0eea2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108291741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2108291741
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4085379409
Short name T192
Test name
Test status
Simulation time 48532343 ps
CPU time 4.67 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:14:04 PM PDT 24
Peak memory 249612 kb
Host smart-17cbcbb9-7467-4e6a-8099-5fbdb9fa1958
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4085379409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4085379409
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2708167360
Short name T549
Test name
Test status
Simulation time 84114306393 ps
CPU time 1470.81 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:38:30 PM PDT 24
Peak memory 273600 kb
Host smart-98e71541-7129-435c-a014-e370df27b233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708167360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2708167360
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2454886949
Short name T560
Test name
Test status
Simulation time 1047212150 ps
CPU time 10.43 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:14:09 PM PDT 24
Peak memory 249224 kb
Host smart-9aed5e5d-62ea-42e0-9798-cb029f9143ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2454886949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2454886949
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.82715268
Short name T253
Test name
Test status
Simulation time 1887779404 ps
CPU time 117.67 seconds
Started Jun 25 07:13:52 PM PDT 24
Finished Jun 25 07:16:00 PM PDT 24
Peak memory 257016 kb
Host smart-b309e2ff-b532-4fca-93db-681fd86663f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82715
268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.82715268
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2822039162
Short name T83
Test name
Test status
Simulation time 1264870249 ps
CPU time 66.09 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:15:06 PM PDT 24
Peak memory 257040 kb
Host smart-6214149e-67d7-44b3-8966-726bb754c21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
39162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2822039162
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3432562411
Short name T307
Test name
Test status
Simulation time 44047133647 ps
CPU time 884.34 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:28:42 PM PDT 24
Peak memory 273152 kb
Host smart-1f33a3f1-cafc-4d5b-99aa-e71c72d7f278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432562411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3432562411
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3393110369
Short name T545
Test name
Test status
Simulation time 5542866860 ps
CPU time 641.28 seconds
Started Jun 25 07:13:50 PM PDT 24
Finished Jun 25 07:24:41 PM PDT 24
Peak memory 273432 kb
Host smart-2a0e724c-0c5b-4a0f-9211-20d0b041d738
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393110369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3393110369
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.843621012
Short name T296
Test name
Test status
Simulation time 9225435884 ps
CPU time 110.89 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:15:50 PM PDT 24
Peak memory 255884 kb
Host smart-3f25ef67-17a9-4d24-953b-d57c7f74479e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843621012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.843621012
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4085357110
Short name T249
Test name
Test status
Simulation time 465836743 ps
CPU time 17.84 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:14:17 PM PDT 24
Peak memory 249244 kb
Host smart-0dff0139-99ab-42d0-9ea6-ecb7f7b3d6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40853
57110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4085357110
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2049493944
Short name T438
Test name
Test status
Simulation time 292177840 ps
CPU time 11.53 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:14:10 PM PDT 24
Peak memory 248840 kb
Host smart-bc4b198a-d4b2-4982-b299-58472b32cf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494
93944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2049493944
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1964321367
Short name T378
Test name
Test status
Simulation time 185992208 ps
CPU time 7.33 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:14:05 PM PDT 24
Peak memory 248836 kb
Host smart-57d2e1eb-1bf6-4d60-8bd5-a7ad74978b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
21367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1964321367
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4134762688
Short name T667
Test name
Test status
Simulation time 170407214 ps
CPU time 6.94 seconds
Started Jun 25 07:13:47 PM PDT 24
Finished Jun 25 07:14:04 PM PDT 24
Peak memory 253264 kb
Host smart-d4c8e5c9-1625-4041-bb40-e3f9d2af46bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41347
62688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4134762688
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2232323716
Short name T43
Test name
Test status
Simulation time 64224828898 ps
CPU time 1810.98 seconds
Started Jun 25 07:13:48 PM PDT 24
Finished Jun 25 07:44:09 PM PDT 24
Peak memory 297988 kb
Host smart-08c48a19-2a1d-4297-a02e-9e8397ca4242
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232323716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2232323716
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.970351443
Short name T193
Test name
Test status
Simulation time 176047892 ps
CPU time 3 seconds
Started Jun 25 07:14:00 PM PDT 24
Finished Jun 25 07:14:11 PM PDT 24
Peak memory 249608 kb
Host smart-3eab5f3c-dbb4-468d-8d64-b0f0fd8a0282
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=970351443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.970351443
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.4293721461
Short name T589
Test name
Test status
Simulation time 84843402340 ps
CPU time 1345.64 seconds
Started Jun 25 07:13:52 PM PDT 24
Finished Jun 25 07:36:28 PM PDT 24
Peak memory 269744 kb
Host smart-a5274d51-c374-47a7-b85e-0ba6144db50c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293721461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.4293721461
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3892666648
Short name T223
Test name
Test status
Simulation time 377358202 ps
CPU time 13.08 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 07:14:20 PM PDT 24
Peak memory 249240 kb
Host smart-a94f04e9-d485-4184-909d-649039ab868d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3892666648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3892666648
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3019660852
Short name T20
Test name
Test status
Simulation time 51495324284 ps
CPU time 277.36 seconds
Started Jun 25 07:13:46 PM PDT 24
Finished Jun 25 07:18:34 PM PDT 24
Peak memory 257556 kb
Host smart-25be30b2-670f-491e-bad9-8045e99b0242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30196
60852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3019660852
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.201738051
Short name T519
Test name
Test status
Simulation time 596483645 ps
CPU time 24.09 seconds
Started Jun 25 07:13:50 PM PDT 24
Finished Jun 25 07:14:24 PM PDT 24
Peak memory 248912 kb
Host smart-49d2066c-df32-4f78-8aa9-98b882518f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
8051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.201738051
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.608380931
Short name T315
Test name
Test status
Simulation time 44644705687 ps
CPU time 2697.36 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 07:59:04 PM PDT 24
Peak memory 282540 kb
Host smart-680f8cf9-cdff-4940-babf-2cb150d66dbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608380931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.608380931
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3030174510
Short name T373
Test name
Test status
Simulation time 38684041936 ps
CPU time 2850.66 seconds
Started Jun 25 07:14:00 PM PDT 24
Finished Jun 25 08:01:40 PM PDT 24
Peak memory 290172 kb
Host smart-6d42b8e1-62e9-4b9f-a0e2-fbfdcf7ad618
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030174510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3030174510
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.341344306
Short name T224
Test name
Test status
Simulation time 9773655567 ps
CPU time 396.71 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 07:20:44 PM PDT 24
Peak memory 249416 kb
Host smart-e3bb8038-ec27-4ee4-9a92-637ed4a70835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341344306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.341344306
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2379403756
Short name T523
Test name
Test status
Simulation time 1927637643 ps
CPU time 42 seconds
Started Jun 25 07:13:52 PM PDT 24
Finished Jun 25 07:14:43 PM PDT 24
Peak memory 256684 kb
Host smart-c1eea7c3-bbe0-4013-b309-ebcbe9a1f91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
03756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2379403756
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2337017288
Short name T30
Test name
Test status
Simulation time 2435297870 ps
CPU time 65.39 seconds
Started Jun 25 07:13:53 PM PDT 24
Finished Jun 25 07:15:08 PM PDT 24
Peak memory 250336 kb
Host smart-0ba5b868-dd27-4efe-a1fd-7bfd1b1a17e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23370
17288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2337017288
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.998190754
Short name T241
Test name
Test status
Simulation time 9342297347 ps
CPU time 34.56 seconds
Started Jun 25 07:13:49 PM PDT 24
Finished Jun 25 07:14:33 PM PDT 24
Peak memory 249460 kb
Host smart-f986803b-1281-45fc-9803-0e640d4a35c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99819
0754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.998190754
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3437041687
Short name T479
Test name
Test status
Simulation time 396735045 ps
CPU time 19.77 seconds
Started Jun 25 07:13:52 PM PDT 24
Finished Jun 25 07:14:22 PM PDT 24
Peak memory 249216 kb
Host smart-5c043f9f-4486-480d-8e44-94194a31d3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34370
41687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3437041687
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2679423765
Short name T273
Test name
Test status
Simulation time 13726316008 ps
CPU time 961.72 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 07:30:09 PM PDT 24
Peak memory 272324 kb
Host smart-42ab357d-c862-4b44-b88d-0dcae2ab254c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679423765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2679423765
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.339258387
Short name T194
Test name
Test status
Simulation time 20374223 ps
CPU time 3.04 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 07:14:11 PM PDT 24
Peak memory 249636 kb
Host smart-84f47884-93d6-40b5-a570-fdd89fe8a892
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339258387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.339258387
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1093921389
Short name T663
Test name
Test status
Simulation time 169283387 ps
CPU time 9.62 seconds
Started Jun 25 07:13:59 PM PDT 24
Finished Jun 25 07:14:18 PM PDT 24
Peak memory 249368 kb
Host smart-317f03fd-214e-458a-a160-9a3b06e6596d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1093921389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1093921389
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.287149257
Short name T594
Test name
Test status
Simulation time 19533670743 ps
CPU time 268.15 seconds
Started Jun 25 07:14:00 PM PDT 24
Finished Jun 25 07:18:37 PM PDT 24
Peak memory 252440 kb
Host smart-ee336f43-0b2b-4ee8-a5a7-18d368f00ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28714
9257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.287149257
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2257378039
Short name T562
Test name
Test status
Simulation time 234061377 ps
CPU time 6.3 seconds
Started Jun 25 07:13:59 PM PDT 24
Finished Jun 25 07:14:15 PM PDT 24
Peak memory 249808 kb
Host smart-c5d903aa-ed56-452b-b57b-aeb1eca66f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22573
78039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2257378039
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2894561735
Short name T657
Test name
Test status
Simulation time 264828486214 ps
CPU time 3560.82 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 08:13:29 PM PDT 24
Peak memory 289656 kb
Host smart-45d72613-1269-4ad6-ac58-97ceac0fec08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894561735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2894561735
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.269444905
Short name T620
Test name
Test status
Simulation time 5114064895 ps
CPU time 616.4 seconds
Started Jun 25 07:14:00 PM PDT 24
Finished Jun 25 07:24:25 PM PDT 24
Peak memory 273892 kb
Host smart-3317cf39-57d5-4a0c-b651-374eb0bc6d77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269444905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.269444905
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1028637677
Short name T701
Test name
Test status
Simulation time 20393227796 ps
CPU time 193.7 seconds
Started Jun 25 07:13:59 PM PDT 24
Finished Jun 25 07:17:22 PM PDT 24
Peak memory 249412 kb
Host smart-00341c25-7fa4-4bc5-a4d1-894cd195d952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028637677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1028637677
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3085348687
Short name T547
Test name
Test status
Simulation time 1564747961 ps
CPU time 43.58 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 07:14:52 PM PDT 24
Peak memory 249356 kb
Host smart-b3538efe-2fa1-4a8a-bcb5-61b6235249f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
48687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3085348687
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1234716487
Short name T582
Test name
Test status
Simulation time 362730262 ps
CPU time 33.32 seconds
Started Jun 25 07:13:59 PM PDT 24
Finished Jun 25 07:14:41 PM PDT 24
Peak memory 248360 kb
Host smart-73ecd5b9-8ba3-4b4f-ac86-ea33b64d4fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12347
16487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1234716487
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2464397979
Short name T469
Test name
Test status
Simulation time 364408078 ps
CPU time 12.21 seconds
Started Jun 25 07:14:00 PM PDT 24
Finished Jun 25 07:14:21 PM PDT 24
Peak memory 248664 kb
Host smart-15c536e8-3576-482e-a6b1-61f39085e5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24643
97979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2464397979
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3903218184
Short name T610
Test name
Test status
Simulation time 309542776 ps
CPU time 25.93 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 07:14:32 PM PDT 24
Peak memory 249236 kb
Host smart-04f6d51f-9797-416a-baee-f2274a20c28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39032
18184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3903218184
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.633525047
Short name T17
Test name
Test status
Simulation time 895232541798 ps
CPU time 3717.27 seconds
Started Jun 25 07:13:59 PM PDT 24
Finished Jun 25 08:16:06 PM PDT 24
Peak memory 289868 kb
Host smart-c21be2a3-7b0b-4c9d-9d86-c92b7ddd7001
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633525047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.633525047
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.16290384
Short name T233
Test name
Test status
Simulation time 756797854860 ps
CPU time 8133.47 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 09:29:41 PM PDT 24
Peak memory 395604 kb
Host smart-0d315b34-eaed-4be2-821d-0b1e3d6ed7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290384 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.16290384
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2061666307
Short name T202
Test name
Test status
Simulation time 79820967 ps
CPU time 2.29 seconds
Started Jun 25 07:12:36 PM PDT 24
Finished Jun 25 07:13:01 PM PDT 24
Peak memory 249552 kb
Host smart-d800147a-6351-4073-a090-e45035ad3c38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2061666307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2061666307
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3638698766
Short name T612
Test name
Test status
Simulation time 179907369224 ps
CPU time 2545.04 seconds
Started Jun 25 07:12:29 PM PDT 24
Finished Jun 25 07:55:18 PM PDT 24
Peak memory 290048 kb
Host smart-9c5e8aaf-ba00-4f2c-bfd5-3af344f2a5ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638698766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3638698766
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2846892486
Short name T113
Test name
Test status
Simulation time 143303703 ps
CPU time 10.46 seconds
Started Jun 25 07:12:33 PM PDT 24
Finished Jun 25 07:13:08 PM PDT 24
Peak memory 249300 kb
Host smart-68b0ea8b-5f04-4efe-b9fb-b2ff0697ec08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2846892486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2846892486
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.976565046
Short name T415
Test name
Test status
Simulation time 928877495 ps
CPU time 80.2 seconds
Started Jun 25 07:12:36 PM PDT 24
Finished Jun 25 07:14:19 PM PDT 24
Peak memory 257512 kb
Host smart-1c581595-0d4a-45d4-9753-2c97bec37898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97656
5046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.976565046
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.493369262
Short name T676
Test name
Test status
Simulation time 2449257515 ps
CPU time 38.42 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 07:13:30 PM PDT 24
Peak memory 249044 kb
Host smart-40ad4838-49d5-4bc4-aeed-0579d4ad772d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49336
9262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.493369262
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2054266505
Short name T5
Test name
Test status
Simulation time 17399288647 ps
CPU time 191.37 seconds
Started Jun 25 07:12:32 PM PDT 24
Finished Jun 25 07:16:06 PM PDT 24
Peak memory 249164 kb
Host smart-060e10c0-4eab-418d-a13d-82fcf16532e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054266505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2054266505
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1407110167
Short name T528
Test name
Test status
Simulation time 27639898 ps
CPU time 3.69 seconds
Started Jun 25 07:12:27 PM PDT 24
Finished Jun 25 07:12:55 PM PDT 24
Peak memory 249316 kb
Host smart-c55ed5cc-7177-43c8-8b31-d23cc92a23f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
10167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1407110167
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2586327913
Short name T683
Test name
Test status
Simulation time 34381665 ps
CPU time 3.52 seconds
Started Jun 25 07:12:27 PM PDT 24
Finished Jun 25 07:12:55 PM PDT 24
Peak memory 241124 kb
Host smart-99cb74a2-5683-45cd-997a-5d0483ffc12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25863
27913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2586327913
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4277328455
Short name T12
Test name
Test status
Simulation time 470322834 ps
CPU time 13.92 seconds
Started Jun 25 07:12:27 PM PDT 24
Finished Jun 25 07:13:05 PM PDT 24
Peak memory 271416 kb
Host smart-1c14180d-34e5-476f-81d9-15cb42f69082
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4277328455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4277328455
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.440646443
Short name T87
Test name
Test status
Simulation time 862975873 ps
CPU time 28.77 seconds
Started Jun 25 07:12:33 PM PDT 24
Finished Jun 25 07:13:26 PM PDT 24
Peak memory 256456 kb
Host smart-2637d294-dc9d-47dd-b4ee-afa463878c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44064
6443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.440646443
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2023516652
Short name T618
Test name
Test status
Simulation time 1430991569 ps
CPU time 29.26 seconds
Started Jun 25 07:12:31 PM PDT 24
Finished Jun 25 07:13:24 PM PDT 24
Peak memory 257092 kb
Host smart-49673d1d-95f4-475f-8ffb-2aa671f5042d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20235
16652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2023516652
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2817472862
Short name T671
Test name
Test status
Simulation time 102890536228 ps
CPU time 2204.59 seconds
Started Jun 25 07:12:29 PM PDT 24
Finished Jun 25 07:49:38 PM PDT 24
Peak memory 290296 kb
Host smart-36e7c94d-f425-4cd8-a14c-d003244aed6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817472862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2817472862
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.49241033
Short name T510
Test name
Test status
Simulation time 68021322034 ps
CPU time 5755.86 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 08:48:50 PM PDT 24
Peak memory 338944 kb
Host smart-d138fefa-b370-4166-b864-fdda9a0cfca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49241033 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.49241033
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4186381804
Short name T607
Test name
Test status
Simulation time 248743863071 ps
CPU time 2281.1 seconds
Started Jun 25 07:14:13 PM PDT 24
Finished Jun 25 07:52:24 PM PDT 24
Peak memory 285788 kb
Host smart-124a7fb9-f532-4715-95f8-31aa6b8351c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186381804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4186381804
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4258369692
Short name T428
Test name
Test status
Simulation time 1753013133 ps
CPU time 45.59 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:15:02 PM PDT 24
Peak memory 257020 kb
Host smart-5b24b8c3-1a1a-4ca1-abf2-3cd93234d961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42583
69692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4258369692
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2948049649
Short name T665
Test name
Test status
Simulation time 877337496 ps
CPU time 30.86 seconds
Started Jun 25 07:14:14 PM PDT 24
Finished Jun 25 07:14:54 PM PDT 24
Peak memory 257036 kb
Host smart-f0772c31-d8b9-4f50-8bca-a2ff9ebc4f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
49649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2948049649
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3689769740
Short name T319
Test name
Test status
Simulation time 257992418607 ps
CPU time 1778.59 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:43:56 PM PDT 24
Peak memory 273948 kb
Host smart-3a1f40f6-e537-4321-9c81-4a8f1e624559
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689769740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3689769740
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3973239989
Short name T652
Test name
Test status
Simulation time 50218541588 ps
CPU time 1750.59 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:43:29 PM PDT 24
Peak memory 284776 kb
Host smart-c7b7109d-90d8-456f-a47f-d32ce4746495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973239989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3973239989
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2001178189
Short name T532
Test name
Test status
Simulation time 273913620 ps
CPU time 21.12 seconds
Started Jun 25 07:13:58 PM PDT 24
Finished Jun 25 07:14:29 PM PDT 24
Peak memory 256580 kb
Host smart-5c271b47-030c-4ed9-9afb-0e196ac5b69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
78189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2001178189
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3821446370
Short name T426
Test name
Test status
Simulation time 94296635 ps
CPU time 6.53 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:14:24 PM PDT 24
Peak memory 253828 kb
Host smart-1cab0c5e-737c-488e-80ee-96fc736377c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38214
46370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3821446370
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2039108594
Short name T687
Test name
Test status
Simulation time 415015728 ps
CPU time 26.04 seconds
Started Jun 25 07:13:57 PM PDT 24
Finished Jun 25 07:14:32 PM PDT 24
Peak memory 256952 kb
Host smart-dfc7812d-00d8-4dc1-a2dd-bf713fabff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20391
08594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2039108594
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4096280987
Short name T107
Test name
Test status
Simulation time 12550780438 ps
CPU time 1557.79 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:40:16 PM PDT 24
Peak memory 289612 kb
Host smart-6a7ae8ef-66c6-4a87-9cb1-8e3e7270948a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096280987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4096280987
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.880062193
Short name T190
Test name
Test status
Simulation time 311585014353 ps
CPU time 4125.32 seconds
Started Jun 25 07:14:07 PM PDT 24
Finished Jun 25 08:23:01 PM PDT 24
Peak memory 338784 kb
Host smart-8000ab4b-30e2-4795-9d70-f2d4f6f93b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880062193 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.880062193
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.858122347
Short name T451
Test name
Test status
Simulation time 15879236089 ps
CPU time 1120.57 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:32:56 PM PDT 24
Peak memory 286952 kb
Host smart-a8d51c32-35dc-436f-adec-a5af1f25bb1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858122347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.858122347
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3019708729
Short name T18
Test name
Test status
Simulation time 2723067904 ps
CPU time 56.76 seconds
Started Jun 25 07:14:14 PM PDT 24
Finished Jun 25 07:15:19 PM PDT 24
Peak memory 257620 kb
Host smart-e0e81827-9edc-4284-83ce-e6b8397fdc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
08729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3019708729
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.609039837
Short name T457
Test name
Test status
Simulation time 1266977567 ps
CPU time 72.24 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:15:28 PM PDT 24
Peak memory 249224 kb
Host smart-69e6c721-c663-4b0c-bb7e-da52e2a7b2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60903
9837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.609039837
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3552791170
Short name T39
Test name
Test status
Simulation time 18650831128 ps
CPU time 890.65 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:29:08 PM PDT 24
Peak memory 273408 kb
Host smart-5cf8cb3a-04dd-4f66-b2e0-4cd0e65ce933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552791170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3552791170
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2150682734
Short name T14
Test name
Test status
Simulation time 257484652425 ps
CPU time 2870.25 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 08:02:09 PM PDT 24
Peak memory 290216 kb
Host smart-bb471928-db7a-48db-bbbe-d1529bb92622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150682734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2150682734
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2989164411
Short name T288
Test name
Test status
Simulation time 80996537768 ps
CPU time 581.99 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:23:59 PM PDT 24
Peak memory 249436 kb
Host smart-691d2191-a059-4d48-a1f0-d97602de3636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989164411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2989164411
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2287979242
Short name T662
Test name
Test status
Simulation time 159656554 ps
CPU time 15.96 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:14:35 PM PDT 24
Peak memory 249348 kb
Host smart-f4dd7106-a05b-4f9f-bebe-eb18b5b1e344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
79242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2287979242
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2392079530
Short name T458
Test name
Test status
Simulation time 4583611555 ps
CPU time 54.91 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:15:10 PM PDT 24
Peak memory 257628 kb
Host smart-6b9a1e82-4ad5-4d73-9e29-f869d33481eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23920
79530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2392079530
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2342145347
Short name T111
Test name
Test status
Simulation time 1467463300 ps
CPU time 36.04 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:14:54 PM PDT 24
Peak memory 257004 kb
Host smart-67661468-eefb-43e9-8c72-6656db847dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
45347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2342145347
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3871670820
Short name T354
Test name
Test status
Simulation time 1416257472 ps
CPU time 22.1 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:14:40 PM PDT 24
Peak memory 255888 kb
Host smart-929faf1a-8844-436b-a44a-0865488cd1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38716
70820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3871670820
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2315858372
Short name T503
Test name
Test status
Simulation time 77578902311 ps
CPU time 2233.61 seconds
Started Jun 25 07:14:08 PM PDT 24
Finished Jun 25 07:51:29 PM PDT 24
Peak memory 284704 kb
Host smart-d50a644f-cb3e-4d03-9702-42e6c3605a22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315858372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2315858372
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2126352375
Short name T660
Test name
Test status
Simulation time 317361607600 ps
CPU time 3126.28 seconds
Started Jun 25 07:14:21 PM PDT 24
Finished Jun 25 08:06:36 PM PDT 24
Peak memory 289940 kb
Host smart-a408c2ab-bcd4-47c1-9491-4b0c9ac5c8aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126352375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2126352375
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.778892036
Short name T555
Test name
Test status
Simulation time 4762018360 ps
CPU time 109.05 seconds
Started Jun 25 07:14:13 PM PDT 24
Finished Jun 25 07:16:11 PM PDT 24
Peak memory 256740 kb
Host smart-9f0839b3-2db5-415a-8c10-3676c0169996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77889
2036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.778892036
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3255929784
Short name T459
Test name
Test status
Simulation time 301886132 ps
CPU time 19.83 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:14:36 PM PDT 24
Peak memory 248896 kb
Host smart-1015bf7d-9bf6-4b78-8a68-fe94f3631b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
29784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3255929784
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2863790714
Short name T106
Test name
Test status
Simulation time 52626516354 ps
CPU time 3416.78 seconds
Started Jun 25 07:14:17 PM PDT 24
Finished Jun 25 08:11:22 PM PDT 24
Peak memory 287652 kb
Host smart-6460cdef-5749-48a9-9024-54155b188bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863790714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2863790714
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.963004502
Short name T421
Test name
Test status
Simulation time 667540095 ps
CPU time 47.24 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:15:06 PM PDT 24
Peak memory 256848 kb
Host smart-785132f4-7abd-4b56-86a8-063e846d1015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96300
4502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.963004502
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.115528223
Short name T89
Test name
Test status
Simulation time 5909884331 ps
CPU time 51.76 seconds
Started Jun 25 07:14:09 PM PDT 24
Finished Jun 25 07:15:09 PM PDT 24
Peak memory 249420 kb
Host smart-7139b385-2a3b-42f6-ac04-bd50985cf14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
8223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.115528223
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3353337637
Short name T517
Test name
Test status
Simulation time 272443622 ps
CPU time 39.03 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:15:07 PM PDT 24
Peak memory 248948 kb
Host smart-b696d692-1c6f-462b-a3e3-9ad9debc841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33533
37637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3353337637
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3728987044
Short name T689
Test name
Test status
Simulation time 1983224808 ps
CPU time 30.73 seconds
Started Jun 25 07:14:10 PM PDT 24
Finished Jun 25 07:14:49 PM PDT 24
Peak memory 257584 kb
Host smart-4b0fdac0-5b54-4d5e-8aed-48dbc36a0606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
87044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3728987044
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4196792261
Short name T688
Test name
Test status
Simulation time 61675658737 ps
CPU time 373.48 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:20:41 PM PDT 24
Peak memory 265880 kb
Host smart-50bbba71-3002-401d-b737-1e141abcad0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196792261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4196792261
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1348338940
Short name T117
Test name
Test status
Simulation time 27885087671 ps
CPU time 1126.56 seconds
Started Jun 25 07:14:18 PM PDT 24
Finished Jun 25 07:33:13 PM PDT 24
Peak memory 282180 kb
Host smart-60a92051-5252-4322-af7f-9f365c50ec7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348338940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1348338940
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3277903910
Short name T616
Test name
Test status
Simulation time 3642620425 ps
CPU time 191.06 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:17:39 PM PDT 24
Peak memory 257608 kb
Host smart-898c9ff4-eaef-47ed-8fbf-a16ff035a073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32779
03910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3277903910
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2457994608
Short name T380
Test name
Test status
Simulation time 196368665 ps
CPU time 12.33 seconds
Started Jun 25 07:14:18 PM PDT 24
Finished Jun 25 07:14:39 PM PDT 24
Peak memory 249256 kb
Host smart-0b34ed0a-bd0c-4793-aa26-e2673c888d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
94608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2457994608
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4036407069
Short name T575
Test name
Test status
Simulation time 8092273899 ps
CPU time 747.21 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:26:55 PM PDT 24
Peak memory 273000 kb
Host smart-a5429df2-4a93-4f9f-b48e-c00359cd26bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036407069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4036407069
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.735766686
Short name T596
Test name
Test status
Simulation time 39756839634 ps
CPU time 430.61 seconds
Started Jun 25 07:14:21 PM PDT 24
Finished Jun 25 07:21:40 PM PDT 24
Peak memory 256648 kb
Host smart-1ac9467f-faf7-49ee-9ae6-207c2afbf950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735766686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.735766686
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3608675266
Short name T650
Test name
Test status
Simulation time 744617883 ps
CPU time 5.05 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:14:32 PM PDT 24
Peak memory 249304 kb
Host smart-f7f27ce1-ede6-4e0c-9594-9697c64e31f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36086
75266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3608675266
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2525583651
Short name T476
Test name
Test status
Simulation time 245361771 ps
CPU time 17.44 seconds
Started Jun 25 07:14:20 PM PDT 24
Finished Jun 25 07:14:46 PM PDT 24
Peak memory 248592 kb
Host smart-29a5ecb5-0d24-4e5e-813a-43f4ad331847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
83651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2525583651
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4099896054
Short name T422
Test name
Test status
Simulation time 248249047 ps
CPU time 26.69 seconds
Started Jun 25 07:14:21 PM PDT 24
Finished Jun 25 07:14:56 PM PDT 24
Peak memory 256900 kb
Host smart-c9644b28-61f6-45e7-9e80-5401c18f54a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
96054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4099896054
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.568895885
Short name T73
Test name
Test status
Simulation time 1108565500 ps
CPU time 23.75 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:14:51 PM PDT 24
Peak memory 249328 kb
Host smart-52570a54-a0d0-4367-8bbe-18c9d56359da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56889
5885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.568895885
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3566976999
Short name T183
Test name
Test status
Simulation time 20240014517 ps
CPU time 2441.15 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:55:09 PM PDT 24
Peak memory 306468 kb
Host smart-c8f491ac-7430-4e7e-8540-63688d5ce45c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566976999 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3566976999
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2086048362
Short name T390
Test name
Test status
Simulation time 129096721074 ps
CPU time 2710.43 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 07:59:45 PM PDT 24
Peak memory 290308 kb
Host smart-d4908fbb-7877-4215-a4af-290262087772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086048362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2086048362
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1406981841
Short name T217
Test name
Test status
Simulation time 1165836852 ps
CPU time 72.78 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 07:15:47 PM PDT 24
Peak memory 249356 kb
Host smart-a4175689-b03a-4609-b6b9-3d2730bb500a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14069
81841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1406981841
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4031971897
Short name T571
Test name
Test status
Simulation time 614676848 ps
CPU time 17.62 seconds
Started Jun 25 07:14:30 PM PDT 24
Finished Jun 25 07:14:53 PM PDT 24
Peak memory 255920 kb
Host smart-c6dd1361-2d0e-4ffb-b944-6aec0af0c91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40319
71897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4031971897
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4121718928
Short name T328
Test name
Test status
Simulation time 189017382196 ps
CPU time 2834.14 seconds
Started Jun 25 07:14:31 PM PDT 24
Finished Jun 25 08:01:51 PM PDT 24
Peak memory 286404 kb
Host smart-6a5af01b-dde7-4796-87a5-6b5470cbf4da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121718928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4121718928
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1180905874
Short name T675
Test name
Test status
Simulation time 47238860846 ps
CPU time 3309.45 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 08:09:44 PM PDT 24
Peak memory 290268 kb
Host smart-44f36833-137d-4006-9613-a7c770afbbc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180905874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1180905874
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.219702272
Short name T120
Test name
Test status
Simulation time 82869927 ps
CPU time 7.83 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:14:35 PM PDT 24
Peak memory 249320 kb
Host smart-727e50b9-a87d-4830-bba9-da99da3d4db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970
2272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.219702272
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2656594085
Short name T399
Test name
Test status
Simulation time 2455703049 ps
CPU time 37.59 seconds
Started Jun 25 07:14:30 PM PDT 24
Finished Jun 25 07:15:13 PM PDT 24
Peak memory 249464 kb
Host smart-f1981af7-a241-482d-97c1-b8a14957c2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26565
94085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2656594085
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.859306702
Short name T275
Test name
Test status
Simulation time 821021668 ps
CPU time 51.9 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 07:15:26 PM PDT 24
Peak memory 250332 kb
Host smart-6f7f60db-4dbd-49a6-9ab2-80a95fd96b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85930
6702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.859306702
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3279553672
Short name T350
Test name
Test status
Simulation time 4399924112 ps
CPU time 61.88 seconds
Started Jun 25 07:14:19 PM PDT 24
Finished Jun 25 07:15:30 PM PDT 24
Peak memory 257588 kb
Host smart-0b572c61-f3bb-4661-810a-bae2fa02e308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32795
53672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3279553672
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2595421251
Short name T57
Test name
Test status
Simulation time 9801154440 ps
CPU time 1034.88 seconds
Started Jun 25 07:14:30 PM PDT 24
Finished Jun 25 07:31:51 PM PDT 24
Peak memory 285628 kb
Host smart-4e32e53f-e09e-4a5f-8107-38ae79f8cc2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595421251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2595421251
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3120379860
Short name T75
Test name
Test status
Simulation time 131528153095 ps
CPU time 2090.65 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 07:49:25 PM PDT 24
Peak memory 289920 kb
Host smart-3ac21faf-e436-446f-9674-666dc3b6bf98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120379860 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3120379860
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3271454905
Short name T98
Test name
Test status
Simulation time 601544349861 ps
CPU time 2761.51 seconds
Started Jun 25 07:14:29 PM PDT 24
Finished Jun 25 08:00:36 PM PDT 24
Peak memory 288752 kb
Host smart-0a2f7cbb-a108-4c91-a4f6-3e498e6a29ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271454905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3271454905
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3385308192
Short name T348
Test name
Test status
Simulation time 3416368750 ps
CPU time 194.5 seconds
Started Jun 25 07:14:33 PM PDT 24
Finished Jun 25 07:17:52 PM PDT 24
Peak memory 251524 kb
Host smart-0f38077f-a258-44a8-ac17-a3de8b30fb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
08192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3385308192
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1614388300
Short name T45
Test name
Test status
Simulation time 391511403 ps
CPU time 21.75 seconds
Started Jun 25 07:14:34 PM PDT 24
Finished Jun 25 07:15:01 PM PDT 24
Peak memory 249156 kb
Host smart-e3480be6-f70e-4dd0-84d2-548d210c238a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
88300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1614388300
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1985579279
Short name T310
Test name
Test status
Simulation time 23905277289 ps
CPU time 1981.45 seconds
Started Jun 25 07:14:33 PM PDT 24
Finished Jun 25 07:47:40 PM PDT 24
Peak memory 290252 kb
Host smart-626a1cbd-3a13-48d4-b3b9-9459c4a8cc63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985579279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1985579279
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.6212780
Short name T472
Test name
Test status
Simulation time 11647401556 ps
CPU time 967.65 seconds
Started Jun 25 07:14:34 PM PDT 24
Finished Jun 25 07:30:47 PM PDT 24
Peak memory 289400 kb
Host smart-a74eea34-2cb0-4766-9718-48fc65014422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6212780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.6212780
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2266554487
Short name T603
Test name
Test status
Simulation time 8128481441 ps
CPU time 195.18 seconds
Started Jun 25 07:14:31 PM PDT 24
Finished Jun 25 07:17:51 PM PDT 24
Peak memory 249436 kb
Host smart-3a2844ab-8774-4c01-a551-e5a16c3958a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266554487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2266554487
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4069998822
Short name T78
Test name
Test status
Simulation time 4367993120 ps
CPU time 82.62 seconds
Started Jun 25 07:14:30 PM PDT 24
Finished Jun 25 07:15:58 PM PDT 24
Peak memory 257548 kb
Host smart-729558f7-06d6-4fa7-9bd7-3731162af3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
98822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4069998822
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4162623210
Short name T514
Test name
Test status
Simulation time 1015562020 ps
CPU time 56.55 seconds
Started Jun 25 07:14:28 PM PDT 24
Finished Jun 25 07:15:30 PM PDT 24
Peak memory 257500 kb
Host smart-0b31a985-a788-4722-98fe-507d1f75487d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41626
23210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4162623210
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3400018618
Short name T649
Test name
Test status
Simulation time 75139698 ps
CPU time 9.71 seconds
Started Jun 25 07:14:31 PM PDT 24
Finished Jun 25 07:14:46 PM PDT 24
Peak memory 248424 kb
Host smart-b488f664-f16c-44fe-8db6-24dcbe015d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000
18618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3400018618
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2166225685
Short name T621
Test name
Test status
Simulation time 403059563 ps
CPU time 14.46 seconds
Started Jun 25 07:14:31 PM PDT 24
Finished Jun 25 07:14:51 PM PDT 24
Peak memory 257464 kb
Host smart-a6163629-9997-40be-9aa3-ca23dda25e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
25685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2166225685
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4066105074
Short name T110
Test name
Test status
Simulation time 17736649345 ps
CPU time 1840.96 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:45:27 PM PDT 24
Peak memory 290104 kb
Host smart-264dcd7d-e053-4325-8d02-4ce7a775ffd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066105074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4066105074
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1123366965
Short name T494
Test name
Test status
Simulation time 1451976655 ps
CPU time 130.72 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:16:56 PM PDT 24
Peak memory 257004 kb
Host smart-64ef8561-5191-46b6-ba9a-b5da2a34a864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233
66965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1123366965
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2366286645
Short name T69
Test name
Test status
Simulation time 5090932259 ps
CPU time 80.73 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:16:06 PM PDT 24
Peak memory 257036 kb
Host smart-8d3409ef-ae84-4197-905e-9a33cc3c0b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
86645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2366286645
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3862728905
Short name T647
Test name
Test status
Simulation time 489632503838 ps
CPU time 2939.79 seconds
Started Jun 25 07:14:40 PM PDT 24
Finished Jun 25 08:03:44 PM PDT 24
Peak memory 285076 kb
Host smart-ee0b43d8-ccb3-440e-814c-bcdc3e88d482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862728905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3862728905
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1126866087
Short name T365
Test name
Test status
Simulation time 37163608662 ps
CPU time 715.92 seconds
Started Jun 25 07:14:40 PM PDT 24
Finished Jun 25 07:26:41 PM PDT 24
Peak memory 273632 kb
Host smart-dfbae0d4-819e-451b-b6c4-91cc1ec9572f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126866087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1126866087
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4278100995
Short name T302
Test name
Test status
Simulation time 2624597712 ps
CPU time 110.48 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:16:36 PM PDT 24
Peak memory 255368 kb
Host smart-746b944a-3d6c-49e0-98c5-8ddd4f982701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278100995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4278100995
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.895946254
Short name T427
Test name
Test status
Simulation time 2086932325 ps
CPU time 58.91 seconds
Started Jun 25 07:14:40 PM PDT 24
Finished Jun 25 07:15:43 PM PDT 24
Peak memory 257064 kb
Host smart-e0212e82-ad83-41e5-8ae9-b66d3aeb60c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89594
6254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.895946254
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3425296660
Short name T377
Test name
Test status
Simulation time 2257449344 ps
CPU time 33.9 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:15:20 PM PDT 24
Peak memory 257144 kb
Host smart-1c564e73-a488-4fcd-a881-2afdcc714e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
96660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3425296660
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3058243740
Short name T554
Test name
Test status
Simulation time 1499611516 ps
CPU time 31.78 seconds
Started Jun 25 07:14:30 PM PDT 24
Finished Jun 25 07:15:08 PM PDT 24
Peak memory 256916 kb
Host smart-c2fe32bd-0b4f-48c4-85e8-796c4d64db16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
43740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3058243740
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2029088363
Short name T63
Test name
Test status
Simulation time 47533866601 ps
CPU time 3893 seconds
Started Jun 25 07:14:39 PM PDT 24
Finished Jun 25 08:19:37 PM PDT 24
Peak memory 323300 kb
Host smart-75c6fbaf-9fbe-4bc9-86b6-2eef97b7bd2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029088363 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2029088363
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3743691611
Short name T360
Test name
Test status
Simulation time 36047285747 ps
CPU time 915.27 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:30:12 PM PDT 24
Peak memory 273444 kb
Host smart-0af10968-fc7b-4258-9b22-e4ebfe3899b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743691611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3743691611
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.460603080
Short name T602
Test name
Test status
Simulation time 16681469546 ps
CPU time 202.65 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 07:18:18 PM PDT 24
Peak memory 257600 kb
Host smart-3370bc0d-f631-49a8-bc00-7abf6b80eea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46060
3080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.460603080
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2390961212
Short name T573
Test name
Test status
Simulation time 157803579 ps
CPU time 3.76 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:15:01 PM PDT 24
Peak memory 241048 kb
Host smart-c7c37479-b622-40e8-817d-118528db950d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
61212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2390961212
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3969954428
Short name T248
Test name
Test status
Simulation time 19924553335 ps
CPU time 1241.82 seconds
Started Jun 25 07:14:57 PM PDT 24
Finished Jun 25 07:35:47 PM PDT 24
Peak memory 273404 kb
Host smart-d43649c3-15f9-4e56-ae73-61de3e303050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969954428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3969954428
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.718092382
Short name T534
Test name
Test status
Simulation time 65416371764 ps
CPU time 1692.85 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:43:11 PM PDT 24
Peak memory 273976 kb
Host smart-750f67ba-ed83-4e73-a98e-56f5e0cd30ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718092382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.718092382
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1695071798
Short name T293
Test name
Test status
Simulation time 9539035262 ps
CPU time 391.01 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:21:29 PM PDT 24
Peak memory 249408 kb
Host smart-5d862428-d5c2-47f6-8588-334ca4fed88b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695071798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1695071798
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1196276084
Short name T537
Test name
Test status
Simulation time 112295875 ps
CPU time 15.45 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:15:01 PM PDT 24
Peak memory 256544 kb
Host smart-f8eeca03-e748-40ea-90a6-5b25392c569b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
76084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1196276084
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.797104313
Short name T599
Test name
Test status
Simulation time 100444515 ps
CPU time 7 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:15:05 PM PDT 24
Peak memory 249344 kb
Host smart-8e59312f-dd49-4989-9468-d1c2e8ff7be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79710
4313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.797104313
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.201085729
Short name T495
Test name
Test status
Simulation time 3629121317 ps
CPU time 17.86 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 07:15:13 PM PDT 24
Peak memory 256224 kb
Host smart-75a8a168-d6d9-48ce-ad81-1f13d31d29b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
5729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.201085729
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2300571099
Short name T114
Test name
Test status
Simulation time 807352858 ps
CPU time 21.18 seconds
Started Jun 25 07:14:41 PM PDT 24
Finished Jun 25 07:15:06 PM PDT 24
Peak memory 256800 kb
Host smart-44d5bb74-dacd-40fe-b166-2b8b5045d3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23005
71099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2300571099
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.439560344
Short name T109
Test name
Test status
Simulation time 134054905584 ps
CPU time 2492.96 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:56:29 PM PDT 24
Peak memory 290412 kb
Host smart-001f5fa0-3916-4877-ad4b-14b6ea829aa3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439560344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.439560344
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.667931638
Short name T103
Test name
Test status
Simulation time 218913637720 ps
CPU time 3270.08 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 08:09:26 PM PDT 24
Peak memory 279784 kb
Host smart-843db12e-89a9-46b1-ab67-316fa545b632
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667931638 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.667931638
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.914480797
Short name T481
Test name
Test status
Simulation time 126815457359 ps
CPU time 2168.4 seconds
Started Jun 25 07:14:57 PM PDT 24
Finished Jun 25 07:51:13 PM PDT 24
Peak memory 273964 kb
Host smart-106a1488-baa4-46ad-9ef8-75186e1d0bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914480797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.914480797
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1702576152
Short name T521
Test name
Test status
Simulation time 1096245707 ps
CPU time 96.58 seconds
Started Jun 25 07:14:52 PM PDT 24
Finished Jun 25 07:16:36 PM PDT 24
Peak memory 256552 kb
Host smart-0ab4f031-c740-49c1-b40b-8cc42365c92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17025
76152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1702576152
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3427534016
Short name T446
Test name
Test status
Simulation time 1298375331 ps
CPU time 71.18 seconds
Started Jun 25 07:14:52 PM PDT 24
Finished Jun 25 07:16:10 PM PDT 24
Peak memory 249712 kb
Host smart-40162c4e-c842-48e5-9dd5-dd8f43e72382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
34016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3427534016
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.184704396
Short name T329
Test name
Test status
Simulation time 124006109490 ps
CPU time 1852.33 seconds
Started Jun 25 07:14:53 PM PDT 24
Finished Jun 25 07:45:53 PM PDT 24
Peak memory 273384 kb
Host smart-0f8707ae-ae82-4038-9e15-377a1c13fb94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184704396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.184704396
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2403013092
Short name T434
Test name
Test status
Simulation time 24537844512 ps
CPU time 1781.19 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:44:39 PM PDT 24
Peak memory 284092 kb
Host smart-c09e323b-1c61-4470-aaab-e02ad9a51d00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403013092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2403013092
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1498821688
Short name T65
Test name
Test status
Simulation time 449935148 ps
CPU time 13.89 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:15:12 PM PDT 24
Peak memory 256748 kb
Host smart-b39cdd32-745b-4ade-88c1-7a8d32316a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14988
21688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1498821688
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3338683105
Short name T455
Test name
Test status
Simulation time 879091064 ps
CPU time 56.51 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 07:15:51 PM PDT 24
Peak memory 257380 kb
Host smart-b7c53d3f-dfa0-443f-90c4-01f8d7488627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33386
83105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3338683105
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.64716838
Short name T270
Test name
Test status
Simulation time 780745167 ps
CPU time 62.1 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:15:59 PM PDT 24
Peak memory 249236 kb
Host smart-0eaaff1c-e6bc-45e8-a442-0e41dee8b847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64716
838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.64716838
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1789217682
Short name T586
Test name
Test status
Simulation time 56389334 ps
CPU time 8.66 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:15:05 PM PDT 24
Peak memory 254336 kb
Host smart-d2c9a9ab-2a93-4245-b8f9-5a201068fc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
17682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1789217682
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2908071396
Short name T246
Test name
Test status
Simulation time 17028753134 ps
CPU time 749.24 seconds
Started Jun 25 07:14:52 PM PDT 24
Finished Jun 25 07:27:28 PM PDT 24
Peak memory 273952 kb
Host smart-95d9efa7-4219-4535-9cb0-a3bcdd7c571c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908071396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2908071396
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.822577008
Short name T540
Test name
Test status
Simulation time 24575035250 ps
CPU time 353.54 seconds
Started Jun 25 07:14:57 PM PDT 24
Finished Jun 25 07:20:58 PM PDT 24
Peak memory 256944 kb
Host smart-16aed7b5-68b1-4664-bb81-fc471e347c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82257
7008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.822577008
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.770074676
Short name T637
Test name
Test status
Simulation time 263142900 ps
CPU time 18.88 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:15:17 PM PDT 24
Peak memory 249320 kb
Host smart-e4420522-d163-43ff-b29d-da2fe4b98cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77007
4676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.770074676
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2018908061
Short name T522
Test name
Test status
Simulation time 10116504729 ps
CPU time 1004.93 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 07:31:41 PM PDT 24
Peak memory 273988 kb
Host smart-90d98fd2-30c2-490e-8fc2-137ed3d6a28d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018908061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2018908061
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2441191135
Short name T437
Test name
Test status
Simulation time 50308997186 ps
CPU time 3296.39 seconds
Started Jun 25 07:14:57 PM PDT 24
Finished Jun 25 08:10:02 PM PDT 24
Peak memory 289572 kb
Host smart-1d366472-dd45-4317-9f4e-eb39610121d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441191135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2441191135
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1123435
Short name T643
Test name
Test status
Simulation time 23618296523 ps
CPU time 488.7 seconds
Started Jun 25 07:14:52 PM PDT 24
Finished Jun 25 07:23:08 PM PDT 24
Peak memory 249412 kb
Host smart-b5ffcd13-2b92-4c42-8608-377e300e2e09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1123435
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2710773575
Short name T371
Test name
Test status
Simulation time 704615539 ps
CPU time 22.88 seconds
Started Jun 25 07:14:53 PM PDT 24
Finished Jun 25 07:15:22 PM PDT 24
Peak memory 256768 kb
Host smart-a7303768-3988-4263-b749-5cbdd8e82895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27107
73575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2710773575
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.17085795
Short name T60
Test name
Test status
Simulation time 460575239 ps
CPU time 25.71 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:15:24 PM PDT 24
Peak memory 256480 kb
Host smart-334ddf43-a677-483b-bfb1-1d719bb23588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085
795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.17085795
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1383263157
Short name T61
Test name
Test status
Simulation time 752109942 ps
CPU time 52.89 seconds
Started Jun 25 07:14:51 PM PDT 24
Finished Jun 25 07:15:51 PM PDT 24
Peak memory 256880 kb
Host smart-057eda42-8933-4523-9c16-f2720cb5bdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13832
63157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1383263157
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2739911938
Short name T507
Test name
Test status
Simulation time 6281669645 ps
CPU time 38.44 seconds
Started Jun 25 07:14:50 PM PDT 24
Finished Jun 25 07:15:35 PM PDT 24
Peak memory 257532 kb
Host smart-5f5a0284-a1ee-46d9-85fd-175b0961cbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27399
11938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2739911938
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2383322685
Short name T475
Test name
Test status
Simulation time 100028903462 ps
CPU time 3243.27 seconds
Started Jun 25 07:14:49 PM PDT 24
Finished Jun 25 08:08:58 PM PDT 24
Peak memory 289896 kb
Host smart-3eaf4b46-7994-4a1d-ad31-ad1aab9d0591
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383322685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2383322685
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3718276656
Short name T205
Test name
Test status
Simulation time 114229869 ps
CPU time 3.09 seconds
Started Jun 25 07:12:44 PM PDT 24
Finished Jun 25 07:13:07 PM PDT 24
Peak memory 249528 kb
Host smart-35123f87-3ed5-40a4-a30a-9bd28f36ec4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3718276656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3718276656
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.336071481
Short name T520
Test name
Test status
Simulation time 81318413911 ps
CPU time 1432.72 seconds
Started Jun 25 07:12:39 PM PDT 24
Finished Jun 25 07:36:54 PM PDT 24
Peak memory 273780 kb
Host smart-8945d611-01a9-419b-91ef-f04d317fc216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336071481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.336071481
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1668991131
Short name T502
Test name
Test status
Simulation time 698962142 ps
CPU time 10.87 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:13:11 PM PDT 24
Peak memory 249408 kb
Host smart-0147f785-e666-403b-95d5-6e3b470e24c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1668991131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1668991131
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1860786775
Short name T347
Test name
Test status
Simulation time 2584760249 ps
CPU time 150.61 seconds
Started Jun 25 07:12:28 PM PDT 24
Finished Jun 25 07:15:23 PM PDT 24
Peak memory 257132 kb
Host smart-75789b70-35fb-467c-9b99-bcee52dad6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
86775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1860786775
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.941260039
Short name T86
Test name
Test status
Simulation time 734448033 ps
CPU time 15.56 seconds
Started Jun 25 07:12:34 PM PDT 24
Finished Jun 25 07:13:13 PM PDT 24
Peak memory 248856 kb
Host smart-c8175d74-ac22-4e68-bb54-35d78f011dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94126
0039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.941260039
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4190049892
Short name T659
Test name
Test status
Simulation time 174283052097 ps
CPU time 1591.07 seconds
Started Jun 25 07:12:41 PM PDT 24
Finished Jun 25 07:39:33 PM PDT 24
Peak memory 282228 kb
Host smart-ace63ac0-3d0d-4e4a-ae38-a6b536190c5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190049892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4190049892
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.36114925
Short name T568
Test name
Test status
Simulation time 34026663610 ps
CPU time 369.16 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:19:11 PM PDT 24
Peak memory 255988 kb
Host smart-c6923f65-5955-4b90-b784-3af2a8a9bd3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36114925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.36114925
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2324943204
Short name T473
Test name
Test status
Simulation time 391346531 ps
CPU time 21.25 seconds
Started Jun 25 07:12:35 PM PDT 24
Finished Jun 25 07:13:19 PM PDT 24
Peak memory 249332 kb
Host smart-67c33864-1f17-48c6-9297-04a46f206590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
43204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2324943204
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.623014395
Short name T344
Test name
Test status
Simulation time 1130915912 ps
CPU time 70.57 seconds
Started Jun 25 07:12:36 PM PDT 24
Finished Jun 25 07:14:09 PM PDT 24
Peak memory 250356 kb
Host smart-e776f231-a0b1-4a6f-97fc-6b6faf3fd656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62301
4395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.623014395
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2579050960
Short name T11
Test name
Test status
Simulation time 876122788 ps
CPU time 14.08 seconds
Started Jun 25 07:12:41 PM PDT 24
Finished Jun 25 07:13:16 PM PDT 24
Peak memory 271648 kb
Host smart-6b7cc667-e00b-40f3-bbfb-0cb65dc5ab98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2579050960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2579050960
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1621969290
Short name T627
Test name
Test status
Simulation time 230734797 ps
CPU time 23.4 seconds
Started Jun 25 07:12:27 PM PDT 24
Finished Jun 25 07:13:14 PM PDT 24
Peak memory 249244 kb
Host smart-2d1e9d61-7bcd-4d58-8c71-db52eef000ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16219
69290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1621969290
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3861510631
Short name T71
Test name
Test status
Simulation time 2033676262 ps
CPU time 34.42 seconds
Started Jun 25 07:12:29 PM PDT 24
Finished Jun 25 07:13:27 PM PDT 24
Peak memory 256436 kb
Host smart-623e1ccf-4392-4576-82e3-5d942bd0d5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38615
10631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3861510631
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2341937328
Short name T411
Test name
Test status
Simulation time 116887538375 ps
CPU time 1688.14 seconds
Started Jun 25 07:14:59 PM PDT 24
Finished Jun 25 07:43:14 PM PDT 24
Peak memory 273424 kb
Host smart-d99dac9d-b5b0-4978-bbc5-48c20d822838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341937328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2341937328
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4261420247
Short name T1
Test name
Test status
Simulation time 477360732 ps
CPU time 31.47 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:15:39 PM PDT 24
Peak memory 256948 kb
Host smart-68e025b0-a698-49be-ae87-e1534803e568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
20247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4261420247
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1704879763
Short name T574
Test name
Test status
Simulation time 1380035267 ps
CPU time 31 seconds
Started Jun 25 07:15:02 PM PDT 24
Finished Jun 25 07:15:40 PM PDT 24
Peak memory 248716 kb
Host smart-519a8af0-8f9f-4ad6-98df-bb340efaab8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
79763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1704879763
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3394067349
Short name T556
Test name
Test status
Simulation time 17984843088 ps
CPU time 1190.02 seconds
Started Jun 25 07:14:59 PM PDT 24
Finished Jun 25 07:34:57 PM PDT 24
Peak memory 265828 kb
Host smart-5c4b56e3-bfde-4a9a-bbe2-cfce213301bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394067349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3394067349
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1051048718
Short name T697
Test name
Test status
Simulation time 2136230688 ps
CPU time 34 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:15:42 PM PDT 24
Peak memory 256772 kb
Host smart-f9126afb-20e2-481e-909e-c26fe43a978a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
48718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1051048718
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4102803452
Short name T401
Test name
Test status
Simulation time 716585268 ps
CPU time 37.94 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:15:45 PM PDT 24
Peak memory 248716 kb
Host smart-46acfc9a-bd81-4249-8c55-d3360cc41f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41028
03452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4102803452
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1952351932
Short name T272
Test name
Test status
Simulation time 2876283090 ps
CPU time 49.39 seconds
Started Jun 25 07:15:01 PM PDT 24
Finished Jun 25 07:15:58 PM PDT 24
Peak memory 257140 kb
Host smart-a01af9e6-fcb6-4197-8c35-e262987a7954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523
51932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1952351932
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.717020845
Short name T454
Test name
Test status
Simulation time 251177263 ps
CPU time 33.15 seconds
Started Jun 25 07:14:59 PM PDT 24
Finished Jun 25 07:15:39 PM PDT 24
Peak memory 249172 kb
Host smart-49f9dd33-4790-4837-898d-12b8c370802b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71702
0845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.717020845
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4012851188
Short name T550
Test name
Test status
Simulation time 19558930012 ps
CPU time 475.12 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:23:03 PM PDT 24
Peak memory 257436 kb
Host smart-e63fd3d4-1982-4639-96eb-57aa32dc698c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012851188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4012851188
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3055506934
Short name T492
Test name
Test status
Simulation time 33339596989 ps
CPU time 1961.04 seconds
Started Jun 25 07:14:59 PM PDT 24
Finished Jun 25 07:47:48 PM PDT 24
Peak memory 285048 kb
Host smart-9ceb2b93-5f16-4979-be8f-b5309836123d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055506934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3055506934
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2861104975
Short name T604
Test name
Test status
Simulation time 2442749358 ps
CPU time 133.55 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:17:21 PM PDT 24
Peak memory 256832 kb
Host smart-bfe4dba2-b9ef-456c-a72f-1ff4df342d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
04975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2861104975
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4273696780
Short name T351
Test name
Test status
Simulation time 97434568 ps
CPU time 7.09 seconds
Started Jun 25 07:15:01 PM PDT 24
Finished Jun 25 07:15:16 PM PDT 24
Peak memory 249888 kb
Host smart-d3dea62f-30bf-4a71-8cd3-c0ee7bb7cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
96780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4273696780
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3368367809
Short name T326
Test name
Test status
Simulation time 195339096637 ps
CPU time 3135.61 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 08:07:32 PM PDT 24
Peak memory 287660 kb
Host smart-60f373fe-ec49-4ea6-8284-033fca262855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368367809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3368367809
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1423886784
Short name T256
Test name
Test status
Simulation time 38657938379 ps
CPU time 971.03 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:31:27 PM PDT 24
Peak memory 272136 kb
Host smart-b699202b-79a9-44d1-8213-2f7aa34edcaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423886784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1423886784
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2429911451
Short name T309
Test name
Test status
Simulation time 8597034137 ps
CPU time 328.07 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:20:35 PM PDT 24
Peak memory 249356 kb
Host smart-62f4e4d9-623b-4a29-8e3b-4f4377b1ade7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429911451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2429911451
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.793160077
Short name T432
Test name
Test status
Simulation time 264667944 ps
CPU time 9.89 seconds
Started Jun 25 07:15:01 PM PDT 24
Finished Jun 25 07:15:18 PM PDT 24
Peak memory 249772 kb
Host smart-76dee30f-29cc-4b8c-8995-b96dcc91edee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79316
0077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.793160077
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3612790351
Short name T359
Test name
Test status
Simulation time 1102081922 ps
CPU time 72.94 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:16:20 PM PDT 24
Peak memory 248760 kb
Host smart-1835f02b-16da-4dbd-9f03-0a61a7137539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
90351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3612790351
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2577719948
Short name T606
Test name
Test status
Simulation time 128697634 ps
CPU time 8.31 seconds
Started Jun 25 07:15:01 PM PDT 24
Finished Jun 25 07:15:17 PM PDT 24
Peak memory 254996 kb
Host smart-9651d445-fd80-433c-bf03-093ffedd9a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25777
19948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2577719948
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3875240607
Short name T387
Test name
Test status
Simulation time 1597710295 ps
CPU time 29.67 seconds
Started Jun 25 07:15:00 PM PDT 24
Finished Jun 25 07:15:37 PM PDT 24
Peak memory 256940 kb
Host smart-08409fc5-3ef8-42e2-b2e9-68417d4d78d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752
40607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3875240607
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.88524537
Short name T525
Test name
Test status
Simulation time 81067925212 ps
CPU time 2592.71 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:58:29 PM PDT 24
Peak memory 289132 kb
Host smart-127e86fc-2f61-4933-9433-e3fde1e76f5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88524537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_hand
ler_stress_all.88524537
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2700425136
Short name T478
Test name
Test status
Simulation time 22745337949 ps
CPU time 1132.74 seconds
Started Jun 25 07:15:10 PM PDT 24
Finished Jun 25 07:34:09 PM PDT 24
Peak memory 289180 kb
Host smart-08185efd-7bfd-49ab-8ff3-68bcdd887065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700425136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2700425136
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1980312349
Short name T382
Test name
Test status
Simulation time 5034866671 ps
CPU time 305.49 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:20:22 PM PDT 24
Peak memory 256936 kb
Host smart-a849878c-6f45-4c31-9bff-b9fd4855f8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
12349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1980312349
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1421356551
Short name T467
Test name
Test status
Simulation time 800388116 ps
CPU time 44.86 seconds
Started Jun 25 07:15:09 PM PDT 24
Finished Jun 25 07:16:00 PM PDT 24
Peak memory 257504 kb
Host smart-8a26e4ec-6446-4b19-8941-711074c443b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14213
56551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1421356551
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4282839412
Short name T76
Test name
Test status
Simulation time 99432568061 ps
CPU time 1573.37 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:41:30 PM PDT 24
Peak memory 282188 kb
Host smart-9e5074e7-73c9-477a-9068-3dd7a4184e6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282839412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4282839412
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3319140594
Short name T692
Test name
Test status
Simulation time 82106156089 ps
CPU time 1632.66 seconds
Started Jun 25 07:15:13 PM PDT 24
Finished Jun 25 07:42:30 PM PDT 24
Peak memory 272868 kb
Host smart-b7202b64-d7a5-4786-a509-894b2d8c804b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319140594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3319140594
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3170078294
Short name T617
Test name
Test status
Simulation time 53818365163 ps
CPU time 547.12 seconds
Started Jun 25 07:15:10 PM PDT 24
Finished Jun 25 07:24:23 PM PDT 24
Peak memory 249364 kb
Host smart-b86cbe40-5740-4cfa-ab49-39166a6fb5fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170078294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3170078294
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2333695822
Short name T444
Test name
Test status
Simulation time 67656431 ps
CPU time 5.5 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:15:22 PM PDT 24
Peak memory 249288 kb
Host smart-2becc4f1-8807-4ee6-89dd-54c49134392e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23336
95822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2333695822
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1625285557
Short name T56
Test name
Test status
Simulation time 3717024686 ps
CPU time 58.62 seconds
Started Jun 25 07:15:10 PM PDT 24
Finished Jun 25 07:16:14 PM PDT 24
Peak memory 256648 kb
Host smart-0f015db9-7475-4c5f-a917-aa2b2282af06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
85557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1625285557
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2194073106
Short name T231
Test name
Test status
Simulation time 1924537543 ps
CPU time 32.11 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:15:48 PM PDT 24
Peak memory 249260 kb
Host smart-83342671-d3d6-4197-8268-31aa4be57604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
73106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2194073106
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2080099755
Short name T638
Test name
Test status
Simulation time 321092308 ps
CPU time 26.4 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:15:42 PM PDT 24
Peak memory 256984 kb
Host smart-53c5a05e-fd6f-4c13-9679-71cb542f8b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
99755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2080099755
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2994120226
Short name T677
Test name
Test status
Simulation time 36250755244 ps
CPU time 541.96 seconds
Started Jun 25 07:15:12 PM PDT 24
Finished Jun 25 07:24:19 PM PDT 24
Peak memory 265836 kb
Host smart-aff5792d-2839-4f66-a775-ccff95c002a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994120226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2994120226
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3593294986
Short name T408
Test name
Test status
Simulation time 121022014791 ps
CPU time 2445.8 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:56:13 PM PDT 24
Peak memory 287220 kb
Host smart-2ed2ed89-e7b5-4792-9f39-607a65657ba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593294986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3593294986
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1579191955
Short name T453
Test name
Test status
Simulation time 169324010 ps
CPU time 4.43 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:15:32 PM PDT 24
Peak memory 248720 kb
Host smart-fa897cce-255d-4588-99d7-c569e5aa550d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15791
91955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1579191955
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2909257298
Short name T440
Test name
Test status
Simulation time 2889355783 ps
CPU time 18.93 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:15:46 PM PDT 24
Peak memory 248792 kb
Host smart-bdde516f-b4e3-40d8-a4d0-acc83edc3639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
57298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2909257298
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.854935287
Short name T370
Test name
Test status
Simulation time 53345182483 ps
CPU time 3218.73 seconds
Started Jun 25 07:15:23 PM PDT 24
Finished Jun 25 08:09:07 PM PDT 24
Peak memory 289296 kb
Host smart-af9c75bd-ec2a-4384-aa79-18ce3dc7a810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854935287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.854935287
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1195880098
Short name T578
Test name
Test status
Simulation time 8858017236 ps
CPU time 212.76 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:19:00 PM PDT 24
Peak memory 249432 kb
Host smart-214e9fcb-4697-4846-a899-afb6ad37aea9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195880098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1195880098
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4056395047
Short name T552
Test name
Test status
Simulation time 4352559703 ps
CPU time 69.45 seconds
Started Jun 25 07:15:09 PM PDT 24
Finished Jun 25 07:16:25 PM PDT 24
Peak memory 257520 kb
Host smart-9eb88db0-5c2b-45f4-beb8-61c3c5cf041c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40563
95047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4056395047
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2319884215
Short name T403
Test name
Test status
Simulation time 176018166 ps
CPU time 13.18 seconds
Started Jun 25 07:15:21 PM PDT 24
Finished Jun 25 07:15:39 PM PDT 24
Peak memory 255504 kb
Host smart-ed3f5553-34b3-46cc-9aa6-ebe0e6bf41d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23198
84215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2319884215
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.260944147
Short name T587
Test name
Test status
Simulation time 229794482 ps
CPU time 5.24 seconds
Started Jun 25 07:15:11 PM PDT 24
Finished Jun 25 07:15:21 PM PDT 24
Peak memory 240988 kb
Host smart-2644b176-413f-4564-b6b7-75605b2089a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26094
4147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.260944147
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.131689432
Short name T561
Test name
Test status
Simulation time 152348082256 ps
CPU time 2402.5 seconds
Started Jun 25 07:15:24 PM PDT 24
Finished Jun 25 07:55:33 PM PDT 24
Peak memory 285092 kb
Host smart-7bb99aab-2d9c-411c-9962-d74bec96453d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131689432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.131689432
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.818225270
Short name T372
Test name
Test status
Simulation time 16934746847 ps
CPU time 282.63 seconds
Started Jun 25 07:15:23 PM PDT 24
Finished Jun 25 07:20:11 PM PDT 24
Peak memory 257076 kb
Host smart-98391f94-0f2c-4835-85c7-944e214e6a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81822
5270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.818225270
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.924574103
Short name T80
Test name
Test status
Simulation time 735906451 ps
CPU time 54.37 seconds
Started Jun 25 07:15:24 PM PDT 24
Finished Jun 25 07:16:25 PM PDT 24
Peak memory 257052 kb
Host smart-54463334-e7aa-4709-bb73-57a6db33862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92457
4103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.924574103
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4251783790
Short name T116
Test name
Test status
Simulation time 8250467164 ps
CPU time 861.76 seconds
Started Jun 25 07:15:38 PM PDT 24
Finished Jun 25 07:30:07 PM PDT 24
Peak memory 274128 kb
Host smart-c284b1ec-4217-4276-953e-59807017d0a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251783790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4251783790
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.694369042
Short name T591
Test name
Test status
Simulation time 10614127401 ps
CPU time 416.43 seconds
Started Jun 25 07:15:21 PM PDT 24
Finished Jun 25 07:22:23 PM PDT 24
Peak memory 249268 kb
Host smart-45fae33a-49c1-4bff-94d2-b9e83cf3f394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694369042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.694369042
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1966546133
Short name T400
Test name
Test status
Simulation time 479418469 ps
CPU time 30.72 seconds
Started Jun 25 07:15:24 PM PDT 24
Finished Jun 25 07:16:01 PM PDT 24
Peak memory 256548 kb
Host smart-c67f4202-4e34-4b5f-a019-4a7f80d838e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
46133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1966546133
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3514863774
Short name T690
Test name
Test status
Simulation time 588133760 ps
CPU time 11.77 seconds
Started Jun 25 07:15:23 PM PDT 24
Finished Jun 25 07:15:40 PM PDT 24
Peak memory 249332 kb
Host smart-e2d0da0c-2708-454d-93b6-bb6214693e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35148
63774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3514863774
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2498130142
Short name T81
Test name
Test status
Simulation time 671373500 ps
CPU time 6.34 seconds
Started Jun 25 07:15:25 PM PDT 24
Finished Jun 25 07:15:38 PM PDT 24
Peak memory 248808 kb
Host smart-2ddf4f30-5894-424b-9b79-4a27c5aee7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
30142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2498130142
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3491687829
Short name T611
Test name
Test status
Simulation time 398148542 ps
CPU time 23.87 seconds
Started Jun 25 07:15:22 PM PDT 24
Finished Jun 25 07:15:51 PM PDT 24
Peak memory 256564 kb
Host smart-d9bfc91d-725c-4355-b7bc-58290ef40af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
87829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3491687829
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3908493080
Short name T251
Test name
Test status
Simulation time 60274903411 ps
CPU time 3417.4 seconds
Started Jun 25 07:15:33 PM PDT 24
Finished Jun 25 08:12:37 PM PDT 24
Peak memory 306700 kb
Host smart-50b6d5b0-acab-41d8-b0b5-8e1c44e3db75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908493080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3908493080
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4003787062
Short name T66
Test name
Test status
Simulation time 131536756911 ps
CPU time 2210.13 seconds
Started Jun 25 07:15:35 PM PDT 24
Finished Jun 25 07:52:32 PM PDT 24
Peak memory 289480 kb
Host smart-c4e078cf-bab7-4a2a-ae0e-f7222f47fbc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003787062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4003787062
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3466672643
Short name T551
Test name
Test status
Simulation time 347329736 ps
CPU time 26.18 seconds
Started Jun 25 07:15:32 PM PDT 24
Finished Jun 25 07:16:04 PM PDT 24
Peak memory 256548 kb
Host smart-12a64d60-476e-456b-8639-1bef3552d494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34666
72643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3466672643
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.25114577
Short name T639
Test name
Test status
Simulation time 671572071 ps
CPU time 25.18 seconds
Started Jun 25 07:15:33 PM PDT 24
Finished Jun 25 07:16:04 PM PDT 24
Peak memory 249840 kb
Host smart-d1a5e1b0-679e-4992-b45e-370f4781ca56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.25114577
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1218445867
Short name T323
Test name
Test status
Simulation time 63844883700 ps
CPU time 1321.1 seconds
Started Jun 25 07:15:38 PM PDT 24
Finished Jun 25 07:37:47 PM PDT 24
Peak memory 282436 kb
Host smart-fb1330c9-ae93-4af3-9d65-fedc61d09968
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218445867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1218445867
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1314100328
Short name T381
Test name
Test status
Simulation time 15287294315 ps
CPU time 935.06 seconds
Started Jun 25 07:15:38 PM PDT 24
Finished Jun 25 07:31:20 PM PDT 24
Peak memory 283664 kb
Host smart-7819db9c-ba43-4dac-9744-b5777983a122
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314100328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1314100328
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1027329502
Short name T285
Test name
Test status
Simulation time 41786466687 ps
CPU time 167.46 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:18:28 PM PDT 24
Peak memory 249224 kb
Host smart-c1d44b01-08fb-4b56-9e66-2f03b2cf0f58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027329502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1027329502
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.4150223364
Short name T664
Test name
Test status
Simulation time 1000597542 ps
CPU time 37.6 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:16:18 PM PDT 24
Peak memory 256800 kb
Host smart-ebfd47f9-290c-4ed3-96e5-34cdb484f0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41502
23364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.4150223364
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1500375930
Short name T2
Test name
Test status
Simulation time 2418676271 ps
CPU time 49.65 seconds
Started Jun 25 07:15:33 PM PDT 24
Finished Jun 25 07:16:28 PM PDT 24
Peak memory 249372 kb
Host smart-9463e493-6796-46ef-9cf7-bca8e8d6e22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15003
75930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1500375930
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3371018676
Short name T85
Test name
Test status
Simulation time 3901060413 ps
CPU time 66.54 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:16:46 PM PDT 24
Peak memory 256880 kb
Host smart-ca61df95-46e8-412b-b630-189cee5598ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
18676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3371018676
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.710020838
Short name T644
Test name
Test status
Simulation time 258711015 ps
CPU time 29.13 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:16:10 PM PDT 24
Peak memory 256868 kb
Host smart-b6419ce1-f634-4770-9d9d-a5b8fd520857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71002
0838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.710020838
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1907242857
Short name T226
Test name
Test status
Simulation time 32531173118 ps
CPU time 2131.39 seconds
Started Jun 25 07:15:44 PM PDT 24
Finished Jun 25 07:51:21 PM PDT 24
Peak memory 286248 kb
Host smart-92dbeff9-c8bc-4c7e-a5a0-9d877de01bd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907242857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1907242857
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.249015724
Short name T376
Test name
Test status
Simulation time 7383883337 ps
CPU time 227.38 seconds
Started Jun 25 07:15:43 PM PDT 24
Finished Jun 25 07:19:36 PM PDT 24
Peak memory 257152 kb
Host smart-50b8a709-e9c3-46d0-b077-6bb47f967c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24901
5724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.249015724
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1136810016
Short name T605
Test name
Test status
Simulation time 1260594936 ps
CPU time 30.59 seconds
Started Jun 25 07:15:44 PM PDT 24
Finished Jun 25 07:16:20 PM PDT 24
Peak memory 257036 kb
Host smart-16ad6a49-23c9-4633-929e-077303bddc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
10016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1136810016
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3988698526
Short name T640
Test name
Test status
Simulation time 102052300493 ps
CPU time 1648.44 seconds
Started Jun 25 07:15:44 PM PDT 24
Finished Jun 25 07:43:18 PM PDT 24
Peak memory 273940 kb
Host smart-74960215-dcbb-442f-9cdd-d680501821eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988698526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3988698526
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2007559921
Short name T593
Test name
Test status
Simulation time 19269401002 ps
CPU time 397.23 seconds
Started Jun 25 07:15:46 PM PDT 24
Finished Jun 25 07:22:27 PM PDT 24
Peak memory 256012 kb
Host smart-cf39d0c7-c1ee-4be5-977f-2832ebf70526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007559921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2007559921
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2973739406
Short name T91
Test name
Test status
Simulation time 287462653 ps
CPU time 20.48 seconds
Started Jun 25 07:15:36 PM PDT 24
Finished Jun 25 07:16:03 PM PDT 24
Peak memory 249296 kb
Host smart-cbc6b65a-e394-4603-bce3-43549e0ffe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737
39406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2973739406
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4226593295
Short name T631
Test name
Test status
Simulation time 675274507 ps
CPU time 48.32 seconds
Started Jun 25 07:15:32 PM PDT 24
Finished Jun 25 07:16:26 PM PDT 24
Peak memory 248436 kb
Host smart-7df32808-3269-45fd-80da-c3601d9013c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
93295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4226593295
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2157842426
Short name T264
Test name
Test status
Simulation time 520328309 ps
CPU time 41.68 seconds
Started Jun 25 07:15:43 PM PDT 24
Finished Jun 25 07:16:31 PM PDT 24
Peak memory 257112 kb
Host smart-1c508c28-f49d-4791-acbc-14257fe877ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
42426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2157842426
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2592618652
Short name T356
Test name
Test status
Simulation time 1002945895 ps
CPU time 30.33 seconds
Started Jun 25 07:15:34 PM PDT 24
Finished Jun 25 07:16:11 PM PDT 24
Peak memory 249336 kb
Host smart-c31108ac-111c-4b6c-bb17-c81660f3472f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25926
18652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2592618652
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2946982866
Short name T216
Test name
Test status
Simulation time 18436704941 ps
CPU time 1199.26 seconds
Started Jun 25 07:15:41 PM PDT 24
Finished Jun 25 07:35:48 PM PDT 24
Peak memory 274052 kb
Host smart-d3f244a2-089e-483a-bca9-20a1cfa9134f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946982866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2946982866
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1227472749
Short name T699
Test name
Test status
Simulation time 31537310773 ps
CPU time 3858.63 seconds
Started Jun 25 07:15:44 PM PDT 24
Finished Jun 25 08:20:09 PM PDT 24
Peak memory 322852 kb
Host smart-1923e2ab-db61-4881-ba34-4b2d91c8a219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227472749 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1227472749
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1447128982
Short name T515
Test name
Test status
Simulation time 50867559358 ps
CPU time 857.89 seconds
Started Jun 25 07:15:58 PM PDT 24
Finished Jun 25 07:30:20 PM PDT 24
Peak memory 273924 kb
Host smart-de7b5c67-691f-468d-8f0f-2b6cababac7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447128982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1447128982
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3357133240
Short name T386
Test name
Test status
Simulation time 10988994727 ps
CPU time 272.27 seconds
Started Jun 25 07:15:44 PM PDT 24
Finished Jun 25 07:20:22 PM PDT 24
Peak memory 257072 kb
Host smart-e9d48f23-59ca-468d-a99c-674bcb8b5402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571
33240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3357133240
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2344402603
Short name T622
Test name
Test status
Simulation time 3063805082 ps
CPU time 45.5 seconds
Started Jun 25 07:15:45 PM PDT 24
Finished Jun 25 07:16:35 PM PDT 24
Peak memory 257588 kb
Host smart-01da030b-aa5d-4ad2-b466-5ed4e3962240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
02603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2344402603
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1917812590
Short name T290
Test name
Test status
Simulation time 13767245022 ps
CPU time 155.23 seconds
Started Jun 25 07:16:01 PM PDT 24
Finished Jun 25 07:18:40 PM PDT 24
Peak memory 249412 kb
Host smart-56b5a400-dcf9-423d-8bf3-f406f5b78159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917812590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1917812590
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1356860036
Short name T448
Test name
Test status
Simulation time 259715726 ps
CPU time 16.2 seconds
Started Jun 25 07:15:45 PM PDT 24
Finished Jun 25 07:16:06 PM PDT 24
Peak memory 256796 kb
Host smart-b9b31888-25a6-49c2-8b44-e2a75232856a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568
60036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1356860036
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.685464541
Short name T648
Test name
Test status
Simulation time 254514956 ps
CPU time 19.28 seconds
Started Jun 25 07:15:43 PM PDT 24
Finished Jun 25 07:16:08 PM PDT 24
Peak memory 257004 kb
Host smart-85548c73-727f-420e-80db-40ed8738f7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68546
4541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.685464541
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.488043157
Short name T670
Test name
Test status
Simulation time 295534909 ps
CPU time 26.57 seconds
Started Jun 25 07:15:46 PM PDT 24
Finished Jun 25 07:16:17 PM PDT 24
Peak memory 257472 kb
Host smart-0c49f1ba-5310-4c4f-8499-9096ae439557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48804
3157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.488043157
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.214629593
Short name T470
Test name
Test status
Simulation time 11076833965 ps
CPU time 1395.61 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 07:39:20 PM PDT 24
Peak memory 289868 kb
Host smart-430883a0-cf79-444e-92ba-482942d899e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214629593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.214629593
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.972102843
Short name T456
Test name
Test status
Simulation time 147824351307 ps
CPU time 2598.63 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 07:59:22 PM PDT 24
Peak memory 289764 kb
Host smart-b6228fc9-5890-4806-a928-c10ff427ff70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972102843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.972102843
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1072418363
Short name T570
Test name
Test status
Simulation time 6166286511 ps
CPU time 133.1 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 07:18:16 PM PDT 24
Peak memory 257132 kb
Host smart-d1c455fe-cf84-4a5f-953f-3ab9b8406680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
18363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1072418363
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.831772034
Short name T623
Test name
Test status
Simulation time 4296333417 ps
CPU time 63.23 seconds
Started Jun 25 07:15:59 PM PDT 24
Finished Jun 25 07:17:06 PM PDT 24
Peak memory 249196 kb
Host smart-92ed7214-9ab8-440f-97da-09bc2ecca80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83177
2034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.831772034
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3832281021
Short name T317
Test name
Test status
Simulation time 45743758485 ps
CPU time 1207.34 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 07:36:12 PM PDT 24
Peak memory 274004 kb
Host smart-86cb8464-710b-429a-b521-ff97dee04ab1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832281021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3832281021
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4101860841
Short name T393
Test name
Test status
Simulation time 89869125012 ps
CPU time 3160.72 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 08:08:45 PM PDT 24
Peak memory 282136 kb
Host smart-84d26fb6-0c89-405c-ada8-e3ca4abae235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101860841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4101860841
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4232247501
Short name T579
Test name
Test status
Simulation time 8131703275 ps
CPU time 94.74 seconds
Started Jun 25 07:15:59 PM PDT 24
Finished Jun 25 07:17:37 PM PDT 24
Peak memory 255072 kb
Host smart-401abb04-ffd5-4a13-9f7d-af03e57b552f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232247501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4232247501
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2082353591
Short name T477
Test name
Test status
Simulation time 29679761 ps
CPU time 5.17 seconds
Started Jun 25 07:16:02 PM PDT 24
Finished Jun 25 07:16:10 PM PDT 24
Peak memory 249296 kb
Host smart-dfb4c1f5-cd5e-44e7-a418-891fe2e7f82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823
53591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2082353591
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.487389806
Short name T92
Test name
Test status
Simulation time 6669475679 ps
CPU time 45.06 seconds
Started Jun 25 07:15:58 PM PDT 24
Finished Jun 25 07:16:47 PM PDT 24
Peak memory 257440 kb
Host smart-5e80641d-7aaf-4b67-9dac-775fa73fe86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48738
9806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.487389806
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1602193940
Short name T392
Test name
Test status
Simulation time 1495800082 ps
CPU time 39.5 seconds
Started Jun 25 07:16:00 PM PDT 24
Finished Jun 25 07:16:43 PM PDT 24
Peak memory 249332 kb
Host smart-6b3f6449-51e3-4693-bf5a-15f067eee3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16021
93940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1602193940
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3928241150
Short name T355
Test name
Test status
Simulation time 537840149 ps
CPU time 35.93 seconds
Started Jun 25 07:15:59 PM PDT 24
Finished Jun 25 07:16:38 PM PDT 24
Peak memory 256560 kb
Host smart-2fba4bd9-dd00-42ad-b36b-bbd75036683d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
41150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3928241150
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1138992316
Short name T6
Test name
Test status
Simulation time 2646636754 ps
CPU time 45.44 seconds
Started Jun 25 07:15:59 PM PDT 24
Finished Jun 25 07:16:48 PM PDT 24
Peak memory 257380 kb
Host smart-bc328948-654f-466d-be0a-288cb6fdf9f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138992316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1138992316
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.904345073
Short name T218
Test name
Test status
Simulation time 77864473771 ps
CPU time 1845.18 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:47:08 PM PDT 24
Peak memory 290284 kb
Host smart-1542a2d9-28ec-4826-8886-2401aa161361
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904345073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.904345073
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1526256419
Short name T445
Test name
Test status
Simulation time 932704422 ps
CPU time 72.98 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:17:36 PM PDT 24
Peak memory 257512 kb
Host smart-f8bd488b-e43a-4cdc-9784-6d2b0a34ffdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15262
56419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1526256419
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4171139941
Short name T22
Test name
Test status
Simulation time 1058179673 ps
CPU time 24.09 seconds
Started Jun 25 07:16:20 PM PDT 24
Finished Jun 25 07:16:48 PM PDT 24
Peak memory 249252 kb
Host smart-b2d714a7-faac-4d9d-9e19-d6482327dd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
39941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4171139941
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2931735416
Short name T500
Test name
Test status
Simulation time 16552961665 ps
CPU time 1647.68 seconds
Started Jun 25 07:16:18 PM PDT 24
Finished Jun 25 07:43:50 PM PDT 24
Peak memory 289936 kb
Host smart-45ba10a3-927d-425b-b149-2bf1468b521a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931735416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2931735416
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1662329960
Short name T214
Test name
Test status
Simulation time 120038510098 ps
CPU time 2280.07 seconds
Started Jun 25 07:16:18 PM PDT 24
Finished Jun 25 07:54:23 PM PDT 24
Peak memory 282236 kb
Host smart-f0102a05-8aa1-443a-850a-5b530e1fafc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662329960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1662329960
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1538316334
Short name T297
Test name
Test status
Simulation time 61375552647 ps
CPU time 242.45 seconds
Started Jun 25 07:16:20 PM PDT 24
Finished Jun 25 07:20:26 PM PDT 24
Peak memory 249424 kb
Host smart-034b4a27-6627-4dcf-9779-9df26bf7cf6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538316334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1538316334
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2988617206
Short name T585
Test name
Test status
Simulation time 299679221 ps
CPU time 24.4 seconds
Started Jun 25 07:16:17 PM PDT 24
Finished Jun 25 07:16:44 PM PDT 24
Peak memory 249620 kb
Host smart-2bbd1cab-88c8-4d7b-801a-65e356602ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29886
17206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2988617206
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2719525219
Short name T358
Test name
Test status
Simulation time 692067653 ps
CPU time 33.96 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:16:57 PM PDT 24
Peak memory 248848 kb
Host smart-44baf55e-8360-41d1-8fb7-4dcc6e4a0bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27195
25219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2719525219
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2500974195
Short name T491
Test name
Test status
Simulation time 848801051 ps
CPU time 47.53 seconds
Started Jun 25 07:16:02 PM PDT 24
Finished Jun 25 07:16:52 PM PDT 24
Peak memory 257092 kb
Host smart-f7f991bb-e33d-4887-9da9-915eeaed8a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25009
74195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2500974195
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.692539317
Short name T252
Test name
Test status
Simulation time 253663864808 ps
CPU time 3103.6 seconds
Started Jun 25 07:16:18 PM PDT 24
Finished Jun 25 08:08:07 PM PDT 24
Peak memory 290196 kb
Host smart-30f24a4b-e198-4655-8dac-10b6b4f5639c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692539317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.692539317
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2077900537
Short name T26
Test name
Test status
Simulation time 282366766910 ps
CPU time 7869.73 seconds
Started Jun 25 07:16:20 PM PDT 24
Finished Jun 25 09:27:35 PM PDT 24
Peak memory 355696 kb
Host smart-4f683d49-2bd5-4399-bffe-e222022c9244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077900537 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2077900537
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1816641211
Short name T199
Test name
Test status
Simulation time 383000001 ps
CPU time 3.72 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:13:14 PM PDT 24
Peak memory 249548 kb
Host smart-cce59678-6262-4fad-9d58-95eb9f9859bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1816641211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1816641211
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2006398205
Short name T79
Test name
Test status
Simulation time 31493488914 ps
CPU time 1820.65 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:43:22 PM PDT 24
Peak memory 273940 kb
Host smart-2a4d6395-311d-48d8-b37a-42ed462799c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006398205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2006398205
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2141065148
Short name T592
Test name
Test status
Simulation time 1226880066 ps
CPU time 16.01 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:13:26 PM PDT 24
Peak memory 249264 kb
Host smart-3c587732-678d-4b06-894f-e38113134143
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2141065148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2141065148
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2095301860
Short name T225
Test name
Test status
Simulation time 36549205024 ps
CPU time 158.65 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:15:40 PM PDT 24
Peak memory 257580 kb
Host smart-425fdc95-082d-4f5b-a4b8-e7b6bae18890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20953
01860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2095301860
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1223531630
Short name T416
Test name
Test status
Simulation time 494017759 ps
CPU time 15.94 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:13:17 PM PDT 24
Peak memory 249704 kb
Host smart-7e425dbc-0ab0-4079-ab63-a06cd728bb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
31630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1223531630
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3066597766
Short name T646
Test name
Test status
Simulation time 26121500861 ps
CPU time 697.85 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:24:39 PM PDT 24
Peak memory 273240 kb
Host smart-3d46ca10-ae1e-4a71-b27e-9ebe07803b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066597766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3066597766
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.44294013
Short name T16
Test name
Test status
Simulation time 26012704206 ps
CPU time 1331.39 seconds
Started Jun 25 07:12:51 PM PDT 24
Finished Jun 25 07:35:21 PM PDT 24
Peak memory 290008 kb
Host smart-8b73a317-37ca-4c27-943a-52c2f6417fc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44294013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.44294013
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1844018644
Short name T311
Test name
Test status
Simulation time 46593932207 ps
CPU time 516.23 seconds
Started Jun 25 07:12:44 PM PDT 24
Finished Jun 25 07:21:40 PM PDT 24
Peak memory 249232 kb
Host smart-9096a478-9950-4717-894c-a7a5e29ca1bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844018644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1844018644
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3027689354
Short name T67
Test name
Test status
Simulation time 471549923 ps
CPU time 16.54 seconds
Started Jun 25 07:12:41 PM PDT 24
Finished Jun 25 07:13:18 PM PDT 24
Peak memory 256740 kb
Host smart-7866c51a-455c-4fee-945f-047e2a10a6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30276
89354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3027689354
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.67869385
Short name T49
Test name
Test status
Simulation time 518692779 ps
CPU time 16.71 seconds
Started Jun 25 07:12:39 PM PDT 24
Finished Jun 25 07:13:17 PM PDT 24
Peak memory 248800 kb
Host smart-dcc86799-0f10-435b-a033-7b882e0afd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67869
385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.67869385
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1561373095
Short name T626
Test name
Test status
Simulation time 547872043 ps
CPU time 17.03 seconds
Started Jun 25 07:12:41 PM PDT 24
Finished Jun 25 07:13:19 PM PDT 24
Peak memory 249348 kb
Host smart-a69013a7-6f54-418c-8561-630242689e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15613
73095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1561373095
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.628172951
Short name T343
Test name
Test status
Simulation time 360256043 ps
CPU time 15.4 seconds
Started Jun 25 07:12:40 PM PDT 24
Finished Jun 25 07:13:16 PM PDT 24
Peak memory 255004 kb
Host smart-d55f1881-d6b4-42e3-ba63-252271c1ffbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62817
2951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.628172951
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3952452101
Short name T59
Test name
Test status
Simulation time 136638416897 ps
CPU time 2093.92 seconds
Started Jun 25 07:16:20 PM PDT 24
Finished Jun 25 07:51:19 PM PDT 24
Peak memory 273444 kb
Host smart-39c46a54-30f6-42ea-a6b4-125f2fe8a367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952452101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3952452101
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3187181001
Short name T584
Test name
Test status
Simulation time 4468326428 ps
CPU time 187.2 seconds
Started Jun 25 07:16:21 PM PDT 24
Finished Jun 25 07:19:32 PM PDT 24
Peak memory 257564 kb
Host smart-e1179d60-d07c-4fc5-93aa-e9e3908173cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871
81001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3187181001
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1121262322
Short name T423
Test name
Test status
Simulation time 278708339 ps
CPU time 23.57 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:16:46 PM PDT 24
Peak memory 256792 kb
Host smart-ea0f846b-da54-4865-8c29-3576ce4f294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11212
62322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1121262322
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.473706909
Short name T506
Test name
Test status
Simulation time 7534206410 ps
CPU time 599.37 seconds
Started Jun 25 07:16:32 PM PDT 24
Finished Jun 25 07:26:33 PM PDT 24
Peak memory 265772 kb
Host smart-e0e232bb-7947-44d4-ba3c-f16263ea598b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473706909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.473706909
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1121506176
Short name T564
Test name
Test status
Simulation time 20711789091 ps
CPU time 454.05 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:23:57 PM PDT 24
Peak memory 256028 kb
Host smart-2a882f6d-1dbb-4f4e-8469-7ca959f11cfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121506176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1121506176
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.847931396
Short name T533
Test name
Test status
Simulation time 1285770023 ps
CPU time 35.87 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:16:59 PM PDT 24
Peak memory 249276 kb
Host smart-55bc627a-fd87-491c-8807-8d889a6bd032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84793
1396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.847931396
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3010187813
Short name T242
Test name
Test status
Simulation time 185345493 ps
CPU time 5.69 seconds
Started Jun 25 07:16:20 PM PDT 24
Finished Jun 25 07:16:30 PM PDT 24
Peak memory 254748 kb
Host smart-a59d10ea-a929-44f6-b8b3-99e17b8e5073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30101
87813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3010187813
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3110480833
Short name T395
Test name
Test status
Simulation time 208327345 ps
CPU time 27.58 seconds
Started Jun 25 07:16:19 PM PDT 24
Finished Jun 25 07:16:51 PM PDT 24
Peak memory 256520 kb
Host smart-b13f72f3-74f3-4256-a704-bd5efdba8aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
80833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3110480833
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3999551241
Short name T41
Test name
Test status
Simulation time 32233604969 ps
CPU time 130.44 seconds
Started Jun 25 07:16:39 PM PDT 24
Finished Jun 25 07:18:53 PM PDT 24
Peak memory 257632 kb
Host smart-0c5b6f55-ecb6-4e0d-a1b7-ad89c8630d20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999551241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3999551241
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1629701500
Short name T483
Test name
Test status
Simulation time 124174911870 ps
CPU time 1411.84 seconds
Started Jun 25 07:16:34 PM PDT 24
Finished Jun 25 07:40:09 PM PDT 24
Peak memory 289496 kb
Host smart-3ae5f566-d9c5-411d-a2f9-0f68c81a10b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629701500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1629701500
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2134715329
Short name T118
Test name
Test status
Simulation time 16055165397 ps
CPU time 251.26 seconds
Started Jun 25 07:16:34 PM PDT 24
Finished Jun 25 07:20:48 PM PDT 24
Peak memory 257756 kb
Host smart-cbfe7e4c-4996-4c91-993e-0a2747169a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21347
15329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2134715329
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1681028458
Short name T635
Test name
Test status
Simulation time 3546365053 ps
CPU time 45.03 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:17:30 PM PDT 24
Peak memory 257000 kb
Host smart-6fcc4334-4fca-43cb-91cb-f4159551c22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16810
28458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1681028458
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2110003594
Short name T282
Test name
Test status
Simulation time 19394823311 ps
CPU time 877.29 seconds
Started Jun 25 07:16:43 PM PDT 24
Finished Jun 25 07:31:24 PM PDT 24
Peak memory 274016 kb
Host smart-e7552ae4-7e59-4418-9dc5-3c1c32f1076b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110003594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2110003594
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1039759884
Short name T499
Test name
Test status
Simulation time 122955604229 ps
CPU time 2195.04 seconds
Started Jun 25 07:16:33 PM PDT 24
Finished Jun 25 07:53:11 PM PDT 24
Peak memory 273816 kb
Host smart-f4b9eb00-f6f9-4a68-970b-e9c17dd0f2cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039759884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1039759884
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.634838047
Short name T601
Test name
Test status
Simulation time 8358069121 ps
CPU time 96.21 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:18:21 PM PDT 24
Peak memory 249416 kb
Host smart-2231e91e-7e2e-4ecb-9b34-b8f7db9a8bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634838047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.634838047
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3525066352
Short name T572
Test name
Test status
Simulation time 63350154 ps
CPU time 4.5 seconds
Started Jun 25 07:16:32 PM PDT 24
Finished Jun 25 07:16:39 PM PDT 24
Peak memory 249364 kb
Host smart-94472b3c-c544-4570-97cf-711a385a2d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35250
66352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3525066352
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3615866870
Short name T94
Test name
Test status
Simulation time 933955740 ps
CPU time 36.65 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:17:21 PM PDT 24
Peak memory 249260 kb
Host smart-08917df6-8771-470b-afef-d1baacd5f470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158
66870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3615866870
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1346527232
Short name T267
Test name
Test status
Simulation time 866308867 ps
CPU time 50.49 seconds
Started Jun 25 07:16:43 PM PDT 24
Finished Jun 25 07:17:37 PM PDT 24
Peak memory 249112 kb
Host smart-faa3a5a7-b195-47fd-9949-3334d8bc7dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13465
27232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1346527232
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3402298443
Short name T414
Test name
Test status
Simulation time 711667498 ps
CPU time 19.86 seconds
Started Jun 25 07:16:38 PM PDT 24
Finished Jun 25 07:17:01 PM PDT 24
Peak memory 257456 kb
Host smart-c8f6d938-018f-4e62-9623-34462053f468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34022
98443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3402298443
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.459582248
Short name T28
Test name
Test status
Simulation time 21258992257 ps
CPU time 348.57 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:22:34 PM PDT 24
Peak memory 257480 kb
Host smart-e5050653-88fb-4ba3-b7a9-1006b1427bfc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459582248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.459582248
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.786526969
Short name T450
Test name
Test status
Simulation time 63491724486 ps
CPU time 1043.79 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:34:09 PM PDT 24
Peak memory 273172 kb
Host smart-31859414-8e0e-4041-ad09-bd578432ff26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786526969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.786526969
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1791831321
Short name T220
Test name
Test status
Simulation time 3683196111 ps
CPU time 194.01 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:19:59 PM PDT 24
Peak memory 257552 kb
Host smart-dae60b9b-4c5f-462e-87ed-7f71be865cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17918
31321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1791831321
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.772456628
Short name T656
Test name
Test status
Simulation time 494938490 ps
CPU time 29.11 seconds
Started Jun 25 07:16:34 PM PDT 24
Finished Jun 25 07:17:07 PM PDT 24
Peak memory 248968 kb
Host smart-7ac1a899-7829-483a-addd-79ddb0f5d141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77245
6628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.772456628
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2758792668
Short name T633
Test name
Test status
Simulation time 39402765171 ps
CPU time 2672.39 seconds
Started Jun 25 07:16:32 PM PDT 24
Finished Jun 25 08:01:06 PM PDT 24
Peak memory 289412 kb
Host smart-1e5b60f4-0471-45ef-8e8d-75954f1834af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758792668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2758792668
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2560937404
Short name T696
Test name
Test status
Simulation time 34882196712 ps
CPU time 2393.45 seconds
Started Jun 25 07:16:42 PM PDT 24
Finished Jun 25 07:56:40 PM PDT 24
Peak memory 287896 kb
Host smart-a207a527-487d-4784-b7a6-4b6afc97a57a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560937404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2560937404
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2401443995
Short name T304
Test name
Test status
Simulation time 8986476661 ps
CPU time 386.77 seconds
Started Jun 25 07:16:40 PM PDT 24
Finished Jun 25 07:23:11 PM PDT 24
Peak memory 256348 kb
Host smart-bc6915af-d308-4551-9f83-117643ff4f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401443995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2401443995
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1971185214
Short name T465
Test name
Test status
Simulation time 79652003 ps
CPU time 5.69 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:16:51 PM PDT 24
Peak memory 249308 kb
Host smart-5e792891-d9c1-4ea1-ad12-cd9b3ba1ea13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19711
85214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1971185214
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.629791611
Short name T496
Test name
Test status
Simulation time 360553962 ps
CPU time 23.01 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:17:08 PM PDT 24
Peak memory 248760 kb
Host smart-bc65a5e6-892d-43d7-8e40-19a2b84ddfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62979
1611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.629791611
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2430644317
Short name T278
Test name
Test status
Simulation time 601767305 ps
CPU time 42.69 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:17:28 PM PDT 24
Peak memory 248896 kb
Host smart-00edfc8c-d3c9-4bcb-9fe7-081afd096fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
44317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2430644317
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2131661616
Short name T419
Test name
Test status
Simulation time 524989465 ps
CPU time 26.42 seconds
Started Jun 25 07:16:43 PM PDT 24
Finished Jun 25 07:17:13 PM PDT 24
Peak memory 256956 kb
Host smart-e4b005ea-89c8-4dca-967c-ecd5e09fbd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316
61616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2131661616
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2724038176
Short name T436
Test name
Test status
Simulation time 16814589647 ps
CPU time 116.13 seconds
Started Jun 25 07:16:41 PM PDT 24
Finished Jun 25 07:18:42 PM PDT 24
Peak memory 257616 kb
Host smart-8f8b6220-f85c-406e-b04e-84147cff89d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724038176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2724038176
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.62498170
Short name T50
Test name
Test status
Simulation time 1543372750 ps
CPU time 146.14 seconds
Started Jun 25 07:16:40 PM PDT 24
Finished Jun 25 07:19:10 PM PDT 24
Peak memory 257040 kb
Host smart-23aa441e-a4e3-4b10-abbe-c2cfb309ddb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62498
170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.62498170
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3510256367
Short name T105
Test name
Test status
Simulation time 881827884 ps
CPU time 52.53 seconds
Started Jun 25 07:16:42 PM PDT 24
Finished Jun 25 07:17:38 PM PDT 24
Peak memory 249340 kb
Host smart-dc90cb38-f8b5-4cfa-996a-e875aaf3a592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35102
56367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3510256367
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2045009017
Short name T409
Test name
Test status
Simulation time 19930567617 ps
CPU time 1338.66 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:39:29 PM PDT 24
Peak memory 273352 kb
Host smart-b4221a09-fbf3-4f87-a0ed-006e679c5bd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045009017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2045009017
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.580575912
Short name T298
Test name
Test status
Simulation time 21647270127 ps
CPU time 517.06 seconds
Started Jun 25 07:17:04 PM PDT 24
Finished Jun 25 07:25:46 PM PDT 24
Peak memory 249264 kb
Host smart-aafac15a-33d0-4e95-9aed-80f1ebc2572e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580575912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.580575912
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.650169638
Short name T64
Test name
Test status
Simulation time 661183478 ps
CPU time 28.81 seconds
Started Jun 25 07:16:33 PM PDT 24
Finished Jun 25 07:17:04 PM PDT 24
Peak memory 249252 kb
Host smart-6f57757e-7790-4cac-9fd5-45af254c9b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65016
9638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.650169638
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1971838085
Short name T95
Test name
Test status
Simulation time 795643789 ps
CPU time 47.41 seconds
Started Jun 25 07:16:43 PM PDT 24
Finished Jun 25 07:17:34 PM PDT 24
Peak memory 256912 kb
Host smart-f28c2946-8717-4683-9f14-5756abe09f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
38085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1971838085
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1245056825
Short name T398
Test name
Test status
Simulation time 268791542 ps
CPU time 33.72 seconds
Started Jun 25 07:17:04 PM PDT 24
Finished Jun 25 07:17:42 PM PDT 24
Peak memory 250236 kb
Host smart-92afb458-15fd-414f-8640-8aae2225b0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12450
56825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1245056825
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.633722752
Short name T115
Test name
Test status
Simulation time 611953188 ps
CPU time 21.17 seconds
Started Jun 25 07:16:37 PM PDT 24
Finished Jun 25 07:17:01 PM PDT 24
Peak memory 255984 kb
Host smart-6eda386c-9b5e-4c14-b8f0-32c144ce0607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63372
2752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.633722752
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1904898491
Short name T261
Test name
Test status
Simulation time 39052439004 ps
CPU time 2569.54 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 08:00:01 PM PDT 24
Peak memory 290020 kb
Host smart-b0174113-b7ac-4199-9ce7-91179194e044
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904898491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1904898491
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1919437598
Short name T425
Test name
Test status
Simulation time 148393672918 ps
CPU time 2914.01 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 08:05:46 PM PDT 24
Peak memory 290352 kb
Host smart-ddd41113-6600-474f-9a6f-c5d32fc8b942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919437598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1919437598
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3463847389
Short name T404
Test name
Test status
Simulation time 1005817305 ps
CPU time 76.48 seconds
Started Jun 25 07:17:04 PM PDT 24
Finished Jun 25 07:18:26 PM PDT 24
Peak memory 257512 kb
Host smart-fb9f3444-953b-4e02-8d25-d4899ff4b80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34638
47389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3463847389
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3293297513
Short name T474
Test name
Test status
Simulation time 581899656 ps
CPU time 42.79 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 07:17:54 PM PDT 24
Peak memory 256636 kb
Host smart-7d4056e0-f8e8-4111-acfd-54d1d79cc238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
97513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3293297513
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3517561289
Short name T324
Test name
Test status
Simulation time 23226179342 ps
CPU time 1810.72 seconds
Started Jun 25 07:17:07 PM PDT 24
Finished Jun 25 07:47:23 PM PDT 24
Peak memory 273948 kb
Host smart-6385322b-0785-4cd1-bfa4-13c5d55bd4e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517561289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3517561289
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2050473774
Short name T391
Test name
Test status
Simulation time 67078358107 ps
CPU time 1894.39 seconds
Started Jun 25 07:17:07 PM PDT 24
Finished Jun 25 07:48:48 PM PDT 24
Peak memory 290320 kb
Host smart-0af25e66-b278-4616-add1-01d37b6b24e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050473774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2050473774
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.278480832
Short name T292
Test name
Test status
Simulation time 13152961027 ps
CPU time 553.73 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:26:24 PM PDT 24
Peak memory 249404 kb
Host smart-df933991-dbca-4410-abd2-72dcb158c55d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278480832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.278480832
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1048948593
Short name T70
Test name
Test status
Simulation time 871637731 ps
CPU time 47.71 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 07:17:59 PM PDT 24
Peak memory 256748 kb
Host smart-716f90e2-f6a7-4277-b424-7e8f0a56372b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10489
48593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1048948593
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1642901759
Short name T580
Test name
Test status
Simulation time 960114913 ps
CPU time 27.54 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:17:38 PM PDT 24
Peak memory 248972 kb
Host smart-e9ca4eda-8fb4-4726-98a4-22078a66de26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16429
01759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1642901759
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1692643158
Short name T666
Test name
Test status
Simulation time 772089982 ps
CPU time 58.05 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 07:18:10 PM PDT 24
Peak memory 256592 kb
Host smart-b6de4a68-8804-4faa-b7f4-d3a989259276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16926
43158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1692643158
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2183521179
Short name T597
Test name
Test status
Simulation time 1662942514 ps
CPU time 54.16 seconds
Started Jun 25 07:17:07 PM PDT 24
Finished Jun 25 07:18:07 PM PDT 24
Peak memory 257168 kb
Host smart-377580fa-a4b7-4b18-9c65-ffc25da67bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
21179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2183521179
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1154913338
Short name T383
Test name
Test status
Simulation time 119422530 ps
CPU time 7.99 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:17:19 PM PDT 24
Peak memory 252872 kb
Host smart-f71d3f71-a3eb-480e-b738-769724eafd6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154913338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1154913338
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2771688278
Short name T397
Test name
Test status
Simulation time 186262848812 ps
CPU time 2760.76 seconds
Started Jun 25 07:17:22 PM PDT 24
Finished Jun 25 08:03:28 PM PDT 24
Peak memory 290432 kb
Host smart-943d92d4-3775-4e6b-af56-176a91e7a69b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771688278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2771688278
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2313304883
Short name T349
Test name
Test status
Simulation time 7323175637 ps
CPU time 118.54 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:19:20 PM PDT 24
Peak memory 256876 kb
Host smart-f62e1441-652e-4a7f-9a97-c4d352adaa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
04883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2313304883
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1423934060
Short name T489
Test name
Test status
Simulation time 72570719 ps
CPU time 7.76 seconds
Started Jun 25 07:17:06 PM PDT 24
Finished Jun 25 07:17:19 PM PDT 24
Peak memory 254956 kb
Host smart-73894081-d22a-4142-a004-e500fbc4867e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14239
34060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1423934060
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3728599028
Short name T313
Test name
Test status
Simulation time 27931889547 ps
CPU time 1465.87 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 07:41:50 PM PDT 24
Peak memory 290232 kb
Host smart-95597761-6658-4f92-9e08-bf81d87d318d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728599028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3728599028
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1752214438
Short name T695
Test name
Test status
Simulation time 37485864438 ps
CPU time 2731.53 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 08:03:00 PM PDT 24
Peak memory 290076 kb
Host smart-63cd9a80-cb1c-4258-ac8c-e5cdbcbc23ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752214438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1752214438
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3715174364
Short name T655
Test name
Test status
Simulation time 9599706532 ps
CPU time 416.49 seconds
Started Jun 25 07:17:18 PM PDT 24
Finished Jun 25 07:24:17 PM PDT 24
Peak memory 255868 kb
Host smart-8237c102-a9c7-4342-b780-8c99220f8a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715174364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3715174364
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1622406806
Short name T58
Test name
Test status
Simulation time 397123446 ps
CPU time 12.84 seconds
Started Jun 25 07:17:05 PM PDT 24
Finished Jun 25 07:17:23 PM PDT 24
Peak memory 249328 kb
Host smart-bb7ac59d-d9a7-44ff-80f1-284bca680a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16224
06806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1622406806
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2579610010
Short name T420
Test name
Test status
Simulation time 140970920 ps
CPU time 19.74 seconds
Started Jun 25 07:17:04 PM PDT 24
Finished Jun 25 07:17:29 PM PDT 24
Peak memory 248908 kb
Host smart-580d37e2-7741-427f-86a9-e0a4ce7e1104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
10010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2579610010
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1111457042
Short name T47
Test name
Test status
Simulation time 1004784448 ps
CPU time 15.56 seconds
Started Jun 25 07:17:30 PM PDT 24
Finished Jun 25 07:17:50 PM PDT 24
Peak memory 256692 kb
Host smart-7a737233-b960-4b57-9579-565c060f26ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11114
57042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1111457042
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1204826071
Short name T463
Test name
Test status
Simulation time 132555939 ps
CPU time 9.92 seconds
Started Jun 25 07:17:07 PM PDT 24
Finished Jun 25 07:17:22 PM PDT 24
Peak memory 255600 kb
Host smart-a0e20de9-0793-4787-823e-78e582201d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12048
26071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1204826071
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.10552321
Short name T258
Test name
Test status
Simulation time 41162429998 ps
CPU time 2000.67 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 07:50:45 PM PDT 24
Peak memory 298052 kb
Host smart-9c4e9b9f-2fc9-4682-807f-08b505aad47e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10552321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.10552321
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1980885151
Short name T286
Test name
Test status
Simulation time 110018655714 ps
CPU time 3538.08 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 08:16:28 PM PDT 24
Peak memory 288436 kb
Host smart-af47e499-6ba4-4aef-a25a-146624430c06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980885151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1980885151
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1412089626
Short name T232
Test name
Test status
Simulation time 7473883780 ps
CPU time 225.31 seconds
Started Jun 25 07:17:21 PM PDT 24
Finished Jun 25 07:21:10 PM PDT 24
Peak memory 257172 kb
Host smart-5f4dc445-82ca-4706-8327-b949efab1def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
89626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1412089626
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2451843268
Short name T577
Test name
Test status
Simulation time 261474678 ps
CPU time 22.31 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 07:17:45 PM PDT 24
Peak memory 255776 kb
Host smart-e72dffa6-6737-4ec3-9945-e24be32f5f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24518
43268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2451843268
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.360108037
Short name T588
Test name
Test status
Simulation time 42228370377 ps
CPU time 1525.25 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:42:47 PM PDT 24
Peak memory 290336 kb
Host smart-19652dc1-f5f1-498a-81c0-d3a9bed25607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360108037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.360108037
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1578733804
Short name T539
Test name
Test status
Simulation time 68075348196 ps
CPU time 1783.74 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:47:14 PM PDT 24
Peak memory 273432 kb
Host smart-62e9e254-58fa-45bb-b163-70199be2892c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578733804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1578733804
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.62812112
Short name T245
Test name
Test status
Simulation time 9259848241 ps
CPU time 389.31 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:23:51 PM PDT 24
Peak memory 249388 kb
Host smart-3742abf7-f287-421d-8cf6-3e74ff629b41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62812112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.62812112
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2740961532
Short name T74
Test name
Test status
Simulation time 425935842 ps
CPU time 13.89 seconds
Started Jun 25 07:17:22 PM PDT 24
Finished Jun 25 07:17:41 PM PDT 24
Peak memory 255192 kb
Host smart-926f867a-56dc-46f7-8168-2b9d0ae9e36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
61532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2740961532
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3690564180
Short name T388
Test name
Test status
Simulation time 1082473555 ps
CPU time 66.24 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:18:36 PM PDT 24
Peak memory 256804 kb
Host smart-04c2f3c9-a00c-4e11-b9f7-d1c32079f299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36905
64180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3690564180
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3163489948
Short name T435
Test name
Test status
Simulation time 2456606756 ps
CPU time 58.36 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 07:18:27 PM PDT 24
Peak memory 249916 kb
Host smart-4bf75657-26bd-4180-aaef-71fbb4ac10d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
89948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3163489948
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.602502517
Short name T624
Test name
Test status
Simulation time 575363882681 ps
CPU time 3554.12 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 08:16:44 PM PDT 24
Peak memory 290404 kb
Host smart-eda8e6e2-7ad8-41a1-a459-d8f29d4fa43e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602502517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.602502517
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.8319847
Short name T279
Test name
Test status
Simulation time 145650126874 ps
CPU time 3491.49 seconds
Started Jun 25 07:17:30 PM PDT 24
Finished Jun 25 08:15:45 PM PDT 24
Peak memory 322912 kb
Host smart-5d14a433-7f2f-44b9-bca0-027c93b1c71a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8319847 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.8319847
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3442171325
Short name T501
Test name
Test status
Simulation time 2606950288 ps
CPU time 126.74 seconds
Started Jun 25 07:17:30 PM PDT 24
Finished Jun 25 07:19:40 PM PDT 24
Peak memory 256896 kb
Host smart-7636e1b4-b145-4a9e-9fb1-9b50ec13713f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34421
71325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3442171325
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3953994749
Short name T368
Test name
Test status
Simulation time 2058942310 ps
CPU time 26.6 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 07:17:56 PM PDT 24
Peak memory 256592 kb
Host smart-69ef9d50-6f73-4ab6-b5d6-c71d4e68f022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39539
94749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3953994749
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.541638532
Short name T322
Test name
Test status
Simulation time 181186930512 ps
CPU time 2418.35 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:57:49 PM PDT 24
Peak memory 282112 kb
Host smart-b733bb94-b88e-45fa-bb40-d980ae8e2fd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541638532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.541638532
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3647439633
Short name T42
Test name
Test status
Simulation time 28204285256 ps
CPU time 1331.95 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 07:39:36 PM PDT 24
Peak memory 286052 kb
Host smart-ae52372f-ec79-4974-95ee-07885c951404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647439633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3647439633
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.492271048
Short name T211
Test name
Test status
Simulation time 942600570 ps
CPU time 22.48 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:17:45 PM PDT 24
Peak memory 255832 kb
Host smart-b758a2ac-09da-4769-a467-120eb477dced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49227
1048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.492271048
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2880845489
Short name T104
Test name
Test status
Simulation time 205017220 ps
CPU time 14.92 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 07:17:43 PM PDT 24
Peak memory 255084 kb
Host smart-4dbc32bc-2a1d-4249-902e-5baac04561fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28808
45489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2880845489
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2596349362
Short name T461
Test name
Test status
Simulation time 1037906479 ps
CPU time 27.31 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 07:17:55 PM PDT 24
Peak memory 249364 kb
Host smart-5cdba5d0-4573-4d0c-a543-395e9965f73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25963
49362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2596349362
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1212318
Short name T417
Test name
Test status
Simulation time 336338247 ps
CPU time 12.97 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 07:17:40 PM PDT 24
Peak memory 249340 kb
Host smart-8a346923-70cb-469a-ace0-bdef7ed44215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12123
18 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1212318
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1860768524
Short name T632
Test name
Test status
Simulation time 18323061859 ps
CPU time 1478.72 seconds
Started Jun 25 07:17:22 PM PDT 24
Finished Jun 25 07:42:06 PM PDT 24
Peak memory 289924 kb
Host smart-1607d075-ad28-4314-8eec-f2d35055fce3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860768524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1860768524
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4195778563
Short name T228
Test name
Test status
Simulation time 314296254891 ps
CPU time 1688.03 seconds
Started Jun 25 07:17:22 PM PDT 24
Finished Jun 25 07:45:35 PM PDT 24
Peak memory 286420 kb
Host smart-86877138-5631-41cf-b169-4e02badd046b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195778563 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4195778563
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3168080166
Short name T566
Test name
Test status
Simulation time 92252522569 ps
CPU time 2823.75 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 08:04:28 PM PDT 24
Peak memory 285136 kb
Host smart-15c654d8-6e78-4066-928b-8a4811b03875
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168080166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3168080166
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1802600460
Short name T567
Test name
Test status
Simulation time 1846685181 ps
CPU time 95.12 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 07:19:04 PM PDT 24
Peak memory 257504 kb
Host smart-38b81e6c-cc03-4a95-ac33-ba0eb1928642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18026
00460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1802600460
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2240432051
Short name T553
Test name
Test status
Simulation time 203790886 ps
CPU time 11.79 seconds
Started Jun 25 07:17:20 PM PDT 24
Finished Jun 25 07:17:34 PM PDT 24
Peak memory 254564 kb
Host smart-6e64aec4-7e4a-4f70-bb16-d3bc503a2e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
32051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2240432051
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2888684761
Short name T325
Test name
Test status
Simulation time 25871903002 ps
CPU time 920.26 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 07:32:48 PM PDT 24
Peak memory 273340 kb
Host smart-92341044-7828-4f0f-be1f-3f741f2eaf36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888684761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2888684761
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1780399570
Short name T511
Test name
Test status
Simulation time 21948375854 ps
CPU time 894.49 seconds
Started Jun 25 07:17:30 PM PDT 24
Finished Jun 25 07:32:28 PM PDT 24
Peak memory 284032 kb
Host smart-f59a6521-ced2-48b3-bda2-3dc25c115b78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780399570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1780399570
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.54897253
Short name T303
Test name
Test status
Simulation time 6001437200 ps
CPU time 250.61 seconds
Started Jun 25 07:17:19 PM PDT 24
Finished Jun 25 07:21:33 PM PDT 24
Peak memory 249196 kb
Host smart-b38cde92-331f-4395-a470-ddacb83de8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54897253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.54897253
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3588976618
Short name T625
Test name
Test status
Simulation time 435272186 ps
CPU time 15.22 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:17:45 PM PDT 24
Peak memory 249252 kb
Host smart-6f1ec41b-385d-4131-9b0f-485db018d379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35889
76618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3588976618
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2689251581
Short name T673
Test name
Test status
Simulation time 207634184 ps
CPU time 19.5 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:17:49 PM PDT 24
Peak memory 257444 kb
Host smart-9090120b-b39c-444e-b785-7013f5846dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
51581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2689251581
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2371797063
Short name T266
Test name
Test status
Simulation time 991661428 ps
CPU time 30.99 seconds
Started Jun 25 07:17:30 PM PDT 24
Finished Jun 25 07:18:05 PM PDT 24
Peak memory 256812 kb
Host smart-b00ed9a6-ce57-4766-a1ec-8d48a6610e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23717
97063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2371797063
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2903334802
Short name T471
Test name
Test status
Simulation time 184287500 ps
CPU time 16.02 seconds
Started Jun 25 07:17:22 PM PDT 24
Finished Jun 25 07:17:42 PM PDT 24
Peak memory 257456 kb
Host smart-766b260d-a8e5-484f-9084-1e328679fbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29033
34802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2903334802
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3514018658
Short name T468
Test name
Test status
Simulation time 170416838351 ps
CPU time 3031.79 seconds
Started Jun 25 07:17:35 PM PDT 24
Finished Jun 25 08:08:11 PM PDT 24
Peak memory 288208 kb
Host smart-ead94b36-d38b-4c99-95cf-35fc3c728b0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514018658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3514018658
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2811487446
Short name T352
Test name
Test status
Simulation time 984445241 ps
CPU time 61.2 seconds
Started Jun 25 07:17:33 PM PDT 24
Finished Jun 25 07:18:38 PM PDT 24
Peak memory 257012 kb
Host smart-2e7c8950-61c9-4704-a624-0aee7753c7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
87446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2811487446
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3745453639
Short name T480
Test name
Test status
Simulation time 1301055948 ps
CPU time 22.18 seconds
Started Jun 25 07:17:24 PM PDT 24
Finished Jun 25 07:17:51 PM PDT 24
Peak memory 255904 kb
Host smart-9d1e593e-91a2-4c02-a330-248dba024266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
53639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3745453639
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.356008013
Short name T257
Test name
Test status
Simulation time 20144805622 ps
CPU time 1169.82 seconds
Started Jun 25 07:17:44 PM PDT 24
Finished Jun 25 07:37:17 PM PDT 24
Peak memory 273276 kb
Host smart-d9f14f42-1989-451a-873a-c3dd2e8397ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356008013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.356008013
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1978634395
Short name T362
Test name
Test status
Simulation time 24131882249 ps
CPU time 1604.9 seconds
Started Jun 25 07:17:33 PM PDT 24
Finished Jun 25 07:44:22 PM PDT 24
Peak memory 273920 kb
Host smart-490006d2-c0b2-48ce-a2f2-0c2ada180a9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978634395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1978634395
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4233479041
Short name T255
Test name
Test status
Simulation time 44869669032 ps
CPU time 493.95 seconds
Started Jun 25 07:17:33 PM PDT 24
Finished Jun 25 07:25:51 PM PDT 24
Peak memory 249416 kb
Host smart-541e6db9-2afc-46f6-840c-5779cda88c58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233479041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4233479041
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3599486673
Short name T412
Test name
Test status
Simulation time 1587094592 ps
CPU time 35.51 seconds
Started Jun 25 07:17:26 PM PDT 24
Finished Jun 25 07:18:06 PM PDT 24
Peak memory 256716 kb
Host smart-20115c21-7fbf-45d2-a84d-61cc848e476e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35994
86673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3599486673
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.454637869
Short name T530
Test name
Test status
Simulation time 533834804 ps
CPU time 22.99 seconds
Started Jun 25 07:17:25 PM PDT 24
Finished Jun 25 07:17:52 PM PDT 24
Peak memory 249232 kb
Host smart-26a4a049-9cd5-4e38-a67a-112ba2066417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45463
7869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.454637869
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3197544709
Short name T52
Test name
Test status
Simulation time 2650199718 ps
CPU time 33.69 seconds
Started Jun 25 07:17:44 PM PDT 24
Finished Jun 25 07:18:20 PM PDT 24
Peak memory 249452 kb
Host smart-4bb47f81-0ef2-4839-b4bb-d53f16e91d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
44709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3197544709
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.167849555
Short name T406
Test name
Test status
Simulation time 3108394458 ps
CPU time 45.9 seconds
Started Jun 25 07:17:23 PM PDT 24
Finished Jun 25 07:18:13 PM PDT 24
Peak memory 257628 kb
Host smart-487e6287-5b97-42a5-a57b-1eb2422cf136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
9555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.167849555
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3018009308
Short name T557
Test name
Test status
Simulation time 416411197115 ps
CPU time 2635.64 seconds
Started Jun 25 07:17:34 PM PDT 24
Finished Jun 25 08:01:34 PM PDT 24
Peak memory 289784 kb
Host smart-332eefb9-8097-4048-ad43-d01dec4538b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018009308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3018009308
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.212562541
Short name T33
Test name
Test status
Simulation time 243049842390 ps
CPU time 4070.17 seconds
Started Jun 25 07:17:34 PM PDT 24
Finished Jun 25 08:25:29 PM PDT 24
Peak memory 306280 kb
Host smart-0853dd85-b1d2-4bdf-8368-e6ba8d1e0663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212562541 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.212562541
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3444431428
Short name T195
Test name
Test status
Simulation time 124501861 ps
CPU time 4.63 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:13:15 PM PDT 24
Peak memory 249496 kb
Host smart-5ec47c2d-ab6b-4198-a1c8-cb8426ae990c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3444431428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3444431428
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3280986472
Short name T682
Test name
Test status
Simulation time 18953140838 ps
CPU time 1259.01 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:34:09 PM PDT 24
Peak memory 273900 kb
Host smart-ec90ed76-8840-44b9-b18b-415a3ed36c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280986472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3280986472
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3627658567
Short name T541
Test name
Test status
Simulation time 4176811325 ps
CPU time 49.01 seconds
Started Jun 25 07:12:54 PM PDT 24
Finished Jun 25 07:14:00 PM PDT 24
Peak memory 249420 kb
Host smart-c92396c0-db79-4fea-9d89-6d582ca35c66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3627658567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3627658567
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3278701111
Short name T452
Test name
Test status
Simulation time 56353409 ps
CPU time 5.01 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:13:15 PM PDT 24
Peak memory 240564 kb
Host smart-985fb1bc-c2dc-4201-a790-530d0a19d9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787
01111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3278701111
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2684862429
Short name T653
Test name
Test status
Simulation time 1219695102 ps
CPU time 73 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:14:24 PM PDT 24
Peak memory 257012 kb
Host smart-5b35918f-bd15-429b-ad05-54f607b66522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26848
62429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2684862429
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.405035388
Short name T330
Test name
Test status
Simulation time 50935798999 ps
CPU time 1132.73 seconds
Started Jun 25 07:12:54 PM PDT 24
Finished Jun 25 07:32:04 PM PDT 24
Peak memory 289400 kb
Host smart-073494c4-ccf7-44a7-914a-569dc4285e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405035388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.405035388
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3953654063
Short name T442
Test name
Test status
Simulation time 57762737611 ps
CPU time 2103.3 seconds
Started Jun 25 07:12:55 PM PDT 24
Finished Jun 25 07:48:15 PM PDT 24
Peak memory 282216 kb
Host smart-7eb52a8e-495e-4abb-a7d3-7457bc45dd69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953654063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3953654063
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1604398250
Short name T600
Test name
Test status
Simulation time 4062888103 ps
CPU time 180.98 seconds
Started Jun 25 07:12:55 PM PDT 24
Finished Jun 25 07:16:13 PM PDT 24
Peak memory 255724 kb
Host smart-5ff1457b-96b6-42c9-a3fc-1c73702bd482
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604398250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1604398250
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1273346032
Short name T443
Test name
Test status
Simulation time 4338174011 ps
CPU time 27.36 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:13:37 PM PDT 24
Peak memory 256796 kb
Host smart-5dac517d-729c-4aba-9f00-e1ed7bf2e304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12733
46032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1273346032
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.461995750
Short name T642
Test name
Test status
Simulation time 867817201 ps
CPU time 53.56 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:14:04 PM PDT 24
Peak memory 249328 kb
Host smart-d2b283fc-e2a9-401a-9348-6d5561ef6028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46199
5750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.461995750
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1696254466
Short name T366
Test name
Test status
Simulation time 236261973 ps
CPU time 14.83 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:13:25 PM PDT 24
Peak memory 256924 kb
Host smart-ff3fcf2d-211d-4a9b-b613-8d33024a73b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16962
54466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1696254466
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2482734651
Short name T441
Test name
Test status
Simulation time 405330194 ps
CPU time 8.66 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:13:19 PM PDT 24
Peak memory 253464 kb
Host smart-99fcf669-4129-4827-bc67-171f034175d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24827
34651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2482734651
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3563208543
Short name T375
Test name
Test status
Simulation time 1209589336 ps
CPU time 72.04 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:14:22 PM PDT 24
Peak memory 257520 kb
Host smart-888cc07d-b0df-4d45-b3fb-c23728bf1573
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563208543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3563208543
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1027414345
Short name T277
Test name
Test status
Simulation time 402895902985 ps
CPU time 2430.6 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:53:41 PM PDT 24
Peak memory 287168 kb
Host smart-216de9c8-b5ff-49d5-9eb6-4865282e1661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027414345 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1027414345
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2680987024
Short name T208
Test name
Test status
Simulation time 37763250 ps
CPU time 2.3 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:13:20 PM PDT 24
Peak memory 249560 kb
Host smart-3af8a428-c6f9-4a2b-8187-bfa10bb12aeb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2680987024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2680987024
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1278155043
Short name T559
Test name
Test status
Simulation time 119470469650 ps
CPU time 2160.28 seconds
Started Jun 25 07:13:02 PM PDT 24
Finished Jun 25 07:49:16 PM PDT 24
Peak memory 286648 kb
Host smart-a2b68d52-507f-4cc4-9217-fbdfb65efad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278155043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1278155043
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1507612487
Short name T658
Test name
Test status
Simulation time 646113519 ps
CPU time 29.3 seconds
Started Jun 25 07:13:04 PM PDT 24
Finished Jun 25 07:13:46 PM PDT 24
Peak memory 249340 kb
Host smart-6951abd5-eb62-4a4c-8df5-a0e21742167f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1507612487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1507612487
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2730066089
Short name T497
Test name
Test status
Simulation time 1476978087 ps
CPU time 135.32 seconds
Started Jun 25 07:13:02 PM PDT 24
Finished Jun 25 07:15:31 PM PDT 24
Peak memory 256576 kb
Host smart-5974e71e-c4cc-4c00-b4d3-ae6522ba378e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27300
66089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2730066089
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3580261875
Short name T21
Test name
Test status
Simulation time 253544319 ps
CPU time 15.76 seconds
Started Jun 25 07:13:04 PM PDT 24
Finished Jun 25 07:13:32 PM PDT 24
Peak memory 249260 kb
Host smart-8b8ba69a-f28d-458d-9e65-420c425b085c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35802
61875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3580261875
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2673132570
Short name T327
Test name
Test status
Simulation time 138212310261 ps
CPU time 2364.03 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:52:41 PM PDT 24
Peak memory 283360 kb
Host smart-d0c57bda-f590-46ed-ac63-11aa205cc0aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673132570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2673132570
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.59751896
Short name T212
Test name
Test status
Simulation time 19772775044 ps
CPU time 1424.38 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:37:01 PM PDT 24
Peak memory 273996 kb
Host smart-4597f0f7-036a-4640-88f9-10bdc832048e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59751896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.59751896
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.280104862
Short name T306
Test name
Test status
Simulation time 8357938065 ps
CPU time 361.63 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:19:18 PM PDT 24
Peak memory 249080 kb
Host smart-a036665e-2310-4581-82e0-86773e79cb04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280104862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.280104862
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1000773035
Short name T680
Test name
Test status
Simulation time 237930219 ps
CPU time 4.09 seconds
Started Jun 25 07:12:52 PM PDT 24
Finished Jun 25 07:13:14 PM PDT 24
Peak memory 241040 kb
Host smart-248c2a2b-194e-47ca-a065-58adaff9862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10007
73035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1000773035
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4026335103
Short name T493
Test name
Test status
Simulation time 201920315 ps
CPU time 5.79 seconds
Started Jun 25 07:13:05 PM PDT 24
Finished Jun 25 07:13:23 PM PDT 24
Peak memory 252052 kb
Host smart-64f90a06-5cce-4493-a7cf-43f6fe598b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
35103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4026335103
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1123251636
Short name T505
Test name
Test status
Simulation time 1066296980 ps
CPU time 19.18 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:13:36 PM PDT 24
Peak memory 248796 kb
Host smart-d3e9c237-f4f0-4c5a-83ab-bc21bd5f6a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11232
51636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1123251636
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3518502727
Short name T518
Test name
Test status
Simulation time 353742867 ps
CPU time 32.25 seconds
Started Jun 25 07:12:53 PM PDT 24
Finished Jun 25 07:13:43 PM PDT 24
Peak memory 249304 kb
Host smart-f67d6286-1cc7-4fef-b786-5181e4e6946b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
02727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3518502727
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.296862676
Short name T460
Test name
Test status
Simulation time 19479283274 ps
CPU time 1097.41 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:31:34 PM PDT 24
Peak memory 273988 kb
Host smart-c5e9e1fc-045d-44fd-8744-a1cdedb924c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296862676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.296862676
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.303814000
Short name T280
Test name
Test status
Simulation time 25374110149 ps
CPU time 1746.87 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:42:23 PM PDT 24
Peak memory 289140 kb
Host smart-4e176fe7-5bd1-41bb-8651-d57f597708c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303814000 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.303814000
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3930060960
Short name T488
Test name
Test status
Simulation time 15715932441 ps
CPU time 1291.79 seconds
Started Jun 25 07:13:03 PM PDT 24
Finished Jun 25 07:34:49 PM PDT 24
Peak memory 289268 kb
Host smart-97a8eeac-6d57-48ce-8461-1b46264dfea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930060960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3930060960
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3651456222
Short name T498
Test name
Test status
Simulation time 5633877194 ps
CPU time 26.42 seconds
Started Jun 25 07:13:09 PM PDT 24
Finished Jun 25 07:13:46 PM PDT 24
Peak memory 249444 kb
Host smart-37457e6c-2d2f-49a0-94d5-8fe75681ff69
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3651456222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3651456222
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2759932456
Short name T484
Test name
Test status
Simulation time 16819421803 ps
CPU time 211.66 seconds
Started Jun 25 07:13:04 PM PDT 24
Finished Jun 25 07:16:49 PM PDT 24
Peak memory 256948 kb
Host smart-c2651805-3ad2-4a3b-a71a-e4a078783b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
32456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2759932456
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2302580803
Short name T526
Test name
Test status
Simulation time 1261221623 ps
CPU time 35.63 seconds
Started Jun 25 07:13:05 PM PDT 24
Finished Jun 25 07:13:53 PM PDT 24
Peak memory 249336 kb
Host smart-58fc00bc-f048-4f43-9ad0-07e3a57f5772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
80803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2302580803
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3730195936
Short name T295
Test name
Test status
Simulation time 149720476433 ps
CPU time 2125.26 seconds
Started Jun 25 07:13:10 PM PDT 24
Finished Jun 25 07:48:46 PM PDT 24
Peak memory 273884 kb
Host smart-a16d5309-853e-4ac2-8a66-683a80abc198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730195936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3730195936
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.833826404
Short name T357
Test name
Test status
Simulation time 8980861092 ps
CPU time 980.74 seconds
Started Jun 25 07:13:09 PM PDT 24
Finished Jun 25 07:29:40 PM PDT 24
Peak memory 285324 kb
Host smart-7878092b-d400-4c1f-89a9-f20bb333b3ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833826404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.833826404
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2964176985
Short name T305
Test name
Test status
Simulation time 59088163402 ps
CPU time 246.81 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:17:25 PM PDT 24
Peak memory 249412 kb
Host smart-e4ce01b6-8de6-46bf-9665-127793c36e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964176985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2964176985
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1465708342
Short name T27
Test name
Test status
Simulation time 1856347641 ps
CPU time 31.07 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:13:49 PM PDT 24
Peak memory 256788 kb
Host smart-08865691-2fdd-446d-b65e-a3e172dc24ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14657
08342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1465708342
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1437887078
Short name T410
Test name
Test status
Simulation time 2131985771 ps
CPU time 10.83 seconds
Started Jun 25 07:13:05 PM PDT 24
Finished Jun 25 07:13:28 PM PDT 24
Peak memory 256828 kb
Host smart-2296ffd2-71a0-4128-90b2-85716da4101e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14378
87078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1437887078
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.730388847
Short name T361
Test name
Test status
Simulation time 7517306443 ps
CPU time 60.8 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:14:19 PM PDT 24
Peak memory 257452 kb
Host smart-5babe814-545c-4b10-9c39-685a738e7cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73038
8847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.730388847
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2477105516
Short name T529
Test name
Test status
Simulation time 228930731 ps
CPU time 17.58 seconds
Started Jun 25 07:13:07 PM PDT 24
Finished Jun 25 07:13:37 PM PDT 24
Peak memory 249304 kb
Host smart-1e4fa937-0633-4d61-9f57-d37537c23f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24771
05516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2477105516
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1112217711
Short name T72
Test name
Test status
Simulation time 748712261 ps
CPU time 18.48 seconds
Started Jun 25 07:13:05 PM PDT 24
Finished Jun 25 07:13:36 PM PDT 24
Peak memory 249356 kb
Host smart-2f83ef68-7713-44bc-83d7-2393a05ae97d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112217711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1112217711
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2189206048
Short name T229
Test name
Test status
Simulation time 24065199808 ps
CPU time 1626.81 seconds
Started Jun 25 07:13:07 PM PDT 24
Finished Jun 25 07:40:25 PM PDT 24
Peak memory 286248 kb
Host smart-8ec87848-7818-4451-896a-473f25a642ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189206048 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2189206048
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2565040924
Short name T203
Test name
Test status
Simulation time 32613085 ps
CPU time 3.31 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:13:29 PM PDT 24
Peak memory 249600 kb
Host smart-4971a0b4-c695-4f0d-b163-86de3f2238a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2565040924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2565040924
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2537810668
Short name T405
Test name
Test status
Simulation time 70037401900 ps
CPU time 2333.82 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:52:18 PM PDT 24
Peak memory 287704 kb
Host smart-7d7f822a-8bed-4cca-b800-9883d04db9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537810668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2537810668
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1531504455
Short name T700
Test name
Test status
Simulation time 3794663351 ps
CPU time 44.64 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:14:09 PM PDT 24
Peak memory 249420 kb
Host smart-78b4de04-8b2d-435b-bf7a-a99633a5569b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1531504455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1531504455
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3024407735
Short name T447
Test name
Test status
Simulation time 4170778469 ps
CPU time 288.85 seconds
Started Jun 25 07:13:18 PM PDT 24
Finished Jun 25 07:18:15 PM PDT 24
Peak memory 252500 kb
Host smart-0d807a7a-ae2e-4761-a4ac-473908580b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
07735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3024407735
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2556869414
Short name T490
Test name
Test status
Simulation time 648737695 ps
CPU time 42.75 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:14:07 PM PDT 24
Peak memory 248948 kb
Host smart-5feb1ba1-fb2f-43f4-ba60-856a71fa0860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568
69414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2556869414
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1078174814
Short name T684
Test name
Test status
Simulation time 17538684751 ps
CPU time 1165.84 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:32:50 PM PDT 24
Peak memory 290292 kb
Host smart-266f7cef-92ad-4690-a722-e08f8573c2f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078174814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1078174814
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.72927673
Short name T312
Test name
Test status
Simulation time 14363384672 ps
CPU time 258.5 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:17:43 PM PDT 24
Peak memory 249400 kb
Host smart-e3e8a82d-1569-4a2f-b677-106a91b9ccf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72927673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.72927673
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1625826442
Short name T668
Test name
Test status
Simulation time 332912571 ps
CPU time 35.4 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:13:53 PM PDT 24
Peak memory 249256 kb
Host smart-717dc5d6-6b5b-4b65-94df-f45ff194d401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16258
26442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1625826442
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2081558755
Short name T32
Test name
Test status
Simulation time 1172837305 ps
CPU time 41.73 seconds
Started Jun 25 07:13:06 PM PDT 24
Finished Jun 25 07:14:00 PM PDT 24
Peak memory 248380 kb
Host smart-5b355d1d-dde4-46ff-8997-a499b34078c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
58755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2081558755
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2413220724
Short name T82
Test name
Test status
Simulation time 1341282509 ps
CPU time 26.42 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:13:50 PM PDT 24
Peak memory 256072 kb
Host smart-1c85a8eb-cf9a-42e5-b709-f99539f65fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
20724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2413220724
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.4245336738
Short name T353
Test name
Test status
Simulation time 471171156 ps
CPU time 26.54 seconds
Started Jun 25 07:13:05 PM PDT 24
Finished Jun 25 07:13:44 PM PDT 24
Peak memory 256544 kb
Host smart-93dc50da-8782-47f6-a419-a75e91275194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
36738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.4245336738
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2182568019
Short name T504
Test name
Test status
Simulation time 16944659118 ps
CPU time 1740.31 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:42:26 PM PDT 24
Peak memory 289772 kb
Host smart-0de7104d-79e0-4a85-9be2-62f3ee8d86c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182568019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2182568019
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1807581200
Short name T206
Test name
Test status
Simulation time 42039998 ps
CPU time 3.57 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:13:29 PM PDT 24
Peak memory 249624 kb
Host smart-affc6bb6-5ddd-41d7-8a6a-358dc357ab54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1807581200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1807581200
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.364754318
Short name T433
Test name
Test status
Simulation time 81200377669 ps
CPU time 966.22 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:29:31 PM PDT 24
Peak memory 273852 kb
Host smart-4c7c6619-cfc2-4ec1-8574-1e824cad93cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364754318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.364754318
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1736483665
Short name T430
Test name
Test status
Simulation time 2242161952 ps
CPU time 46.75 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:14:11 PM PDT 24
Peak memory 249420 kb
Host smart-9434a6f0-b21c-4b8a-8ab7-d10079250d0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1736483665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1736483665
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.410615280
Short name T374
Test name
Test status
Simulation time 1516524240 ps
CPU time 75.62 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:14:40 PM PDT 24
Peak memory 256564 kb
Host smart-33f1ed83-498b-40d1-8686-8f0f56e438e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061
5280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.410615280
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1245142326
Short name T590
Test name
Test status
Simulation time 706073798 ps
CPU time 20.39 seconds
Started Jun 25 07:13:15 PM PDT 24
Finished Jun 25 07:13:43 PM PDT 24
Peak memory 257528 kb
Host smart-088b3ed2-c0f6-406d-a6e7-95f5bb228dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12451
42326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1245142326
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2153596620
Short name T630
Test name
Test status
Simulation time 59961033690 ps
CPU time 1309.3 seconds
Started Jun 25 07:13:17 PM PDT 24
Finished Jun 25 07:35:15 PM PDT 24
Peak memory 284596 kb
Host smart-36d99e85-4d9f-449e-be7a-cc14f78b1eae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153596620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2153596620
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1752124184
Short name T565
Test name
Test status
Simulation time 29631629355 ps
CPU time 2022.23 seconds
Started Jun 25 07:13:19 PM PDT 24
Finished Jun 25 07:47:09 PM PDT 24
Peak memory 274020 kb
Host smart-9cec1e82-44b0-4f8c-9c7e-9e9f5d9ed7e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752124184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1752124184
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2020462208
Short name T294
Test name
Test status
Simulation time 10634663448 ps
CPU time 404.24 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:20:09 PM PDT 24
Peak memory 249136 kb
Host smart-8e613bad-fe57-40a7-b4c8-9570e8125029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020462208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2020462208
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3169758216
Short name T538
Test name
Test status
Simulation time 752411377 ps
CPU time 12.99 seconds
Started Jun 25 07:13:14 PM PDT 24
Finished Jun 25 07:13:36 PM PDT 24
Peak memory 249256 kb
Host smart-99c67b21-ed9f-4b3c-97f4-7cb462c8d53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
58216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3169758216
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3488123794
Short name T464
Test name
Test status
Simulation time 287283051 ps
CPU time 5.24 seconds
Started Jun 25 07:13:18 PM PDT 24
Finished Jun 25 07:13:32 PM PDT 24
Peak memory 240328 kb
Host smart-bc4b9fa1-6bc6-4f42-80e8-624ad12c59ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34881
23794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3488123794
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2038969494
Short name T608
Test name
Test status
Simulation time 58466191 ps
CPU time 7.94 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:13:33 PM PDT 24
Peak memory 248804 kb
Host smart-d21fd4ee-a523-4a64-8ad4-2327ae9d7939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389
69494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2038969494
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4208671227
Short name T466
Test name
Test status
Simulation time 2322770884 ps
CPU time 37.07 seconds
Started Jun 25 07:13:16 PM PDT 24
Finished Jun 25 07:14:02 PM PDT 24
Peak memory 256624 kb
Host smart-28b2a59c-47e6-4be7-aac1-cb6ffa3fc953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42086
71227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4208671227
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2427748787
Short name T576
Test name
Test status
Simulation time 28320690200 ps
CPU time 1550.84 seconds
Started Jun 25 07:13:19 PM PDT 24
Finished Jun 25 07:39:18 PM PDT 24
Peak memory 289640 kb
Host smart-d686a5cc-2d43-4288-9f85-409eea698cb9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427748787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2427748787
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%