Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	99145	1			T1	7		T5	66		T17	135
class_i[0x1]	61530	1			T1	7		T8	732		T17	1623
class_i[0x2]	56104	1			T17	26		T40	2		T20	241
class_i[0x3]	64128	1			T1	13		T17	2980		T40	4

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71707	1			T1	7		T5	15		T8	12
alert[0x1]	70654	1			T1	8		T5	7		T8	10
alert[0x2]	69586	1			T1	12		T5	21		T8	690
alert[0x3]	68960	1			T5	23		T8	20		T17	1170

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

280639

1

T1

27

T5

66

T8

732

esc_ping_fail

268

1

T40

3

T61

3

T41

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71625	1			T1	7		T5	15		T8	12
esc_integrity_fail	alert[0x1]	70591	1			T1	8		T5	7		T8	10
esc_integrity_fail	alert[0x2]	69526	1			T1	12		T5	21		T8	690
esc_integrity_fail	alert[0x3]	68897	1			T5	23		T8	20		T17	1170
esc_ping_fail	alert[0x0]	82	1			T40	1		T61	1		T41	1
esc_ping_fail	alert[0x1]	63	1			T41	1		T286	1		T287	4
esc_ping_fail	alert[0x2]	60	1			T40	1		T61	1		T41	2
esc_ping_fail	alert[0x3]	63	1			T40	1		T61	1		T41	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	99055	1			T1	7		T5	66		T17	135
esc_integrity_fail	class_i[0x1]	61473	1			T1	7		T8	732		T17	1623
esc_integrity_fail	class_i[0x2]	56033	1			T17	26		T40	2		T20	241
esc_integrity_fail	class_i[0x3]	64078	1			T1	13		T17	2980		T40	2
esc_ping_fail	class_i[0x0]	90	1			T40	1		T61	1		T41	1
esc_ping_fail	class_i[0x1]	57	1			T61	2		T41	5		T286	1
esc_ping_fail	class_i[0x2]	71	1			T286	3		T288	1		T322	1
esc_ping_fail	class_i[0x3]	50	1			T40	2		T286	3		T273	1