Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	662190782	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	662190782	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	662190782	662008565	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	662190782	662008565	0	0
tb.dut.EdnKnownO_A	0	0	662190782	662008565	0	0
tb.dut.EscPKnownO_A	0	0	662190782	662008565	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	662190782	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	662190782	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	662190782	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	662190782	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	662190782	90	0	0
tb.dut.IrqAKnownO_A	0	0	662190782	662008565	0	0
tb.dut.IrqBKnownO_A	0	0	662190782	662008565	0	0
tb.dut.IrqCKnownO_A	0	0	662190782	662008565	0	0
tb.dut.IrqDKnownO_A	0	0	662190782	662008565	0	0
tb.dut.TlAReadyKnownO_A	0	0	662190782	662008565	0	0
tb.dut.TlDValidKnownO_A	0	0	662190782	662008565	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	684949674	2839879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	684949674	11078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	684949674	11381	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	684949674	10947	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	684949674	11036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	684949674	11354	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	684949674	11190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	684949674	11934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	684949674	11292	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	684949674	12214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	684949674	11959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	684949674	11251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	684949674	11485	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	684949674	11389	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	684949674	11387	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	684949674	11460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	684949674	11191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	684949674	11096	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	684949674	11002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	684949674	11869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	684949674	11256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	684949674	11958	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	684949674	11035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	684949674	11722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	684949674	10990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	684949674	10643	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	684949674	11640	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	684949674	11180	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	684949674	11401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	684949674	12004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	684949674	11117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	684949674	10944	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	684949674	11868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	684949674	11239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	684949674	11179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	684949674	12050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	684949674	11078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	684949674	11377	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	684949674	10913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	684949674	11220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	684949674	11214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	684949674	11385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	684949674	11379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	684949674	11533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	684949674	11724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	684949674	11713	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	684949674	11379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	684949674	11050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	684949674	12063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	684949674	11916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	684949674	11352	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	684949674	11382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	684949674	12112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	684949674	11234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	684949674	11169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	684949674	11440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	684949674	11266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	684949674	11754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	684949674	11102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	684949674	11282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	684949674	10889	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	684949674	11899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	684949674	11367	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	684949674	11859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	684949674	11086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	684949674	11778	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	684949674	11136	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	684949674	11440	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	684949674	11101	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	684949674	11562	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	684949674	20988	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	684949674	11371	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	684949674	11309	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	684949674	11544	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	684949674	11292	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	684949674	12107	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	684949674	11172	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	684949674	11834	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	684949674	11498	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	662190782	2916	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	662190782	276685	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	662190782	328048057	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	662190782	334	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	662190782	900	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	662190782	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	662190782	482	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	661822219	231044858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	662190782	993	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	662190782	976	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	662190782	949	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	662190782	919	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	662190782	2004	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	662190782	185468	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	662190782	1897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	662190782	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662190782	1587	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	662190782	1317	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	661820635	661752236	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	662190782	662008565	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	662190782	991	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	662190782	189119	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	662190782	387582529	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	662190782	332	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	662190782	516	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	662190782	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	662190782	245	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	661822219	306092502	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	662190782	591	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	662190782	580	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	662190782	571	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	662190782	561	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	662190782	1064	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	662190782	125431	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	662190782	979	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	662190782	62	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662190782	1630	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	662190782	1360	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	661820635	661752236	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	662190782	662008565	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	662190782	6527	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	662190782	213561	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	662190782	369324794	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	662190782	239	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	662190782	518	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	662190782	22	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	662190782	220	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	661822219	265782666	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	662190782	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	662190782	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	662190782	565	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	662190782	557	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	662190782	1802	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	662190782	168042	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	662190782	1722	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	662190782	58	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662190782	1654	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	662190782	1384	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	661820635	661752236	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	662190782	662008565	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	662190782	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	662190782	3635	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	662190782	168316	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	662190782	380487679	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	662190782	288	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	662190782	457	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	662190782	33	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	662190782	198	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	661822219	289241853	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	662190782	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	662190782	537	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	662190782	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	662190782	518	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	662190782	1823	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	662190782	222416	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	662190782	1729	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	662190782	60	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	662190782	1625	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	662190782	1355	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	661820635	661752236	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	662190782	662008565	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	684949674	129319373	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	684949674	684308389	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	684949674	684308389	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	684949674	174449439	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	684949674	684308389	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	684949674	684308389	0	0
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tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	824	824	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	824	824	0	0

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