Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	175	1			T10	1		T22	1		T19	1
index[0x1]	153	1			T1	1		T3	1		T8	1
index[0x2]	181	1			T17	1		T25	1		T24	2
index[0x3]	161	1			T4	1		T17	1		T60	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	232	1			T1	1		T3	1		T17	3
lens_less_than_1000[1]	112	1			T17	4		T24	2		T18	1
lens_less_than_1000[2]	71	1			T60	1		T18	1		T73	1
lens_less_than_1000[3]	63	1			T22	1		T72	1		T43	1
lens_less_than_1000[4]	65	1			T4	1		T17	8		T80	1
lens_less_than_1000[5]	53	1			T17	1		T24	1		T18	1
lens_less_than_1000[6]	27	1			T8	1		T45	1		T50	1
lens_less_than_1000[7]	16	1			T73	1		T96	1		T98	1
lens_less_than_1000[8]	12	1			T258	1		T259	1		T260	1
lens_less_than_1000[9]	7	1			T19	1		T109	1		T53	1
len_2	12	1			T10	1		T261	1		T105	9

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	65	1			T18	1		T73	1		T42	3
index[0x0]	lens_less_than_1000[1]	23	1			T70	1		T109	1		T262	1
index[0x0]	lens_less_than_1000[2]	22	1			T18	1		T81	1		T223	1
index[0x0]	lens_less_than_1000[3]	14	1			T22	1		T65	1		T225	1
index[0x0]	lens_less_than_1000[4]	13	1			T111	1		T46	2		T87	1
index[0x0]	lens_less_than_1000[5]	20	1			T18	1		T70	1		T263	1
index[0x0]	lens_less_than_1000[6]	4	1			T264	1		T265	1		T190	1
index[0x0]	lens_less_than_1000[7]	1	1			T266	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	2	1			T258	1		T260	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T19	1		-	-		-	-
index[0x0]	len_2	10	1			T10	1		T105	9		-	-
index[0x1]	lens_less_than_1000[0]	57	1			T1	1		T3	1		T17	3
index[0x1]	lens_less_than_1000[1]	27	1			T17	3		T24	1		T18	1
index[0x1]	lens_less_than_1000[2]	15	1			T73	1		T70	1		T83	1
index[0x1]	lens_less_than_1000[3]	14	1			T98	1		T109	1		T267	1
index[0x1]	lens_less_than_1000[4]	17	1			T17	7		T53	1		T176	1
index[0x1]	lens_less_than_1000[5]	8	1			T17	1		T67	1		T223	1
index[0x1]	lens_less_than_1000[6]	7	1			T8	1		T21	1		T268	3
index[0x1]	lens_less_than_1000[7]	3	1			T73	1		T98	1		T269	1
index[0x1]	lens_less_than_1000[8]	3	1			T190	2		T270	1		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T248	1		T105	1		-	-
index[0x2]	lens_less_than_1000[0]	59	1			T25	1		T39	1		T42	2
index[0x2]	lens_less_than_1000[1]	22	1			T24	1		T92	2		T271	1
index[0x2]	lens_less_than_1000[2]	20	1			T109	2		T272	1		T48	1
index[0x2]	lens_less_than_1000[3]	22	1			T72	1		T43	1		T222	1
index[0x2]	lens_less_than_1000[4]	19	1			T17	1		T63	1		T66	1
index[0x2]	lens_less_than_1000[5]	17	1			T24	1		T273	2		T77	4
index[0x2]	lens_less_than_1000[6]	5	1			T274	1		T256	1		T240	1
index[0x2]	lens_less_than_1000[7]	10	1			T96	1		T99	2		T21	1
index[0x2]	lens_less_than_1000[8]	5	1			T259	1		T104	1		T190	2
index[0x2]	lens_less_than_1000[9]	1	1			T53	1		-	-		-	-
index[0x2]	len_2	1	1			T261	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	51	1			T20	2		T81	1		T42	1
index[0x3]	lens_less_than_1000[1]	40	1			T17	1		T275	1		T276	1
index[0x3]	lens_less_than_1000[2]	14	1			T60	1		T74	1		T48	1
index[0x3]	lens_less_than_1000[3]	13	1			T96	1		T49	1		T103	1
index[0x3]	lens_less_than_1000[4]	16	1			T4	1		T80	1		T70	3
index[0x3]	lens_less_than_1000[5]	8	1			T43	1		T95	1		T182	1
index[0x3]	lens_less_than_1000[6]	11	1			T45	1		T50	1		T277	1
index[0x3]	lens_less_than_1000[7]	2	1			T21	1		T278	1		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T190	1		T279	1		-	-
index[0x3]	lens_less_than_1000[9]	3	1			T109	1		T182	1		T241	1
index[0x3]	len_2	1	1			T280	1		-	-		-	-