Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T73	2		T70	1		T43	1
class_index[0x1]	62	1			T16	1		T18	1		T20	1
class_index[0x2]	58	1			T17	1		T18	2		T74	1
class_index[0x3]	61	1			T17	2		T18	1		T73	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	79	1			T18	1		T73	1		T74	1
intr_timeout_cnt[1]	49	1			T16	1		T17	2		T18	3
intr_timeout_cnt[2]	24	1			T17	1		T68	2		T111	1
intr_timeout_cnt[3]	22	1			T62	1		T79	1		T21	1
intr_timeout_cnt[4]	19	1			T73	1		T70	1		T44	1
intr_timeout_cnt[5]	15	1			T43	3		T75	1		T77	1
intr_timeout_cnt[6]	8	1			T62	1		T21	1		T191	2
intr_timeout_cnt[7]	7	1			T21	1		T176	2		T95	1
intr_timeout_cnt[8]	13	1			T42	1		T68	1		T56	1
intr_timeout_cnt[9]	6	1			T49	1		T238	1		T239	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T73	1		T34	1		T92	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T70	1		T64	1		T76	2
class_index[0x0]	intr_timeout_cnt[2]	2	1			T79	1		T49	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	2	1			T79	1		T240	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T73	1		T95	1		T241	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T43	1		T75	1		T191	2
class_index[0x0]	intr_timeout_cnt[6]	2	1			T21	1		T191	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T89	3		T242	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T106	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T42	1		T66	1		T78	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T16	1		T18	1		T20	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T243	1		T244	2		T89	2
class_index[0x1]	intr_timeout_cnt[3]	10	1			T62	1		T245	1		T191	1
class_index[0x1]	intr_timeout_cnt[4]	7	1			T49	1		T56	1		T246	2
class_index[0x1]	intr_timeout_cnt[5]	2	1			T78	1		T49	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T247	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T176	1		T95	1		T185	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T42	1		T68	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T239	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T18	1		T74	1		T70	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T18	1		T248	1		T100	1
class_index[0x2]	intr_timeout_cnt[2]	11	1			T17	1		T68	2		T111	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T21	1		T176	1		T95	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T70	1		T44	1		T95	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T249	1		T190	1		T191	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T21	1		T176	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T250	1		T89	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T49	1		T238	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	14	1			T45	1		T46	1		T251	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T17	2		T18	1		T73	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T79	1		T21	1		T238	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T54	1		T103	1		T245	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T49	1		T252	1		T253	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T43	2		T77	1		T254	2
class_index[0x3]	intr_timeout_cnt[6]	5	1			T62	1		T191	1		T255	2
class_index[0x3]	intr_timeout_cnt[7]	2	1			T191	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	5	1			T56	1		T190	2		T257	1
class_index[0x3]	intr_timeout_cnt[9]	2	1			T242	2		-	-		-	-