Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354888	1			T1	1985		T2	13		T3	1761
all_values[1]	354888	1			T1	1985		T2	13		T3	1761
all_values[2]	354888	1			T1	1985		T2	13		T3	1761
all_values[3]	354888	1			T1	1985		T2	13		T3	1761

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

706503

1

T1

3921

T2

25

T3

3603

auto[1]

713049

1

T1

4019

T2

27

T3

3441

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839175

1

T1

4022

T2

51

T3

5276

auto[1]

580377

1

T1

3918

T2

1

T3

1768

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102593	1			T1	488		T2	8		T3	916
all_values[0]	auto[0]	auto[1]	74143	1			T1	484		T3	1		T4	8
all_values[0]	auto[1]	auto[0]	103518	1			T1	509		T2	4		T3	843
all_values[0]	auto[1]	auto[1]	74634	1			T1	504		T2	1		T3	1
all_values[1]	auto[0]	auto[0]	105903	1			T1	479		T2	9		T3	714
all_values[1]	auto[0]	auto[1]	70733	1			T1	474		T3	205		T4	7
all_values[1]	auto[1]	auto[0]	107045	1			T1	517		T2	4		T3	619
all_values[1]	auto[1]	auto[1]	71207	1			T1	515		T3	223		T4	11
all_values[2]	auto[0]	auto[0]	104631	1			T1	512		T2	4		T3	543
all_values[2]	auto[0]	auto[1]	72439	1			T1	462		T3	333		T4	9
all_values[2]	auto[1]	auto[0]	105617	1			T1	522		T2	9		T3	561
all_values[2]	auto[1]	auto[1]	72201	1			T1	489		T3	324		T4	9
all_values[3]	auto[0]	auto[0]	103869	1			T1	512		T2	4		T3	544
all_values[3]	auto[0]	auto[1]	72192	1			T1	510		T3	347		T4	6
all_values[3]	auto[1]	auto[0]	105999	1			T1	483		T2	9		T3	536
all_values[3]	auto[1]	auto[1]	72828	1			T1	480		T3	334		T4	10