Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	354888	1			T1	1985		T2	13		T3	1761
all_pins[1]	354888	1			T1	1985		T2	13		T3	1761
all_pins[2]	354888	1			T1	1985		T2	13		T3	1761
all_pins[3]	354888	1			T1	1985		T2	13		T3	1761

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1128682	1			T1	5952		T2	51		T3	6162
values[0x1]	290870	1			T1	1988		T2	1		T3	882
transitions[0x0=>0x1]	192850	1			T1	1243		T2	1		T3	674
transitions[0x1=>0x0]	193124	1			T1	1244		T2	1		T3	674

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280254	1			T1	1481		T2	12		T3	1760
all_pins[0]	values[0x1]	74634	1			T1	504		T2	1		T3	1
all_pins[0]	transitions[0x0=>0x1]	73903	1			T1	503		T2	1		T3	1
all_pins[0]	transitions[0x1=>0x0]	72371	1			T1	480		T3	334		T4	10
all_pins[1]	values[0x0]	283681	1			T1	1470		T2	13		T3	1538
all_pins[1]	values[0x1]	71207	1			T1	515		T3	223		T4	11
all_pins[1]	transitions[0x0=>0x1]	38674	1			T1	264		T3	223		T4	4
all_pins[1]	transitions[0x1=>0x0]	42101	1			T1	253		T2	1		T3	1
all_pins[2]	values[0x0]	282687	1			T1	1496		T2	13		T3	1437
all_pins[2]	values[0x1]	72201	1			T1	489		T3	324		T4	9
all_pins[2]	transitions[0x0=>0x1]	40072	1			T1	231		T3	241		T4	4
all_pins[2]	transitions[0x1=>0x0]	39078	1			T1	257		T3	140		T4	6
all_pins[3]	values[0x0]	282060	1			T1	1505		T2	13		T3	1427
all_pins[3]	values[0x1]	72828	1			T1	480		T3	334		T4	10
all_pins[3]	transitions[0x0=>0x1]	40201	1			T1	245		T3	209		T4	6
all_pins[3]	transitions[0x1=>0x0]	39574	1			T1	254		T3	199		T4	5