Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91657	1			T1	1127		T6	919		T17	799
accum_cnt_1000	220190	1			T1	1031		T3	2088		T6	970
accum_cnt_100	27451	1			T1	54		T3	252		T6	50
accum_cnt_50	77631	1			T1	1513		T3	188		T4	41
accum_cnt_10	174123	1			T1	25		T2	9		T3	59
accum_cnt_0	408756	1			T1	1483		T2	35		T3	2613

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263045	1			T1	1475		T2	11		T3	1300
class_index[0x1]	263045	1			T1	1475		T2	11		T3	1300
class_index[0x2]	263045	1			T1	1475		T2	11		T3	1300
class_index[0x3]	263045	1			T1	1475		T2	11		T3	1300

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28182	1			T1	503		T6	468		T17	274
class_index[0x0]	accum_cnt_1000	56598	1			T1	464		T6	431		T17	1629
class_index[0x0]	accum_cnt_100	7355	1			T1	24		T6	20		T17	161
class_index[0x0]	accum_cnt_50	15080	1			T1	22		T4	20		T5	10
class_index[0x0]	accum_cnt_10	47121	1			T1	20		T2	9		T3	2
class_index[0x0]	accum_cnt_0	90435	1			T1	5		T2	2		T3	1298
class_index[0x1]	accum_cnt_2000	23666	1			T60	65		T72	74		T42	337
class_index[0x1]	accum_cnt_1000	52419	1			T3	976		T8	14		T17	497
class_index[0x1]	accum_cnt_100	6428	1			T3	162		T22	7		T17	35
class_index[0x1]	accum_cnt_50	21024	1			T1	1473		T3	123		T4	21
class_index[0x1]	accum_cnt_10	35149	1			T1	2		T3	33		T4	4
class_index[0x1]	accum_cnt_0	114051	1			T2	11		T3	6		T4	3
class_index[0x2]	accum_cnt_2000	20247	1			T6	451		T70	24		T72	376
class_index[0x2]	accum_cnt_1000	57581	1			T3	1112		T6	539		T17	16
class_index[0x2]	accum_cnt_100	7816	1			T3	90		T6	30		T17	45
class_index[0x2]	accum_cnt_50	18327	1			T3	65		T6	22		T8	12
class_index[0x2]	accum_cnt_10	52327	1			T3	24		T4	1		T6	6
class_index[0x2]	accum_cnt_0	92931	1			T1	1475		T2	11		T3	9
class_index[0x3]	accum_cnt_2000	19562	1			T1	624		T17	525		T71	293
class_index[0x3]	accum_cnt_1000	53592	1			T1	567		T17	1358		T73	15
class_index[0x3]	accum_cnt_100	5852	1			T1	30		T16	4		T17	101
class_index[0x3]	accum_cnt_50	23200	1			T1	18		T16	24		T17	152
class_index[0x3]	accum_cnt_10	39526	1			T1	3		T4	2		T8	16
class_index[0x3]	accum_cnt_0	111339	1			T1	3		T2	11		T3	1300