Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	10563	1			T1	271		T9	1		T42	6247
alert[0x1]	4010	1			T17	42		T61	1		T43	108
alert[0x2]	10489	1			T17	26		T42	346		T43	8
alert[0x3]	4714	1			T1	2		T5	7		T17	17
alert[0x4]	3940	1			T1	62		T17	14		T63	327
alert[0x5]	1722	1			T1	32		T17	13		T61	1
alert[0x6]	7561	1			T1	26		T17	129		T61	1
alert[0x7]	8747	1			T17	176		T43	38		T98	184
alert[0x8]	4407	1			T61	1		T42	20		T221	71
alert[0x9]	13854	1			T5	2		T43	60		T66	7
alert[0xa]	6548	1			T1	20		T17	345		T18	1
alert[0xb]	6523	1			T1	510		T61	1		T42	53
alert[0xc]	7517	1			T63	13		T43	388		T98	94
alert[0xd]	8408	1			T1	110		T41	1		T286	1
alert[0xe]	11535	1			T17	278		T41	1		T42	372
alert[0xf]	6384	1			T1	139		T17	33		T42	51
alert[0x10]	11773	1			T1	18		T40	1		T61	2
alert[0x11]	8458	1			T1	21		T17	23		T41	1
alert[0x12]	11122	1			T1	68		T17	204		T20	3
alert[0x13]	5885	1			T1	508		T40	1		T110	139
alert[0x14]	17430	1			T1	1373		T18	161		T63	49
alert[0x15]	3109	1			T8	3		T17	24		T42	17
alert[0x16]	10204	1			T1	59		T3	1		T17	685
alert[0x17]	6898	1			T17	292		T41	1		T70	2
alert[0x18]	3232	1			T40	1		T42	38		T43	1001
alert[0x19]	5900	1			T8	3		T9	1		T22	7
alert[0x1a]	12437	1			T1	62		T17	10		T41	1
alert[0x1b]	5958	1			T17	19		T66	1		T110	38
alert[0x1c]	5990	1			T42	582		T63	82		T43	11
alert[0x1d]	6793	1			T1	6		T17	41		T41	1
alert[0x1e]	3070	1			T8	1		T41	1		T42	202
alert[0x1f]	4349	1			T5	12		T20	1		T41	1
alert[0x20]	7825	1			T1	92		T17	28		T40	2
alert[0x21]	3115	1			T17	370		T42	354		T43	7
alert[0x22]	6902	1			T1	24		T17	115		T61	2
alert[0x23]	6539	1			T42	57		T63	6		T43	1017
alert[0x24]	4373	1			T8	3		T17	71		T98	145
alert[0x25]	4368	1			T1	228		T17	39		T40	1
alert[0x26]	5593	1			T1	111		T42	32		T63	55
alert[0x27]	20665	1			T1	57		T70	2		T42	30
alert[0x28]	9648	1			T17	55		T20	6		T63	31
alert[0x29]	6263	1			T1	88		T17	3		T61	1
alert[0x2a]	9390	1			T110	24		T75	2		T46	46
alert[0x2b]	4116	1			T1	20		T9	1		T18	4
alert[0x2c]	14790	1			T1	72		T18	10		T42	20
alert[0x2d]	5414	1			T42	155		T62	2		T63	422
alert[0x2e]	14597	1			T1	222		T42	12		T63	989
alert[0x2f]	6506	1			T5	1		T17	23		T40	1
alert[0x30]	8705	1			T1	225		T17	91		T63	1368
alert[0x31]	7004	1			T1	7		T5	2		T17	461
alert[0x32]	11613	1			T17	444		T110	72		T221	2061
alert[0x33]	7681	1			T9	1		T22	34		T42	17
alert[0x34]	7176	1			T17	7		T41	1		T42	7
alert[0x35]	7693	1			T9	2		T42	123		T63	158
alert[0x36]	11688	1			T9	1		T41	2		T110	11
alert[0x37]	9052	1			T9	1		T42	31		T63	112
alert[0x38]	16304	1			T42	16		T63	1		T221	288
alert[0x39]	9833	1			T22	3		T17	10		T42	23
alert[0x3a]	6512	1			T1	21		T41	1		T42	44
alert[0x3b]	6672	1			T5	2		T17	577		T44	1
alert[0x3c]	10575	1			T17	208		T41	1		T42	27
alert[0x3d]	12507	1			T1	23		T42	19		T43	5
alert[0x3e]	4915	1			T1	32		T221	153		T98	84
alert[0x3f]	7235	1			T1	1153		T17	27		T42	59
alert[0x40]	21124	1			T1	9		T9	1		T17	22

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	136777	1			T5	12		T17	823		T18	287
class_i[0x1]	155182	1			T1	5671		T5	9		T22	34
class_i[0x2]	162583	1			T5	5		T22	3		T17	4053
class_i[0x3]	81381	1			T3	1		T8	10		T9	9

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

535211

1

T1

5671

T5

26

T8

10

alert_ping_fail

712

1

T3

1

T9

9

T40

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	10548	1			T1	271		T42	6247		T63	3
alert_integrity_fail	alert[0x1]	3997	1			T17	42		T43	108		T110	47
alert_integrity_fail	alert[0x2]	10476	1			T17	26		T42	346		T43	8
alert_integrity_fail	alert[0x3]	4703	1			T1	2		T5	7		T17	17
alert_integrity_fail	alert[0x4]	3929	1			T1	62		T17	14		T63	327
alert_integrity_fail	alert[0x5]	1701	1			T1	32		T17	13		T20	1
alert_integrity_fail	alert[0x6]	7554	1			T1	26		T17	129		T43	118
alert_integrity_fail	alert[0x7]	8731	1			T17	176		T43	38		T98	184
alert_integrity_fail	alert[0x8]	4396	1			T42	20		T221	71		T46	8
alert_integrity_fail	alert[0x9]	13840	1			T5	2		T43	60		T66	7
alert_integrity_fail	alert[0xa]	6543	1			T1	20		T17	345		T18	1
alert_integrity_fail	alert[0xb]	6510	1			T1	510		T42	53		T43	343
alert_integrity_fail	alert[0xc]	7506	1			T63	13		T43	388		T98	94
alert_integrity_fail	alert[0xd]	8395	1			T1	110		T108	27		T77	524
alert_integrity_fail	alert[0xe]	11530	1			T17	278		T42	372		T98	56
alert_integrity_fail	alert[0xf]	6380	1			T1	139		T17	33		T42	51
alert_integrity_fail	alert[0x10]	11765	1			T1	18		T42	177		T63	17
alert_integrity_fail	alert[0x11]	8445	1			T1	21		T17	23		T110	806
alert_integrity_fail	alert[0x12]	11117	1			T1	68		T17	204		T20	3
alert_integrity_fail	alert[0x13]	5873	1			T1	508		T110	139		T221	43
alert_integrity_fail	alert[0x14]	17422	1			T1	1373		T18	161		T63	49
alert_integrity_fail	alert[0x15]	3101	1			T8	3		T17	24		T42	17
alert_integrity_fail	alert[0x16]	10184	1			T1	59		T17	685		T18	8
alert_integrity_fail	alert[0x17]	6890	1			T17	292		T70	2		T42	600
alert_integrity_fail	alert[0x18]	3218	1			T42	38		T43	1001		T221	146
alert_integrity_fail	alert[0x19]	5888	1			T8	3		T22	7		T221	23
alert_integrity_fail	alert[0x1a]	12427	1			T1	62		T17	10		T73	2
alert_integrity_fail	alert[0x1b]	5946	1			T17	19		T66	1		T110	38
alert_integrity_fail	alert[0x1c]	5982	1			T42	582		T63	82		T43	11
alert_integrity_fail	alert[0x1d]	6787	1			T1	6		T17	41		T43	11
alert_integrity_fail	alert[0x1e]	3058	1			T8	1		T42	202		T110	130
alert_integrity_fail	alert[0x1f]	4331	1			T5	12		T20	1		T42	382
alert_integrity_fail	alert[0x20]	7811	1			T1	92		T17	28		T63	32
alert_integrity_fail	alert[0x21]	3104	1			T17	370		T42	354		T43	7
alert_integrity_fail	alert[0x22]	6884	1			T1	24		T17	115		T63	2
alert_integrity_fail	alert[0x23]	6528	1			T42	57		T63	6		T43	1017
alert_integrity_fail	alert[0x24]	4367	1			T8	3		T17	71		T98	145
alert_integrity_fail	alert[0x25]	4358	1			T1	228		T17	39		T20	2
alert_integrity_fail	alert[0x26]	5583	1			T1	111		T42	32		T63	55
alert_integrity_fail	alert[0x27]	20659	1			T1	57		T70	2		T42	30
alert_integrity_fail	alert[0x28]	9631	1			T17	55		T20	6		T63	31
alert_integrity_fail	alert[0x29]	6251	1			T1	88		T17	3		T43	274
alert_integrity_fail	alert[0x2a]	9382	1			T110	24		T75	2		T46	46
alert_integrity_fail	alert[0x2b]	4107	1			T1	20		T18	4		T42	18
alert_integrity_fail	alert[0x2c]	14778	1			T1	72		T18	10		T42	20
alert_integrity_fail	alert[0x2d]	5401	1			T42	155		T62	2		T63	422
alert_integrity_fail	alert[0x2e]	14585	1			T1	222		T42	12		T63	989
alert_integrity_fail	alert[0x2f]	6488	1			T5	1		T17	23		T42	37
alert_integrity_fail	alert[0x30]	8692	1			T1	225		T17	91		T63	1368
alert_integrity_fail	alert[0x31]	6995	1			T1	7		T5	2		T17	461
alert_integrity_fail	alert[0x32]	11606	1			T17	444		T110	72		T221	2061
alert_integrity_fail	alert[0x33]	7669	1			T22	34		T42	17		T63	22
alert_integrity_fail	alert[0x34]	7166	1			T17	7		T42	7		T110	50
alert_integrity_fail	alert[0x35]	7685	1			T42	123		T63	158		T110	29
alert_integrity_fail	alert[0x36]	11679	1			T110	11		T111	8		T46	178
alert_integrity_fail	alert[0x37]	9043	1			T42	31		T63	112		T43	1437
alert_integrity_fail	alert[0x38]	16296	1			T42	16		T63	1		T221	288
alert_integrity_fail	alert[0x39]	9818	1			T22	3		T17	10		T42	23
alert_integrity_fail	alert[0x3a]	6497	1			T1	21		T42	44		T63	275
alert_integrity_fail	alert[0x3b]	6660	1			T5	2		T17	577		T44	1
alert_integrity_fail	alert[0x3c]	10569	1			T17	208		T42	27		T43	13
alert_integrity_fail	alert[0x3d]	12502	1			T1	23		T42	19		T43	5
alert_integrity_fail	alert[0x3e]	4907	1			T1	32		T221	153		T98	84
alert_integrity_fail	alert[0x3f]	7226	1			T1	1153		T17	27		T42	59
alert_integrity_fail	alert[0x40]	21111	1			T1	9		T17	22		T63	116
alert_ping_fail	alert[0x0]	15	1			T9	1		T287	1		T288	2
alert_ping_fail	alert[0x1]	13	1			T61	1		T233	1		T287	1
alert_ping_fail	alert[0x2]	13	1			T286	1		T289	1		T233	1
alert_ping_fail	alert[0x3]	11	1			T233	1		T290	1		T291	1
alert_ping_fail	alert[0x4]	11	1			T286	1		T233	1		T292	1
alert_ping_fail	alert[0x5]	21	1			T61	1		T41	1		T81	2
alert_ping_fail	alert[0x6]	7	1			T61	1		T288	1		T293	1
alert_ping_fail	alert[0x7]	16	1			T287	1		T294	1		T295	1
alert_ping_fail	alert[0x8]	11	1			T61	1		T286	1		T287	1
alert_ping_fail	alert[0x9]	14	1			T286	1		T233	1		T296	1
alert_ping_fail	alert[0xa]	5	1			T264	1		T297	1		T291	1
alert_ping_fail	alert[0xb]	13	1			T61	1		T233	3		T287	1
alert_ping_fail	alert[0xc]	11	1			T233	1		T298	1		T299	1
alert_ping_fail	alert[0xd]	13	1			T41	1		T286	1		T287	1
alert_ping_fail	alert[0xe]	5	1			T41	1		T273	1		T299	2
alert_ping_fail	alert[0xf]	4	1			T298	1		T300	1		T301	1
alert_ping_fail	alert[0x10]	8	1			T40	1		T61	2		T296	2
alert_ping_fail	alert[0x11]	13	1			T41	1		T286	2		T298	1
alert_ping_fail	alert[0x12]	5	1			T302	1		T290	1		T303	1
alert_ping_fail	alert[0x13]	12	1			T40	1		T304	1		T298	1
alert_ping_fail	alert[0x14]	8	1			T298	1		T305	1		T306	1
alert_ping_fail	alert[0x15]	8	1			T307	1		T294	1		T296	1
alert_ping_fail	alert[0x16]	20	1			T3	1		T285	1		T308	2
alert_ping_fail	alert[0x17]	8	1			T41	1		T273	1		T296	1
alert_ping_fail	alert[0x18]	14	1			T40	1		T233	1		T302	1
alert_ping_fail	alert[0x19]	12	1			T9	1		T273	1		T309	1
alert_ping_fail	alert[0x1a]	10	1			T41	1		T302	1		T264	1
alert_ping_fail	alert[0x1b]	12	1			T273	1		T298	1		T288	1
alert_ping_fail	alert[0x1c]	8	1			T287	1		T296	1		T310	1
alert_ping_fail	alert[0x1d]	6	1			T41	1		T286	1		T289	1
alert_ping_fail	alert[0x1e]	12	1			T41	1		T287	1		T298	1
alert_ping_fail	alert[0x1f]	18	1			T41	1		T231	1		T287	1
alert_ping_fail	alert[0x20]	14	1			T40	2		T311	1		T309	2
alert_ping_fail	alert[0x21]	11	1			T286	1		T292	2		T294	1
alert_ping_fail	alert[0x22]	18	1			T61	2		T281	1		T312	1
alert_ping_fail	alert[0x23]	11	1			T287	1		T288	1		T311	1
alert_ping_fail	alert[0x24]	6	1			T233	1		T313	1		T314	1
alert_ping_fail	alert[0x25]	10	1			T40	1		T273	1		T298	1
alert_ping_fail	alert[0x26]	10	1			T298	1		T313	1		T315	2
alert_ping_fail	alert[0x27]	6	1			T316	1		T317	1		T318	1
alert_ping_fail	alert[0x28]	17	1			T298	2		T292	1		T310	1
alert_ping_fail	alert[0x29]	12	1			T61	1		T296	1		T313	2
alert_ping_fail	alert[0x2a]	8	1			T298	1		T319	1		T303	1
alert_ping_fail	alert[0x2b]	9	1			T9	1		T61	1		T233	1
alert_ping_fail	alert[0x2c]	12	1			T286	1		T289	1		T307	1
alert_ping_fail	alert[0x2d]	13	1			T284	1		T299	1		T295	1
alert_ping_fail	alert[0x2e]	12	1			T319	1		T296	1		T316	3
alert_ping_fail	alert[0x2f]	18	1			T40	1		T320	1		T233	1
alert_ping_fail	alert[0x30]	13	1			T294	2		T299	1		T264	2
alert_ping_fail	alert[0x31]	9	1			T298	1		T264	1		T310	1
alert_ping_fail	alert[0x32]	7	1			T289	1		T298	1		T294	1
alert_ping_fail	alert[0x33]	12	1			T9	1		T292	1		T299	1
alert_ping_fail	alert[0x34]	10	1			T41	1		T288	1		T294	1
alert_ping_fail	alert[0x35]	8	1			T9	2		T273	1		T294	1
alert_ping_fail	alert[0x36]	9	1			T9	1		T41	2		T287	1
alert_ping_fail	alert[0x37]	9	1			T9	1		T233	1		T299	1
alert_ping_fail	alert[0x38]	8	1			T233	1		T292	1		T291	1
alert_ping_fail	alert[0x39]	15	1			T286	1		T298	1		T288	1
alert_ping_fail	alert[0x3a]	15	1			T41	1		T233	1		T287	2
alert_ping_fail	alert[0x3b]	12	1			T233	3		T311	1		T297	1
alert_ping_fail	alert[0x3c]	6	1			T41	1		T287	1		T264	1
alert_ping_fail	alert[0x3d]	5	1			T286	1		T298	1		T321	2
alert_ping_fail	alert[0x3e]	8	1			T288	1		T292	1		T264	1
alert_ping_fail	alert[0x3f]	9	1			T233	1		T294	1		T296	1
alert_ping_fail	alert[0x40]	13	1			T9	1		T286	1		T287	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	136565	1			T5	12		T17	823		T18	287
alert_integrity_fail	class_i[0x1]	155012	1			T1	5671		T5	9		T22	34
alert_integrity_fail	class_i[0x2]	162404	1			T5	5		T22	3		T17	4053
alert_integrity_fail	class_i[0x3]	81230	1			T8	10		T22	7		T17	25
alert_ping_fail	class_i[0x0]	212	1			T40	1		T61	2		T41	8
alert_ping_fail	class_i[0x1]	170	1			T40	2		T61	1		T41	3
alert_ping_fail	class_i[0x2]	179	1			T40	1		T61	7		T41	2
alert_ping_fail	class_i[0x3]	151	1			T3	1		T9	9		T40	3