Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.72 100.00 100.00 100.00 99.38 99.68


Total test records in report: 824
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T133 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3810435775 Jun 26 07:05:42 PM PDT 24 Jun 26 07:07:50 PM PDT 24 6880168082 ps
T774 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2747765433 Jun 26 07:05:44 PM PDT 24 Jun 26 07:05:56 PM PDT 24 1064401570 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1799743625 Jun 26 07:05:07 PM PDT 24 Jun 26 07:05:15 PM PDT 24 916153143 ps
T137 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3783998163 Jun 26 07:06:46 PM PDT 24 Jun 26 07:11:18 PM PDT 24 9584802352 ps
T138 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.538004832 Jun 26 07:05:44 PM PDT 24 Jun 26 07:24:42 PM PDT 24 60835064033 ps
T147 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2581477811 Jun 26 07:05:42 PM PDT 24 Jun 26 07:08:42 PM PDT 24 4207228752 ps
T125 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.304065324 Jun 26 07:05:46 PM PDT 24 Jun 26 07:12:53 PM PDT 24 20570975434 ps
T167 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2344100304 Jun 26 07:05:20 PM PDT 24 Jun 26 07:06:00 PM PDT 24 605451252 ps
T161 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1167492422 Jun 26 07:05:50 PM PDT 24 Jun 26 07:07:02 PM PDT 24 4381024538 ps
T776 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1425241099 Jun 26 07:05:59 PM PDT 24 Jun 26 07:06:05 PM PDT 24 8054476 ps
T777 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.800796440 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:07 PM PDT 24 36401403 ps
T778 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.720716374 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:04 PM PDT 24 6370427 ps
T131 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4097236299 Jun 26 07:05:46 PM PDT 24 Jun 26 07:11:32 PM PDT 24 6085624940 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2080635673 Jun 26 07:05:46 PM PDT 24 Jun 26 07:06:18 PM PDT 24 687115739 ps
T140 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2145932582 Jun 26 07:05:46 PM PDT 24 Jun 26 07:29:08 PM PDT 24 310803720061 ps
T780 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3779376557 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:08 PM PDT 24 102274502 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1885197539 Jun 26 07:05:45 PM PDT 24 Jun 26 07:05:59 PM PDT 24 207276944 ps
T164 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.378780609 Jun 26 07:05:54 PM PDT 24 Jun 26 07:05:59 PM PDT 24 63308660 ps
T782 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2307100479 Jun 26 07:05:46 PM PDT 24 Jun 26 07:05:52 PM PDT 24 8564528 ps
T151 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3460067673 Jun 26 07:05:56 PM PDT 24 Jun 26 07:08:47 PM PDT 24 8653533205 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2480737797 Jun 26 07:05:30 PM PDT 24 Jun 26 07:06:12 PM PDT 24 617614481 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3227384342 Jun 26 07:05:45 PM PDT 24 Jun 26 07:06:11 PM PDT 24 4088768775 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4171947199 Jun 26 07:05:10 PM PDT 24 Jun 26 07:11:28 PM PDT 24 5959067345 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1671994125 Jun 26 07:05:44 PM PDT 24 Jun 26 07:07:10 PM PDT 24 1246856764 ps
T786 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3535077740 Jun 26 07:05:31 PM PDT 24 Jun 26 07:05:35 PM PDT 24 24089690 ps
T787 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2290866929 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:02 PM PDT 24 14047181 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3899033223 Jun 26 07:05:08 PM PDT 24 Jun 26 07:05:15 PM PDT 24 120501225 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.232110867 Jun 26 07:05:09 PM PDT 24 Jun 26 07:05:40 PM PDT 24 1699216395 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.942984171 Jun 26 07:05:20 PM PDT 24 Jun 26 07:06:14 PM PDT 24 1498486082 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.419836961 Jun 26 07:05:23 PM PDT 24 Jun 26 07:05:27 PM PDT 24 20567272 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.555260928 Jun 26 07:05:07 PM PDT 24 Jun 26 07:07:36 PM PDT 24 1172077929 ps
T793 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2417014394 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:09 PM PDT 24 157151652 ps
T794 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3830809624 Jun 26 07:05:20 PM PDT 24 Jun 26 07:05:23 PM PDT 24 7931671 ps
T795 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4024939301 Jun 26 07:05:45 PM PDT 24 Jun 26 07:06:07 PM PDT 24 239608652 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.523810765 Jun 26 07:05:46 PM PDT 24 Jun 26 07:06:04 PM PDT 24 202882708 ps
T146 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2097935754 Jun 26 07:06:46 PM PDT 24 Jun 26 07:11:49 PM PDT 24 2638453187 ps
T797 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.496195835 Jun 26 07:05:18 PM PDT 24 Jun 26 07:09:04 PM PDT 24 3865815346 ps
T149 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.722976583 Jun 26 07:05:10 PM PDT 24 Jun 26 07:07:44 PM PDT 24 8106715854 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2814803141 Jun 26 07:05:34 PM PDT 24 Jun 26 07:05:39 PM PDT 24 22903149 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3278908555 Jun 26 07:05:50 PM PDT 24 Jun 26 07:06:16 PM PDT 24 648793160 ps
T800 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.870658544 Jun 26 07:05:56 PM PDT 24 Jun 26 07:06:00 PM PDT 24 20217041 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3049946791 Jun 26 07:05:42 PM PDT 24 Jun 26 07:05:45 PM PDT 24 20542102 ps
T802 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4198664231 Jun 26 07:05:33 PM PDT 24 Jun 26 07:05:40 PM PDT 24 52764434 ps
T803 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3082349095 Jun 26 07:05:31 PM PDT 24 Jun 26 07:05:58 PM PDT 24 453984950 ps
T804 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1484467530 Jun 26 07:06:00 PM PDT 24 Jun 26 07:06:05 PM PDT 24 8512907 ps
T805 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3321540731 Jun 26 07:05:58 PM PDT 24 Jun 26 07:06:10 PM PDT 24 126844796 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2653717980 Jun 26 07:05:29 PM PDT 24 Jun 26 07:08:57 PM PDT 24 2765820575 ps
T144 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1309843505 Jun 26 07:05:46 PM PDT 24 Jun 26 07:16:17 PM PDT 24 8534902230 ps
T806 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3014285129 Jun 26 07:05:46 PM PDT 24 Jun 26 07:05:55 PM PDT 24 53086863 ps
T807 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2239005177 Jun 26 07:05:45 PM PDT 24 Jun 26 07:06:02 PM PDT 24 175620597 ps
T808 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3824125376 Jun 26 07:05:44 PM PDT 24 Jun 26 07:06:03 PM PDT 24 263403638 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1361365438 Jun 26 07:05:21 PM PDT 24 Jun 26 07:07:20 PM PDT 24 1638142421 ps
T810 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2814281061 Jun 26 07:05:50 PM PDT 24 Jun 26 07:05:58 PM PDT 24 68604534 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.618153721 Jun 26 07:05:19 PM PDT 24 Jun 26 07:05:31 PM PDT 24 521540650 ps
T148 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4092000190 Jun 26 07:05:32 PM PDT 24 Jun 26 07:14:14 PM PDT 24 11971289343 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2216600809 Jun 26 07:05:57 PM PDT 24 Jun 26 07:06:04 PM PDT 24 59380818 ps
T813 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1674663091 Jun 26 07:05:57 PM PDT 24 Jun 26 07:06:02 PM PDT 24 22948599 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2006416692 Jun 26 07:05:33 PM PDT 24 Jun 26 07:05:41 PM PDT 24 144745231 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2651490387 Jun 26 07:05:20 PM PDT 24 Jun 26 07:05:23 PM PDT 24 15789176 ps
T142 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3942714601 Jun 26 07:05:34 PM PDT 24 Jun 26 07:08:52 PM PDT 24 1891337774 ps
T816 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.406483051 Jun 26 07:05:32 PM PDT 24 Jun 26 07:05:47 PM PDT 24 152316216 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.719535589 Jun 26 07:05:22 PM PDT 24 Jun 26 07:05:25 PM PDT 24 13997163 ps
T135 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.716232173 Jun 26 07:05:43 PM PDT 24 Jun 26 07:08:06 PM PDT 24 1925764885 ps
T818 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1379158904 Jun 26 07:05:44 PM PDT 24 Jun 26 07:05:53 PM PDT 24 112386156 ps
T819 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2156659317 Jun 26 07:05:20 PM PDT 24 Jun 26 07:05:34 PM PDT 24 929605987 ps
T152 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2026470699 Jun 26 07:06:00 PM PDT 24 Jun 26 07:29:31 PM PDT 24 17332306129 ps
T820 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1768109267 Jun 26 07:05:44 PM PDT 24 Jun 26 07:05:49 PM PDT 24 7733921 ps
T166 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3479164354 Jun 26 07:05:43 PM PDT 24 Jun 26 07:05:48 PM PDT 24 30974980 ps
T168 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1315967298 Jun 26 07:06:46 PM PDT 24 Jun 26 07:07:16 PM PDT 24 2769851127 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1579349652 Jun 26 07:06:46 PM PDT 24 Jun 26 07:06:56 PM PDT 24 63362125 ps
T822 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.339913726 Jun 26 07:05:49 PM PDT 24 Jun 26 07:06:20 PM PDT 24 344042197 ps
T823 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2768176589 Jun 26 07:06:00 PM PDT 24 Jun 26 07:06:05 PM PDT 24 6259463 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.465435215 Jun 26 07:05:30 PM PDT 24 Jun 26 07:05:41 PM PDT 24 134613217 ps
T143 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1921292398 Jun 26 07:05:46 PM PDT 24 Jun 26 07:11:47 PM PDT 24 7882798630 ps

Test location /workspace/coverage/default/45.alert_handler_entropy.1619775715
Short name T1
Test name
Test status
Simulation time 14213967545 ps
CPU time 1476.89 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:35:23 PM PDT 24
Peak memory 290208 kb
Host smart-e92a9816-caaa-4710-bef4-8aec094f0a8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619775715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1619775715
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1444313113
Short name T17
Test name
Test status
Simulation time 35751588750 ps
CPU time 3930.84 seconds
Started Jun 26 07:06:42 PM PDT 24
Finished Jun 26 08:12:15 PM PDT 24
Peak memory 330832 kb
Host smart-0cf03708-13b0-4cc2-aae0-ebf07f43228b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444313113 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1444313113
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3986913583
Short name T12
Test name
Test status
Simulation time 468158243 ps
CPU time 26.76 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:06:44 PM PDT 24
Peak memory 273564 kb
Host smart-f06ba6a3-e420-452f-8b5f-a40339eb1a50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3986913583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3986913583
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1062925621
Short name T153
Test name
Test status
Simulation time 2174667740 ps
CPU time 90.62 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:07:21 PM PDT 24
Peak memory 240632 kb
Host smart-9b945978-a75e-471c-8296-8d287e367820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1062925621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1062925621
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.798538723
Short name T42
Test name
Test status
Simulation time 128199227918 ps
CPU time 2241.57 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:43:41 PM PDT 24
Peak memory 289768 kb
Host smart-2564d91e-55db-424e-9f15-23c89e417fd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798538723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.798538723
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2733135815
Short name T70
Test name
Test status
Simulation time 12403227002 ps
CPU time 1176.02 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:27:47 PM PDT 24
Peak memory 284280 kb
Host smart-d53108d3-8b50-4ca7-a882-04a827d40824
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733135815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2733135815
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3779889799
Short name T39
Test name
Test status
Simulation time 45994989610 ps
CPU time 955.67 seconds
Started Jun 26 07:06:35 PM PDT 24
Finished Jun 26 07:22:32 PM PDT 24
Peak memory 290076 kb
Host smart-2b5a3b6a-cce5-4269-b8cb-1296e610512c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779889799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3779889799
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3816440050
Short name T122
Test name
Test status
Simulation time 1716814188 ps
CPU time 221.32 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:09:01 PM PDT 24
Peak memory 265484 kb
Host smart-1decc716-4901-45f4-b094-5ff4ca8d062e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3816440050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3816440050
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2722633960
Short name T49
Test name
Test status
Simulation time 444245993853 ps
CPU time 4113.57 seconds
Started Jun 26 07:07:09 PM PDT 24
Finished Jun 26 08:15:44 PM PDT 24
Peak memory 298440 kb
Host smart-a8f9ac0c-80a9-4203-9d8a-cb310845d9ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722633960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2722633960
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1430202629
Short name T96
Test name
Test status
Simulation time 30154710583 ps
CPU time 1744.24 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:38:00 PM PDT 24
Peak memory 267864 kb
Host smart-1a869fbe-b7c3-459c-aef7-13246c150989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430202629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1430202629
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3815415818
Short name T117
Test name
Test status
Simulation time 20035997990 ps
CPU time 346.46 seconds
Started Jun 26 07:05:10 PM PDT 24
Finished Jun 26 07:10:58 PM PDT 24
Peak memory 270348 kb
Host smart-0ae581ff-d407-4c43-bd0f-ee7681dc6293
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815415818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3815415818
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.538004832
Short name T138
Test name
Test status
Simulation time 60835064033 ps
CPU time 1135.11 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:24:42 PM PDT 24
Peak memory 265564 kb
Host smart-0d57de68-f23a-48d7-a533-265cdac5873e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538004832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.538004832
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3450173267
Short name T105
Test name
Test status
Simulation time 175323610806 ps
CPU time 2636.65 seconds
Started Jun 26 07:10:30 PM PDT 24
Finished Jun 26 07:54:29 PM PDT 24
Peak memory 301336 kb
Host smart-3e11f4a2-cdad-4a48-894a-1cd01393d130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450173267 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3450173267
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2503784309
Short name T21
Test name
Test status
Simulation time 202161672225 ps
CPU time 2964.3 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:58:21 PM PDT 24
Peak memory 290180 kb
Host smart-1f63bc83-3990-4baa-8ac4-84996801d482
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503784309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2503784309
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2145932582
Short name T140
Test name
Test status
Simulation time 310803720061 ps
CPU time 1398.18 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:29:08 PM PDT 24
Peak memory 265468 kb
Host smart-b4407839-6e1e-49f7-a9aa-94b88e07777f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145932582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2145932582
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2927750593
Short name T285
Test name
Test status
Simulation time 54367943225 ps
CPU time 3380.26 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 08:04:29 PM PDT 24
Peak memory 289676 kb
Host smart-433471a4-271d-4ab3-b193-6399c1c00760
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927750593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2927750593
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2060269071
Short name T115
Test name
Test status
Simulation time 6853687074 ps
CPU time 268.91 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:10:01 PM PDT 24
Peak memory 273640 kb
Host smart-466b7beb-886f-496a-ba7c-686a5e09ea45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2060269071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2060269071
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1321506008
Short name T237
Test name
Test status
Simulation time 30807187 ps
CPU time 1.54 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:06:18 PM PDT 24
Peak memory 237624 kb
Host smart-36c2471b-d6e7-40e8-88e3-7a218b1e7152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1321506008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1321506008
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1327388157
Short name T41
Test name
Test status
Simulation time 98560514820 ps
CPU time 366.48 seconds
Started Jun 26 07:08:00 PM PDT 24
Finished Jun 26 07:14:08 PM PDT 24
Peak memory 249452 kb
Host smart-44f9e2f6-3855-45c1-beeb-3be9b967318f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327388157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1327388157
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2712541612
Short name T121
Test name
Test status
Simulation time 3377451716 ps
CPU time 138.96 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:08:23 PM PDT 24
Peak memory 265576 kb
Host smart-6e4a38dc-e023-4877-8ee5-1d17f96f637c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2712541612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2712541612
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2795155785
Short name T9
Test name
Test status
Simulation time 7826333470 ps
CPU time 321.45 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:13:27 PM PDT 24
Peak memory 255324 kb
Host smart-4417c5c4-e971-49f2-b4a1-d4a55c8f008b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795155785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2795155785
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1703026663
Short name T312
Test name
Test status
Simulation time 72586179805 ps
CPU time 2539.43 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:49:26 PM PDT 24
Peak memory 286364 kb
Host smart-2d134810-4408-440a-8430-c5bdbf1cd8cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703026663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1703026663
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4259066206
Short name T130
Test name
Test status
Simulation time 4243303172 ps
CPU time 528.44 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:14:22 PM PDT 24
Peak memory 265444 kb
Host smart-16bfc214-78e3-4bc8-ad2e-287f82aff16d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259066206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4259066206
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1042691232
Short name T298
Test name
Test status
Simulation time 91437934610 ps
CPU time 596.55 seconds
Started Jun 26 07:10:28 PM PDT 24
Finished Jun 26 07:20:27 PM PDT 24
Peak memory 256076 kb
Host smart-eb926a39-82aa-4bee-819e-86111279310e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042691232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1042691232
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3810435775
Short name T133
Test name
Test status
Simulation time 6880168082 ps
CPU time 126.97 seconds
Started Jun 26 07:05:42 PM PDT 24
Finished Jun 26 07:07:50 PM PDT 24
Peak memory 265492 kb
Host smart-e1755adb-c385-480c-9715-e67e6d064899
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810435775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3810435775
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3201852458
Short name T296
Test name
Test status
Simulation time 162744138089 ps
CPU time 569.05 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:18:24 PM PDT 24
Peak memory 249104 kb
Host smart-6ea038e8-4fdf-4433-a128-11e9c0a80d21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201852458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3201852458
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3746333637
Short name T284
Test name
Test status
Simulation time 607058557898 ps
CPU time 2642.76 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:52:14 PM PDT 24
Peak memory 282216 kb
Host smart-c1393d5d-77d4-4fab-b95a-86a0594ae29d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746333637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3746333637
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4208362959
Short name T120
Test name
Test status
Simulation time 54913573637 ps
CPU time 454.51 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:13:24 PM PDT 24
Peak memory 269368 kb
Host smart-acb0ae62-5410-4dce-9b58-9c78229ac540
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208362959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4208362959
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2480687159
Short name T323
Test name
Test status
Simulation time 31936030183 ps
CPU time 2068.61 seconds
Started Jun 26 07:08:02 PM PDT 24
Finished Jun 26 07:42:33 PM PDT 24
Peak memory 273964 kb
Host smart-950b4eff-a0bd-4a37-9b58-bf9113ddaf91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480687159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2480687159
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.274419008
Short name T190
Test name
Test status
Simulation time 210398621005 ps
CPU time 5163.88 seconds
Started Jun 26 07:10:45 PM PDT 24
Finished Jun 26 08:36:51 PM PDT 24
Peak memory 355268 kb
Host smart-d5237057-83e0-4d70-b2a7-ae4556477c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274419008 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.274419008
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1558942012
Short name T281
Test name
Test status
Simulation time 37432328550 ps
CPU time 1119.59 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:26:12 PM PDT 24
Peak memory 271224 kb
Host smart-0236f953-e004-40ec-bbcf-fb1861f0080a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558942012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1558942012
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2715108406
Short name T108
Test name
Test status
Simulation time 360183757706 ps
CPU time 2409.73 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:49:32 PM PDT 24
Peak memory 282968 kb
Host smart-f8545ae7-8c59-43bc-8d07-95302a68501a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715108406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2715108406
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4262778144
Short name T608
Test name
Test status
Simulation time 44072326802 ps
CPU time 490.85 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:17:05 PM PDT 24
Peak memory 249400 kb
Host smart-5c092abe-ed7e-4896-b9aa-47282960dd44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262778144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4262778144
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2389593379
Short name T126
Test name
Test status
Simulation time 6523953658 ps
CPU time 578.55 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:15:27 PM PDT 24
Peak memory 265440 kb
Host smart-81c3ba2c-e5f4-4ed0-bdc7-80018a808c5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389593379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2389593379
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1877837355
Short name T319
Test name
Test status
Simulation time 473077010550 ps
CPU time 2220.65 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:45:57 PM PDT 24
Peak memory 285344 kb
Host smart-8ee0f832-4fe7-48db-a9ec-e832a198a81e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877837355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1877837355
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.510790716
Short name T288
Test name
Test status
Simulation time 91811640818 ps
CPU time 333.86 seconds
Started Jun 26 07:06:30 PM PDT 24
Finished Jun 26 07:12:05 PM PDT 24
Peak memory 249440 kb
Host smart-662d8522-7582-46b7-b4c4-8a2b03543579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510790716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.510790716
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1826179051
Short name T134
Test name
Test status
Simulation time 12422558802 ps
CPU time 358.09 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:11:43 PM PDT 24
Peak memory 265452 kb
Host smart-6cb10a71-1247-475a-8f26-bc9a31d3130a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826179051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1826179051
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4097236299
Short name T131
Test name
Test status
Simulation time 6085624940 ps
CPU time 341.57 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:11:32 PM PDT 24
Peak memory 265504 kb
Host smart-5eebbc75-d707-4222-a3b8-d3dbd1140eaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4097236299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4097236299
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1748929892
Short name T705
Test name
Test status
Simulation time 11114608 ps
CPU time 1.62 seconds
Started Jun 26 07:05:55 PM PDT 24
Finished Jun 26 07:05:59 PM PDT 24
Peak memory 237604 kb
Host smart-b990e2d4-a12c-4082-969b-468cc301b08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1748929892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1748929892
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2561944271
Short name T191
Test name
Test status
Simulation time 11935711734 ps
CPU time 877.09 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:23:33 PM PDT 24
Peak memory 273752 kb
Host smart-8f84b6a2-7181-43ac-b18d-72bc274743ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561944271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2561944271
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3316283995
Short name T95
Test name
Test status
Simulation time 70260400606 ps
CPU time 4962.67 seconds
Started Jun 26 07:09:41 PM PDT 24
Finished Jun 26 08:32:27 PM PDT 24
Peak memory 314752 kb
Host smart-12db374b-b105-4c3b-a390-28de5b9abaa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316283995 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3316283995
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3861192180
Short name T89
Test name
Test status
Simulation time 70362538325 ps
CPU time 2373.81 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:47:07 PM PDT 24
Peak memory 290068 kb
Host smart-6706ec86-b477-4ece-a886-3bd9d80bc5b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861192180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3861192180
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1978560937
Short name T700
Test name
Test status
Simulation time 22624891847 ps
CPU time 471.77 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:17:50 PM PDT 24
Peak memory 255764 kb
Host smart-573e12e1-6d48-4c6d-9216-46cdc54d4aac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978560937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1978560937
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3892955873
Short name T79
Test name
Test status
Simulation time 33943523301 ps
CPU time 1534.23 seconds
Started Jun 26 07:10:12 PM PDT 24
Finished Jun 26 07:35:47 PM PDT 24
Peak memory 299960 kb
Host smart-c8a26071-f294-4901-ab1f-20441935d993
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892955873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3892955873
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1444179558
Short name T162
Test name
Test status
Simulation time 137072194 ps
CPU time 7.16 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 237596 kb
Host smart-9f4b9f64-e84d-4d04-81b9-554673d4e940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1444179558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1444179558
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3402947430
Short name T132
Test name
Test status
Simulation time 55065402508 ps
CPU time 459.66 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:13:12 PM PDT 24
Peak memory 265448 kb
Host smart-a692232a-92e1-43d1-819d-751839227bb7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402947430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3402947430
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3654937599
Short name T7
Test name
Test status
Simulation time 21728450 ps
CPU time 3.02 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:17 PM PDT 24
Peak memory 249588 kb
Host smart-879fa6b7-5921-41f0-9fc5-8ec0f353603c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3654937599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3654937599
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3870252178
Short name T192
Test name
Test status
Simulation time 28854319 ps
CPU time 3.16 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:06:22 PM PDT 24
Peak memory 249612 kb
Host smart-dece4a0f-2df5-4009-8fa5-19e7a4aa74b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3870252178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3870252178
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3650058985
Short name T82
Test name
Test status
Simulation time 65748622 ps
CPU time 3.35 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:07:08 PM PDT 24
Peak memory 249616 kb
Host smart-981363e0-3289-4bda-85cc-b210eb0e3339
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3650058985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3650058985
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.954817872
Short name T205
Test name
Test status
Simulation time 35246627 ps
CPU time 4.17 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:07:34 PM PDT 24
Peak memory 249556 kb
Host smart-da14fee4-fc70-4128-b81a-f3ba3605ab3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=954817872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.954817872
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2298676258
Short name T305
Test name
Test status
Simulation time 57098140669 ps
CPU time 617.37 seconds
Started Jun 26 07:06:18 PM PDT 24
Finished Jun 26 07:16:37 PM PDT 24
Peak memory 265804 kb
Host smart-14cd5584-ff81-4f9b-95c6-36e457f40dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298676258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2298676258
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3068230692
Short name T73
Test name
Test status
Simulation time 123334431681 ps
CPU time 3778.9 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 08:10:07 PM PDT 24
Peak memory 303492 kb
Host smart-5365eeaf-af37-4b7f-a4a6-949283b4a75b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068230692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3068230692
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2337797823
Short name T24
Test name
Test status
Simulation time 1548166014 ps
CPU time 44.9 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:53 PM PDT 24
Peak memory 256400 kb
Host smart-2053908a-9d7a-4d32-9423-dc189f84fdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23377
97823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2337797823
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3065663474
Short name T241
Test name
Test status
Simulation time 83769890370 ps
CPU time 1852.84 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:37:40 PM PDT 24
Peak memory 297928 kb
Host smart-4484744b-3658-4c1c-b2b5-be5cd5ea8df8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065663474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3065663474
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1921292398
Short name T143
Test name
Test status
Simulation time 7882798630 ps
CPU time 357.28 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:11:47 PM PDT 24
Peak memory 265440 kb
Host smart-91d0abe2-fdea-4376-b036-147cebf7ccfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921292398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1921292398
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1309843505
Short name T144
Test name
Test status
Simulation time 8534902230 ps
CPU time 626.83 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:16:17 PM PDT 24
Peak memory 265548 kb
Host smart-83b62cda-7056-4964-b661-29da31a86c7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309843505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1309843505
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3460067673
Short name T151
Test name
Test status
Simulation time 8653533205 ps
CPU time 168.9 seconds
Started Jun 26 07:05:56 PM PDT 24
Finished Jun 26 07:08:47 PM PDT 24
Peak memory 265488 kb
Host smart-eecddd26-1a88-4254-92e2-3bf4a60118e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460067673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3460067673
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.842452178
Short name T145
Test name
Test status
Simulation time 8812915605 ps
CPU time 565.46 seconds
Started Jun 26 07:05:09 PM PDT 24
Finished Jun 26 07:14:37 PM PDT 24
Peak memory 265644 kb
Host smart-96b6d8d3-0f93-4aaf-a894-70153d0e7026
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842452178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.842452178
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2748046684
Short name T724
Test name
Test status
Simulation time 16160669 ps
CPU time 1.63 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:01 PM PDT 24
Peak memory 237636 kb
Host smart-1757fa44-094c-40a1-8a7a-d282d322359e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2748046684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2748046684
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1292559791
Short name T303
Test name
Test status
Simulation time 32505426761 ps
CPU time 718.74 seconds
Started Jun 26 07:06:18 PM PDT 24
Finished Jun 26 07:18:19 PM PDT 24
Peak memory 255920 kb
Host smart-d9771745-c51c-4488-b2d0-770c9176347a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292559791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1292559791
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.98630638
Short name T258
Test name
Test status
Simulation time 381089841771 ps
CPU time 1586.17 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:32:42 PM PDT 24
Peak memory 267844 kb
Host smart-07afd49b-804d-4557-8bca-0339175f163b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98630638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.98630638
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.516980895
Short name T261
Test name
Test status
Simulation time 8025532657 ps
CPU time 818.19 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:20:41 PM PDT 24
Peak memory 273784 kb
Host smart-0533bece-8342-4b7b-9415-c5289d5083a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516980895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.516980895
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.336093495
Short name T326
Test name
Test status
Simulation time 27262904284 ps
CPU time 1883.47 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:38:30 PM PDT 24
Peak memory 289564 kb
Host smart-e69e0052-4f97-4508-b585-1eb24d2e2624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336093495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.336093495
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2693665054
Short name T106
Test name
Test status
Simulation time 15113213458 ps
CPU time 883.73 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:21:51 PM PDT 24
Peak memory 265796 kb
Host smart-1a9a191a-5ce7-4253-af4a-b4d400256b05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693665054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2693665054
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2730071034
Short name T268
Test name
Test status
Simulation time 141298953907 ps
CPU time 5124.56 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 08:32:31 PM PDT 24
Peak memory 322224 kb
Host smart-3a889436-4dc2-4dbb-a5d9-f2bb4cc74023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730071034 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2730071034
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3505161598
Short name T324
Test name
Test status
Simulation time 159855398211 ps
CPU time 2511.64 seconds
Started Jun 26 07:07:33 PM PDT 24
Finished Jun 26 07:49:26 PM PDT 24
Peak memory 289360 kb
Host smart-d6646739-1ba8-4bb8-bc29-cf18efdee6fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505161598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3505161598
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1285691375
Short name T701
Test name
Test status
Simulation time 5211400117 ps
CPU time 212.48 seconds
Started Jun 26 07:08:11 PM PDT 24
Finished Jun 26 07:11:46 PM PDT 24
Peak memory 249372 kb
Host smart-d875b5d1-298d-465c-8042-eb7c0a6dc698
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285691375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1285691375
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2726867157
Short name T662
Test name
Test status
Simulation time 32062876293 ps
CPU time 1970.51 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:39:09 PM PDT 24
Peak memory 284232 kb
Host smart-9357752a-1ba6-4138-8ab4-a241bc2d9cfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726867157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2726867157
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2988385066
Short name T3
Test name
Test status
Simulation time 76894020693 ps
CPU time 2290.74 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:46:18 PM PDT 24
Peak memory 290288 kb
Host smart-e9b8de89-9948-479e-8109-da9eae22e8be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988385066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2988385066
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1621763793
Short name T77
Test name
Test status
Simulation time 225218356062 ps
CPU time 3441.54 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 08:05:33 PM PDT 24
Peak memory 290312 kb
Host smart-f7015452-a391-4367-b93d-b055248fb6fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621763793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1621763793
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2664474134
Short name T328
Test name
Test status
Simulation time 20726637556 ps
CPU time 1355.35 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:31:33 PM PDT 24
Peak memory 273308 kb
Host smart-2d58dd53-77a2-4047-8c9b-c6e354f6c44c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664474134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2664474134
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4022436055
Short name T19
Test name
Test status
Simulation time 2334839226 ps
CPU time 25.45 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:06:39 PM PDT 24
Peak memory 256660 kb
Host smart-b6b9551e-a03c-4c80-8047-c2d7cdae215a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40224
36055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4022436055
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.671095355
Short name T266
Test name
Test status
Simulation time 139162968 ps
CPU time 4.46 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:06:21 PM PDT 24
Peak memory 241160 kb
Host smart-397fbfb5-a919-4387-b9d1-0ec13a1b041c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67109
5355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.671095355
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1376643846
Short name T280
Test name
Test status
Simulation time 15172652542 ps
CPU time 1662.62 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:37:02 PM PDT 24
Peak memory 290176 kb
Host smart-39d1e080-628a-41e9-846f-e985d7dcc73e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376643846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1376643846
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3837689043
Short name T53
Test name
Test status
Simulation time 3863789723 ps
CPU time 56.79 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:10:16 PM PDT 24
Peak memory 249136 kb
Host smart-49f69876-b8eb-4bcd-9f24-a00aeba47cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38376
89043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3837689043
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3836038223
Short name T242
Test name
Test status
Simulation time 42392729024 ps
CPU time 5209.02 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 08:36:23 PM PDT 24
Peak memory 338844 kb
Host smart-82cdc828-2c49-417c-b48a-55f9d675dc96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836038223 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3836038223
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4101879225
Short name T239
Test name
Test status
Simulation time 726900522 ps
CPU time 7.53 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:10:22 PM PDT 24
Peak memory 241600 kb
Host smart-982fa34b-85de-4020-a3f2-1fdab652d1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41018
79225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4101879225
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.180915691
Short name T247
Test name
Test status
Simulation time 111390195436 ps
CPU time 3840.64 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 08:10:48 PM PDT 24
Peak memory 306684 kb
Host smart-72189e59-2dcc-483d-bac0-cdd74ca0e0f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180915691 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.180915691
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.722976583
Short name T149
Test name
Test status
Simulation time 8106715854 ps
CPU time 152.76 seconds
Started Jun 26 07:05:10 PM PDT 24
Finished Jun 26 07:07:44 PM PDT 24
Peak memory 268696 kb
Host smart-397a38b9-9ae8-4ec9-a654-10746bddab5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=722976583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.722976583
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2642375634
Short name T155
Test name
Test status
Simulation time 1297402392 ps
CPU time 87.82 seconds
Started Jun 26 07:05:41 PM PDT 24
Finished Jun 26 07:07:10 PM PDT 24
Peak memory 237644 kb
Host smart-906ca792-996c-49a7-bb47-d7a0aa638ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2642375634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2642375634
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1962927866
Short name T159
Test name
Test status
Simulation time 481195739 ps
CPU time 40.42 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 240564 kb
Host smart-8c04e91d-bc1a-4579-bd27-e785929f0029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1962927866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1962927866
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1167492422
Short name T161
Test name
Test status
Simulation time 4381024538 ps
CPU time 69.38 seconds
Started Jun 26 07:05:50 PM PDT 24
Finished Jun 26 07:07:02 PM PDT 24
Peak memory 238972 kb
Host smart-91fd2b6c-c427-4a69-932c-ec75377bfc35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1167492422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1167492422
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2344100304
Short name T167
Test name
Test status
Simulation time 605451252 ps
CPU time 38.55 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 237848 kb
Host smart-7266ca38-4258-495b-95fe-3859a542ede9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2344100304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2344100304
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2580568454
Short name T160
Test name
Test status
Simulation time 1929611045 ps
CPU time 42.46 seconds
Started Jun 26 07:05:30 PM PDT 24
Finished Jun 26 07:06:14 PM PDT 24
Peak memory 237684 kb
Host smart-86bc7701-e467-46e1-8a24-127b9885b85e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2580568454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2580568454
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.263880155
Short name T163
Test name
Test status
Simulation time 58244943 ps
CPU time 2.1 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:49 PM PDT 24
Peak memory 237644 kb
Host smart-6f40be7b-fa1b-4a74-ae2b-434cbf382e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=263880155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.263880155
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4145045393
Short name T127
Test name
Test status
Simulation time 9974049064 ps
CPU time 149.91 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:07:52 PM PDT 24
Peak memory 265432 kb
Host smart-978bef03-8630-4e9b-b3e0-6c9bd6570f6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4145045393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4145045393
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3479164354
Short name T166
Test name
Test status
Simulation time 30974980 ps
CPU time 2.86 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:05:48 PM PDT 24
Peak memory 238660 kb
Host smart-1f2d2b5d-af03-4fd3-91b8-420a1ede0a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3479164354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3479164354
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3364338505
Short name T116
Test name
Test status
Simulation time 7721618393 ps
CPU time 273.79 seconds
Started Jun 26 07:05:49 PM PDT 24
Finished Jun 26 07:10:26 PM PDT 24
Peak memory 265368 kb
Host smart-31fae9cb-b219-41fa-b522-9ad3ffae546c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364338505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3364338505
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3916836194
Short name T154
Test name
Test status
Simulation time 999002813 ps
CPU time 67.01 seconds
Started Jun 26 07:05:49 PM PDT 24
Finished Jun 26 07:06:59 PM PDT 24
Peak memory 240516 kb
Host smart-c033af3a-9e13-4f95-a21d-53ebf623d712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3916836194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3916836194
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3314836839
Short name T169
Test name
Test status
Simulation time 1847058418 ps
CPU time 76.48 seconds
Started Jun 26 07:05:56 PM PDT 24
Finished Jun 26 07:07:14 PM PDT 24
Peak memory 245816 kb
Host smart-a2a6a9e7-a861-42ba-9bd4-6fed9526452b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3314836839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3314836839
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1315967298
Short name T168
Test name
Test status
Simulation time 2769851127 ps
CPU time 28.5 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:07:16 PM PDT 24
Peak memory 240424 kb
Host smart-8e437099-5017-4828-9559-8e9699e897a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1315967298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1315967298
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1777598837
Short name T170
Test name
Test status
Simulation time 60617370 ps
CPU time 3.87 seconds
Started Jun 26 07:05:08 PM PDT 24
Finished Jun 26 07:05:14 PM PDT 24
Peak memory 238612 kb
Host smart-fe3ec1d3-c068-4129-995b-65ccb10dd26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1777598837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1777598837
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1148017744
Short name T165
Test name
Test status
Simulation time 1926448164 ps
CPU time 35.87 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:24 PM PDT 24
Peak memory 240716 kb
Host smart-b5fee8d5-f6cc-4d9a-955d-9eec9e3962c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1148017744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1148017744
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1671994125
Short name T171
Test name
Test status
Simulation time 1246856764 ps
CPU time 82.62 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:07:10 PM PDT 24
Peak memory 240600 kb
Host smart-09ffcd94-733d-4d06-a56c-e97d53181462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1671994125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1671994125
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1388812242
Short name T175
Test name
Test status
Simulation time 94322653 ps
CPU time 2.69 seconds
Started Jun 26 07:05:47 PM PDT 24
Finished Jun 26 07:05:53 PM PDT 24
Peak memory 237600 kb
Host smart-5d4ad01e-2380-4fb5-a4c2-22e48d09c777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1388812242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1388812242
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.378780609
Short name T164
Test name
Test status
Simulation time 63308660 ps
CPU time 3.34 seconds
Started Jun 26 07:05:54 PM PDT 24
Finished Jun 26 07:05:59 PM PDT 24
Peak memory 238636 kb
Host smart-20bba08f-7f7a-47b9-acb4-1d92e9507f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=378780609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.378780609
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1882374140
Short name T14
Test name
Test status
Simulation time 46580200017 ps
CPU time 2549.4 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:51:22 PM PDT 24
Peak memory 286152 kb
Host smart-2cd34075-ec94-43ee-8dd2-ab9567acb6b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882374140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1882374140
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.670405480
Short name T15
Test name
Test status
Simulation time 3956538568 ps
CPU time 80.87 seconds
Started Jun 26 07:09:44 PM PDT 24
Finished Jun 26 07:11:07 PM PDT 24
Peak memory 256708 kb
Host smart-f81529e7-5432-4f06-a594-bc853a714093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67040
5480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.670405480
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.555260928
Short name T792
Test name
Test status
Simulation time 1172077929 ps
CPU time 147.24 seconds
Started Jun 26 07:05:07 PM PDT 24
Finished Jun 26 07:07:36 PM PDT 24
Peak memory 240576 kb
Host smart-631328da-6bcc-49df-b3ab-757950e1a001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=555260928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.555260928
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4171947199
Short name T785
Test name
Test status
Simulation time 5959067345 ps
CPU time 376.44 seconds
Started Jun 26 07:05:10 PM PDT 24
Finished Jun 26 07:11:28 PM PDT 24
Peak memory 240756 kb
Host smart-b04e6785-fde5-4bd5-9c07-09a1c8f19944
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4171947199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4171947199
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1799743625
Short name T775
Test name
Test status
Simulation time 916153143 ps
CPU time 5.62 seconds
Started Jun 26 07:05:07 PM PDT 24
Finished Jun 26 07:05:15 PM PDT 24
Peak memory 248780 kb
Host smart-59529234-5645-4083-a850-40ce6d5c2642
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1799743625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1799743625
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3899033223
Short name T788
Test name
Test status
Simulation time 120501225 ps
CPU time 6.34 seconds
Started Jun 26 07:05:08 PM PDT 24
Finished Jun 26 07:05:15 PM PDT 24
Peak memory 249832 kb
Host smart-87f484a1-9d35-46d8-bdbf-936eb6dfdf5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899033223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3899033223
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2701731240
Short name T726
Test name
Test status
Simulation time 121152337 ps
CPU time 5.38 seconds
Started Jun 26 07:05:08 PM PDT 24
Finished Jun 26 07:05:15 PM PDT 24
Peak memory 237636 kb
Host smart-79238e21-4a46-4bce-9f08-a428921eb725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2701731240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2701731240
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3553019998
Short name T716
Test name
Test status
Simulation time 11969863 ps
CPU time 1.35 seconds
Started Jun 26 07:05:11 PM PDT 24
Finished Jun 26 07:05:13 PM PDT 24
Peak memory 237652 kb
Host smart-b4c36ac0-7512-4011-a7b1-eb39048b85c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3553019998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3553019998
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1917576229
Short name T754
Test name
Test status
Simulation time 228864140 ps
CPU time 11.37 seconds
Started Jun 26 07:05:08 PM PDT 24
Finished Jun 26 07:05:21 PM PDT 24
Peak memory 245832 kb
Host smart-cc222677-1e75-4c3b-8ecf-e733a3915636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1917576229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1917576229
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.232110867
Short name T789
Test name
Test status
Simulation time 1699216395 ps
CPU time 28.86 seconds
Started Jun 26 07:05:09 PM PDT 24
Finished Jun 26 07:05:40 PM PDT 24
Peak memory 248844 kb
Host smart-b084192d-5f09-4b68-be84-d2fbb759eff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=232110867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.232110867
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2652952037
Short name T729
Test name
Test status
Simulation time 6346629056 ps
CPU time 272.99 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:09:58 PM PDT 24
Peak memory 240596 kb
Host smart-93e44618-b9c5-464a-962d-73f894a28da4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2652952037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2652952037
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.496195835
Short name T797
Test name
Test status
Simulation time 3865815346 ps
CPU time 224.8 seconds
Started Jun 26 07:05:18 PM PDT 24
Finished Jun 26 07:09:04 PM PDT 24
Peak memory 236736 kb
Host smart-100175b4-71f3-4d31-9813-a9642c5c9d3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=496195835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.496195835
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.618153721
Short name T811
Test name
Test status
Simulation time 521540650 ps
CPU time 10.33 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:05:31 PM PDT 24
Peak memory 249280 kb
Host smart-0cd62dd9-2385-4a5f-858d-0efea3ece187
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=618153721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.618153721
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3146980049
Short name T747
Test name
Test status
Simulation time 128452982 ps
CPU time 11.6 seconds
Started Jun 26 07:05:18 PM PDT 24
Finished Jun 26 07:05:31 PM PDT 24
Peak memory 243656 kb
Host smart-ab26aa9a-fac7-4d42-9b69-31fee6d79a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146980049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3146980049
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1013678991
Short name T765
Test name
Test status
Simulation time 127897004 ps
CPU time 9.78 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:05:30 PM PDT 24
Peak memory 237636 kb
Host smart-5cc2522c-debd-4bc2-8985-f5d3c2abbf64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1013678991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1013678991
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.719535589
Short name T817
Test name
Test status
Simulation time 13997163 ps
CPU time 1.46 seconds
Started Jun 26 07:05:22 PM PDT 24
Finished Jun 26 07:05:25 PM PDT 24
Peak memory 237620 kb
Host smart-ab01509f-0ebd-4ba9-8dcc-e612870c5e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=719535589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.719535589
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3071345943
Short name T728
Test name
Test status
Simulation time 166240234 ps
CPU time 26.55 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:05:47 PM PDT 24
Peak memory 245820 kb
Host smart-f6211a62-118d-4da3-bc3e-3f1e9f63ee54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3071345943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3071345943
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.127928282
Short name T746
Test name
Test status
Simulation time 145474331 ps
CPU time 9.62 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:06:57 PM PDT 24
Peak memory 248652 kb
Host smart-a0e8cdfa-a208-4e78-9acd-bd5a036f9767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127928282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.127928282
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1199505283
Short name T756
Test name
Test status
Simulation time 98854292 ps
CPU time 2.53 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:05:27 PM PDT 24
Peak memory 238092 kb
Host smart-a8f7f577-b109-4d9f-95ef-774d0e329407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1199505283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1199505283
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.523810765
Short name T796
Test name
Test status
Simulation time 202882708 ps
CPU time 15.18 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 252456 kb
Host smart-9461ce2b-7130-41fb-b2e2-1da97c1bb6ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523810765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.523810765
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1488994004
Short name T753
Test name
Test status
Simulation time 364271704 ps
CPU time 4.54 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:05:52 PM PDT 24
Peak memory 240548 kb
Host smart-551000bc-9e3c-4bdb-80f0-90fea45ed0be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1488994004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1488994004
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3049946791
Short name T801
Test name
Test status
Simulation time 20542102 ps
CPU time 1.4 seconds
Started Jun 26 07:05:42 PM PDT 24
Finished Jun 26 07:05:45 PM PDT 24
Peak memory 236648 kb
Host smart-38ba6c39-7cf0-4e83-8483-bef0b8dbe9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3049946791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3049946791
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2080635673
Short name T779
Test name
Test status
Simulation time 687115739 ps
CPU time 28.36 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:18 PM PDT 24
Peak memory 245832 kb
Host smart-86df8ae3-f988-469b-ae43-44337870b3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2080635673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2080635673
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3608928675
Short name T763
Test name
Test status
Simulation time 375942014 ps
CPU time 13.51 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 248652 kb
Host smart-23bfb443-7595-49b0-b0cb-a9559c1c9de9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3608928675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3608928675
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1885197539
Short name T781
Test name
Test status
Simulation time 207276944 ps
CPU time 9.47 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:05:59 PM PDT 24
Peak memory 252040 kb
Host smart-3bdbfd67-e0a3-4118-be6a-95ee8fd27a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885197539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1885197539
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3665344054
Short name T235
Test name
Test status
Simulation time 77822589 ps
CPU time 5.53 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:53 PM PDT 24
Peak memory 240540 kb
Host smart-e1c0e5b1-ba2c-4ba1-8882-d7148cbe667c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3665344054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3665344054
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2379189268
Short name T708
Test name
Test status
Simulation time 10328676 ps
CPU time 1.61 seconds
Started Jun 26 07:05:50 PM PDT 24
Finished Jun 26 07:05:54 PM PDT 24
Peak memory 235604 kb
Host smart-0393a53e-fd5c-47be-ae5c-65f7cfb0c623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2379189268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2379189268
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4159376457
Short name T179
Test name
Test status
Simulation time 100306443 ps
CPU time 11.99 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 248800 kb
Host smart-ac54962e-0332-4805-b11b-f229d785eba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4159376457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4159376457
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.716232173
Short name T135
Test name
Test status
Simulation time 1925764885 ps
CPU time 140.87 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:08:06 PM PDT 24
Peak memory 265356 kb
Host smart-6790d876-da03-47ca-8808-a55fe9bd227d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=716232173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.716232173
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2747765433
Short name T774
Test name
Test status
Simulation time 1064401570 ps
CPU time 9.67 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:56 PM PDT 24
Peak memory 248844 kb
Host smart-0e39363e-1772-4cb9-b2b6-40e700db2e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2747765433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2747765433
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.68955551
Short name T742
Test name
Test status
Simulation time 135908035 ps
CPU time 11.11 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 251292 kb
Host smart-ec267695-d2c9-49b2-8fc3-ae6ba8d5296b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68955551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.alert_handler_csr_mem_rw_with_rand_reset.68955551
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3539899504
Short name T755
Test name
Test status
Simulation time 125216257 ps
CPU time 5.38 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:05:53 PM PDT 24
Peak memory 236668 kb
Host smart-6a01086f-153f-4381-ae58-92c92eb98f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3539899504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3539899504
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3240958469
Short name T752
Test name
Test status
Simulation time 7500092 ps
CPU time 1.44 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:05:50 PM PDT 24
Peak memory 237648 kb
Host smart-7df239c0-a6e9-419b-b4a0-7d3ef3693204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3240958469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3240958469
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.665933539
Short name T745
Test name
Test status
Simulation time 322635538 ps
CPU time 11.91 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 245804 kb
Host smart-97aa6da0-4ef8-4c8d-aa3a-138ab53c51cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=665933539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.665933539
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.304065324
Short name T125
Test name
Test status
Simulation time 20570975434 ps
CPU time 422.6 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:12:53 PM PDT 24
Peak memory 272876 kb
Host smart-5c21a42e-a367-4428-bab2-1964bc44a545
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=304065324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.304065324
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3227384342
Short name T784
Test name
Test status
Simulation time 4088768775 ps
CPU time 21.89 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:11 PM PDT 24
Peak memory 257176 kb
Host smart-709b4e61-f201-4b7e-89c9-2e403af5b07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3227384342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3227384342
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1931599668
Short name T771
Test name
Test status
Simulation time 177877257 ps
CPU time 13.86 seconds
Started Jun 26 07:05:47 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 252880 kb
Host smart-65eae546-7862-4e76-996a-894ef54d218c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931599668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1931599668
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1789914710
Short name T236
Test name
Test status
Simulation time 225152500 ps
CPU time 9.22 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:05:58 PM PDT 24
Peak memory 240604 kb
Host smart-2ca4863a-030d-4503-8dfb-e40fcb46bd58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1789914710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1789914710
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1768109267
Short name T820
Test name
Test status
Simulation time 7733921 ps
CPU time 1.42 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:49 PM PDT 24
Peak memory 235724 kb
Host smart-e1c2ba5b-c3a8-4dae-9544-2d3f7253e930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768109267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1768109267
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2239005177
Short name T807
Test name
Test status
Simulation time 175620597 ps
CPU time 13.36 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 245840 kb
Host smart-415f8c3c-79aa-47d3-a08c-56c25f8b21ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2239005177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2239005177
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3933006529
Short name T738
Test name
Test status
Simulation time 82279852 ps
CPU time 12.65 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:59 PM PDT 24
Peak memory 248864 kb
Host smart-8b597f5c-f381-4f8d-a985-ecb1f8675458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933006529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3933006529
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1945278341
Short name T751
Test name
Test status
Simulation time 592789529 ps
CPU time 8.8 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:05:54 PM PDT 24
Peak memory 240748 kb
Host smart-d3ee73d9-57ed-4ea3-a651-db8e31edb277
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945278341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1945278341
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2604621178
Short name T712
Test name
Test status
Simulation time 543564156 ps
CPU time 4.2 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:51 PM PDT 24
Peak memory 239552 kb
Host smart-694aa91d-bb9f-4ad0-8df6-582e119c926a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2604621178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2604621178
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2307100479
Short name T782
Test name
Test status
Simulation time 8564528 ps
CPU time 1.63 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:05:52 PM PDT 24
Peak memory 237604 kb
Host smart-f79c2bc5-a2bc-456a-9652-b260fc904273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2307100479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2307100479
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3180178642
Short name T732
Test name
Test status
Simulation time 882759109 ps
CPU time 20.19 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:09 PM PDT 24
Peak memory 240592 kb
Host smart-bd0c6026-a45c-4e04-9586-c77a40e635b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3180178642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3180178642
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3824125376
Short name T808
Test name
Test status
Simulation time 263403638 ps
CPU time 16.68 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 248340 kb
Host smart-d132fe5c-431a-4099-a6c5-29871e100aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3824125376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3824125376
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3973011646
Short name T736
Test name
Test status
Simulation time 442367496 ps
CPU time 10.29 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 239692 kb
Host smart-24101484-b229-42ea-a511-af8492b2bd06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973011646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3973011646
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3014285129
Short name T806
Test name
Test status
Simulation time 53086863 ps
CPU time 4.81 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:05:55 PM PDT 24
Peak memory 240664 kb
Host smart-0b86da27-3f36-4169-b740-11df7f7be6e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3014285129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3014285129
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2984436906
Short name T750
Test name
Test status
Simulation time 9551781 ps
CPU time 1.37 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:49 PM PDT 24
Peak memory 237592 kb
Host smart-b0ff64f7-4877-4e4f-a918-2e7ce51d4385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984436906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2984436906
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2117727158
Short name T181
Test name
Test status
Simulation time 1889996430 ps
CPU time 20.65 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:06:07 PM PDT 24
Peak memory 244868 kb
Host smart-66c2737a-3307-4d18-96b5-a0b56fcb5397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2117727158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2117727158
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.103753641
Short name T119
Test name
Test status
Simulation time 6983578370 ps
CPU time 105.73 seconds
Started Jun 26 07:05:47 PM PDT 24
Finished Jun 26 07:07:36 PM PDT 24
Peak memory 265504 kb
Host smart-31782995-73f4-45fc-a363-bf4d1580023c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103753641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.103753641
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3485051076
Short name T136
Test name
Test status
Simulation time 2413836997 ps
CPU time 350.25 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:11:37 PM PDT 24
Peak memory 270508 kb
Host smart-e8564cb0-6492-441d-94c9-23c9acc06e56
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485051076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3485051076
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.339913726
Short name T822
Test name
Test status
Simulation time 344042197 ps
CPU time 27.84 seconds
Started Jun 26 07:05:49 PM PDT 24
Finished Jun 26 07:06:20 PM PDT 24
Peak memory 248792 kb
Host smart-1d149ca2-69fe-43e2-a23d-e81315cb7f96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339913726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.339913726
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2814281061
Short name T810
Test name
Test status
Simulation time 68604534 ps
CPU time 5.28 seconds
Started Jun 26 07:05:50 PM PDT 24
Finished Jun 26 07:05:58 PM PDT 24
Peak memory 238128 kb
Host smart-b24137b9-175e-4336-bfd4-9e351821c7d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814281061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2814281061
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1379158904
Short name T818
Test name
Test status
Simulation time 112386156 ps
CPU time 6.13 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:05:53 PM PDT 24
Peak memory 237736 kb
Host smart-90aa141b-7473-417e-ac6f-813b1e27231a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1379158904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1379158904
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3932866109
Short name T717
Test name
Test status
Simulation time 10944682 ps
CPU time 1.33 seconds
Started Jun 26 07:05:50 PM PDT 24
Finished Jun 26 07:05:54 PM PDT 24
Peak memory 237600 kb
Host smart-849531d5-d1cd-40b6-8c90-2755629777d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3932866109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3932866109
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1105812294
Short name T761
Test name
Test status
Simulation time 3397137390 ps
CPU time 26.89 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:17 PM PDT 24
Peak memory 245876 kb
Host smart-38e08e52-3de0-4c7e-ab63-e6ef7d4a794d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1105812294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1105812294
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2211698514
Short name T128
Test name
Test status
Simulation time 25152936234 ps
CPU time 542.45 seconds
Started Jun 26 07:05:49 PM PDT 24
Finished Jun 26 07:14:54 PM PDT 24
Peak memory 265524 kb
Host smart-5b57c194-7f79-41aa-8d3f-59d2b05a7030
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211698514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2211698514
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4024939301
Short name T795
Test name
Test status
Simulation time 239608652 ps
CPU time 18.08 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:06:07 PM PDT 24
Peak memory 254732 kb
Host smart-6fbc7fc2-36cb-43b7-a096-693c354eb6c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4024939301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4024939301
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.800796440
Short name T777
Test name
Test status
Simulation time 36401403 ps
CPU time 5.89 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:07 PM PDT 24
Peak memory 248804 kb
Host smart-f10c42c0-3b79-45d6-b99f-1944fe46d51c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800796440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.800796440
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3321540731
Short name T805
Test name
Test status
Simulation time 126844796 ps
CPU time 9.06 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:10 PM PDT 24
Peak memory 237596 kb
Host smart-600a1685-5cf1-48db-b9f8-cb1729f3c8ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3321540731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3321540731
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2537364115
Short name T735
Test name
Test status
Simulation time 7682048 ps
CPU time 1.49 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 236716 kb
Host smart-c104b5a8-2b11-4849-b563-9e84e23b021a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2537364115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2537364115
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.535666552
Short name T180
Test name
Test status
Simulation time 701359269 ps
CPU time 51.56 seconds
Started Jun 26 07:05:56 PM PDT 24
Finished Jun 26 07:06:50 PM PDT 24
Peak memory 248768 kb
Host smart-37650d53-60fd-4a3c-a884-b3cc04b11967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=535666552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.535666552
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.174498055
Short name T141
Test name
Test status
Simulation time 18861037607 ps
CPU time 196.79 seconds
Started Jun 26 07:05:45 PM PDT 24
Finished Jun 26 07:09:05 PM PDT 24
Peak memory 271604 kb
Host smart-f74ea485-67c8-48b7-aea3-c4d45788bd88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=174498055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.174498055
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3278908555
Short name T799
Test name
Test status
Simulation time 648793160 ps
CPU time 23.67 seconds
Started Jun 26 07:05:50 PM PDT 24
Finished Jun 26 07:06:16 PM PDT 24
Peak memory 248808 kb
Host smart-09251609-b53e-448c-8245-fe5514fec4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278908555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3278908555
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2114020817
Short name T346
Test name
Test status
Simulation time 113225460 ps
CPU time 5.51 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 241032 kb
Host smart-585b6eeb-ef5d-45ad-a0c6-5b9a47d3ce58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114020817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2114020817
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1119507281
Short name T769
Test name
Test status
Simulation time 103950858 ps
CPU time 3.44 seconds
Started Jun 26 07:05:55 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 239548 kb
Host smart-8932687e-6419-41b5-b49a-0d48e72e75f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1119507281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1119507281
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1777654375
Short name T762
Test name
Test status
Simulation time 661524226 ps
CPU time 24.73 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:28 PM PDT 24
Peak memory 244868 kb
Host smart-b27eada2-7021-49af-8037-6f7d7f2c8c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1777654375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1777654375
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2026470699
Short name T152
Test name
Test status
Simulation time 17332306129 ps
CPU time 1406.23 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:29:31 PM PDT 24
Peak memory 265548 kb
Host smart-9ecc0401-960d-47e7-be4c-728bfc0682c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026470699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2026470699
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.827014550
Short name T725
Test name
Test status
Simulation time 246738259 ps
CPU time 17.32 seconds
Started Jun 26 07:05:56 PM PDT 24
Finished Jun 26 07:06:16 PM PDT 24
Peak memory 248828 kb
Host smart-ecc7799e-7914-47de-add8-aabdb0381bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=827014550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.827014550
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2417014394
Short name T793
Test name
Test status
Simulation time 157151652 ps
CPU time 7.56 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:09 PM PDT 24
Peak memory 241132 kb
Host smart-d33fdb99-c60c-4512-9d9a-3a315c9dbad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417014394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2417014394
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2216600809
Short name T812
Test name
Test status
Simulation time 59380818 ps
CPU time 4.77 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 240528 kb
Host smart-51389eab-5aa8-40e5-9850-cd3258303b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2216600809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2216600809
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1801631651
Short name T718
Test name
Test status
Simulation time 23597777 ps
CPU time 1.33 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 236732 kb
Host smart-f05a5784-6d35-4b71-9186-c63a238a801d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1801631651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1801631651
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3734664084
Short name T737
Test name
Test status
Simulation time 361103246 ps
CPU time 23.79 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:23 PM PDT 24
Peak memory 244876 kb
Host smart-667d6e47-4bf8-4457-8117-a4d1da56fe5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3734664084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3734664084
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2992386223
Short name T113
Test name
Test status
Simulation time 6248710308 ps
CPU time 533.8 seconds
Started Jun 26 07:05:54 PM PDT 24
Finished Jun 26 07:14:49 PM PDT 24
Peak memory 268736 kb
Host smart-78374a50-b379-40c0-a3cc-3086702ba280
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992386223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2992386223
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3779376557
Short name T780
Test name
Test status
Simulation time 102274502 ps
CPU time 6.85 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:08 PM PDT 24
Peak memory 249072 kb
Host smart-a4119fb6-7307-4e80-b062-12dcceaad5d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3779376557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3779376557
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4170944574
Short name T741
Test name
Test status
Simulation time 574241217 ps
CPU time 73.7 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:06:35 PM PDT 24
Peak memory 237628 kb
Host smart-a6b4bea7-a82b-4317-ab59-1da9f266343e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4170944574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4170944574
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3150020221
Short name T733
Test name
Test status
Simulation time 1705401366 ps
CPU time 105.94 seconds
Started Jun 26 07:05:18 PM PDT 24
Finished Jun 26 07:07:05 PM PDT 24
Peak memory 236688 kb
Host smart-4b3ed8d5-d89c-487b-b344-3c02cd01e2a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3150020221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3150020221
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2759092788
Short name T706
Test name
Test status
Simulation time 378156735 ps
CPU time 8.78 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:05:31 PM PDT 24
Peak memory 249128 kb
Host smart-805d0439-d639-4928-91ec-98e678c2f413
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2759092788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2759092788
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.155267809
Short name T345
Test name
Test status
Simulation time 34031996 ps
CPU time 5.41 seconds
Started Jun 26 07:05:19 PM PDT 24
Finished Jun 26 07:05:26 PM PDT 24
Peak memory 242192 kb
Host smart-d86aa704-6d30-4964-b4a5-c5f03f49344c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155267809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.155267809
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.387054971
Short name T174
Test name
Test status
Simulation time 20063759 ps
CPU time 3.55 seconds
Started Jun 26 07:05:24 PM PDT 24
Finished Jun 26 07:05:29 PM PDT 24
Peak memory 237636 kb
Host smart-f33b5305-dd77-403f-9318-c37a1fbb0b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=387054971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.387054971
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3830809624
Short name T794
Test name
Test status
Simulation time 7931671 ps
CPU time 1.58 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:05:23 PM PDT 24
Peak memory 237584 kb
Host smart-d635e6ac-df65-4550-a5d2-743a684c241d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3830809624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3830809624
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.942984171
Short name T790
Test name
Test status
Simulation time 1498486082 ps
CPU time 51.5 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:06:14 PM PDT 24
Peak memory 245808 kb
Host smart-dde7d874-eb29-4e38-9871-4ee3543255af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=942984171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.942984171
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2079025759
Short name T118
Test name
Test status
Simulation time 11587457385 ps
CPU time 198.25 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:08:43 PM PDT 24
Peak memory 265588 kb
Host smart-e48ed0ea-16d4-468c-b2d5-033437f1a07b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2079025759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2079025759
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3783998163
Short name T137
Test name
Test status
Simulation time 9584802352 ps
CPU time 269.91 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:11:18 PM PDT 24
Peak memory 265272 kb
Host smart-e62fc934-b727-4eb2-9e57-1312a5c57a54
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783998163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3783998163
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.386987817
Short name T707
Test name
Test status
Simulation time 38557521 ps
CPU time 5.19 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:05:28 PM PDT 24
Peak memory 248016 kb
Host smart-fa4d5905-845e-4601-ab47-a92c8cb4d62e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386987817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.386987817
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2860900538
Short name T157
Test name
Test status
Simulation time 13581825 ps
CPU time 1.58 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:01 PM PDT 24
Peak memory 236664 kb
Host smart-3174f453-bc41-41d7-a876-406f300e4946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2860900538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2860900538
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4093685454
Short name T338
Test name
Test status
Simulation time 22801899 ps
CPU time 1.58 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 237616 kb
Host smart-0c59bb2e-c67c-4c1a-bb99-cc4b49ac497e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093685454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4093685454
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.720716374
Short name T778
Test name
Test status
Simulation time 6370427 ps
CPU time 1.46 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 237652 kb
Host smart-5b96a946-3110-4161-bab3-0186e156c410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=720716374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.720716374
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.97246716
Short name T768
Test name
Test status
Simulation time 21779564 ps
CPU time 1.45 seconds
Started Jun 26 07:05:59 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 236664 kb
Host smart-0df02bc7-5014-4c62-b2cf-5e5d0b78f574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=97246716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.97246716
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3128246055
Short name T773
Test name
Test status
Simulation time 28475624 ps
CPU time 2.1 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:07 PM PDT 24
Peak memory 236660 kb
Host smart-874400d2-045c-41b3-8e4d-48fec4f53d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3128246055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3128246055
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3683881850
Short name T715
Test name
Test status
Simulation time 9683682 ps
CPU time 1.52 seconds
Started Jun 26 07:05:55 PM PDT 24
Finished Jun 26 07:05:58 PM PDT 24
Peak memory 237652 kb
Host smart-13145ff2-156c-484f-87e0-b63206d1df0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3683881850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3683881850
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1425241099
Short name T776
Test name
Test status
Simulation time 8054476 ps
CPU time 1.57 seconds
Started Jun 26 07:05:59 PM PDT 24
Finished Jun 26 07:06:05 PM PDT 24
Peak memory 235664 kb
Host smart-9680ff83-a72a-4e88-b459-606f4e7bf51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1425241099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1425241099
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1765372283
Short name T710
Test name
Test status
Simulation time 9996618 ps
CPU time 1.27 seconds
Started Jun 26 07:05:59 PM PDT 24
Finished Jun 26 07:06:05 PM PDT 24
Peak memory 237608 kb
Host smart-cb15168e-1081-456a-a76a-9f543216d545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1765372283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1765372283
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2366973303
Short name T734
Test name
Test status
Simulation time 8157257 ps
CPU time 1.34 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 237620 kb
Host smart-3da076b3-8eb1-492b-996b-1927afc17050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2366973303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2366973303
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1543958476
Short name T758
Test name
Test status
Simulation time 3715972406 ps
CPU time 133.46 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:07:37 PM PDT 24
Peak memory 240616 kb
Host smart-1f9157d0-f2e5-45de-b552-f4d4568e7210
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1543958476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1543958476
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1361365438
Short name T809
Test name
Test status
Simulation time 1638142421 ps
CPU time 117.25 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:07:20 PM PDT 24
Peak memory 240552 kb
Host smart-e918dc02-801a-4651-befb-e0f05ddd3055
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1361365438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1361365438
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2664047938
Short name T740
Test name
Test status
Simulation time 50722280 ps
CPU time 5.25 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:05:28 PM PDT 24
Peak memory 248752 kb
Host smart-ab76f561-a631-46de-b56d-988e99690f6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2664047938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2664047938
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1579349652
Short name T821
Test name
Test status
Simulation time 63362125 ps
CPU time 8.69 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:06:56 PM PDT 24
Peak memory 253108 kb
Host smart-3a15068d-3196-4ca3-bfc4-ded2462225c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579349652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1579349652
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2444179603
Short name T727
Test name
Test status
Simulation time 63012644 ps
CPU time 3.51 seconds
Started Jun 26 07:05:18 PM PDT 24
Finished Jun 26 07:05:23 PM PDT 24
Peak memory 240544 kb
Host smart-beda5aa0-ba2e-4245-82d8-8bdd0a9fd505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2444179603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2444179603
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2651490387
Short name T815
Test name
Test status
Simulation time 15789176 ps
CPU time 1.59 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:05:23 PM PDT 24
Peak memory 237584 kb
Host smart-f09be705-fce8-401c-a336-04448f544f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2651490387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2651490387
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1381823529
Short name T770
Test name
Test status
Simulation time 459218736 ps
CPU time 14.06 seconds
Started Jun 26 07:05:21 PM PDT 24
Finished Jun 26 07:05:37 PM PDT 24
Peak memory 239668 kb
Host smart-369e5833-2dd8-401a-96df-1e7fddffbeeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381823529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1381823529
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2097935754
Short name T146
Test name
Test status
Simulation time 2638453187 ps
CPU time 301.21 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:11:49 PM PDT 24
Peak memory 265240 kb
Host smart-6c944a6a-c643-4176-8b58-86d13fcf6508
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097935754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2097935754
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2035629492
Short name T723
Test name
Test status
Simulation time 905143919 ps
CPU time 13.85 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:07:01 PM PDT 24
Peak memory 248024 kb
Host smart-b9ebd764-9989-49d6-beee-cefa42593342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2035629492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2035629492
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3556904507
Short name T721
Test name
Test status
Simulation time 8430225 ps
CPU time 1.56 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:01 PM PDT 24
Peak memory 236704 kb
Host smart-35a414ad-b8d3-4254-85d1-699c480bbb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3556904507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3556904507
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3010048274
Short name T342
Test name
Test status
Simulation time 13933391 ps
CPU time 1.63 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 236708 kb
Host smart-cfadda44-f161-40a2-a1cd-605e6e297a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010048274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3010048274
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1631714082
Short name T749
Test name
Test status
Simulation time 9994494 ps
CPU time 1.29 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 235704 kb
Host smart-a5544642-88f1-4b25-9fdc-9c39e4636216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1631714082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1631714082
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4118945458
Short name T748
Test name
Test status
Simulation time 12348758 ps
CPU time 1.41 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 237652 kb
Host smart-355b0630-512d-4191-8224-c13489c64be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4118945458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4118945458
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2744193809
Short name T714
Test name
Test status
Simulation time 11251807 ps
CPU time 1.28 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 237604 kb
Host smart-a5c7f1d4-41a0-4eee-9e3c-616a469759c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744193809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2744193809
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3178623347
Short name T767
Test name
Test status
Simulation time 10491652 ps
CPU time 1.36 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:06:33 PM PDT 24
Peak memory 237652 kb
Host smart-bbfd5ce0-7056-42f3-8c0a-8ca7336c7ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3178623347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3178623347
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2937385645
Short name T743
Test name
Test status
Simulation time 41362431 ps
CPU time 1.39 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 237480 kb
Host smart-05b2e689-057f-4893-b512-effe8ed97bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2937385645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2937385645
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1484467530
Short name T804
Test name
Test status
Simulation time 8512907 ps
CPU time 1.55 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:05 PM PDT 24
Peak memory 237652 kb
Host smart-b21862ba-a669-4e67-9ca5-7bbef7216ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1484467530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1484467530
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2290866929
Short name T787
Test name
Test status
Simulation time 14047181 ps
CPU time 1.47 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 237620 kb
Host smart-30247f4b-2162-4620-a29d-7bc1c6d46c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290866929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2290866929
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3912124944
Short name T764
Test name
Test status
Simulation time 14820859 ps
CPU time 1.32 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 235688 kb
Host smart-b372a2cb-18a5-43d5-8109-8875023c049f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912124944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3912124944
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.340922618
Short name T744
Test name
Test status
Simulation time 1186335237 ps
CPU time 78.42 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:06:51 PM PDT 24
Peak memory 240576 kb
Host smart-346a4d65-4cfd-4301-b3ef-4eeb6679927a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=340922618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.340922618
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.243979632
Short name T344
Test name
Test status
Simulation time 11910929536 ps
CPU time 213.13 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:09:08 PM PDT 24
Peak memory 237672 kb
Host smart-46565240-936f-4c41-9aee-39ee1c34dbf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=243979632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.243979632
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3035909156
Short name T229
Test name
Test status
Simulation time 246463378 ps
CPU time 5.65 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:39 PM PDT 24
Peak memory 240596 kb
Host smart-c4ab01a3-0de7-45f5-aee4-95ed1ec92dd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3035909156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3035909156
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.465435215
Short name T824
Test name
Test status
Simulation time 134613217 ps
CPU time 9.34 seconds
Started Jun 26 07:05:30 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 240600 kb
Host smart-2f16e3f5-3171-43f2-a160-c3294dc59dd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465435215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.465435215
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2006416692
Short name T814
Test name
Test status
Simulation time 144745231 ps
CPU time 5.82 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 237600 kb
Host smart-2d0c6275-3282-4e8c-a623-2dcb2ebe6efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2006416692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2006416692
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.419836961
Short name T791
Test name
Test status
Simulation time 20567272 ps
CPU time 1.54 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:05:27 PM PDT 24
Peak memory 236764 kb
Host smart-6b082fc6-d3a8-47c9-9d80-96444dc40fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=419836961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.419836961
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2480737797
Short name T783
Test name
Test status
Simulation time 617614481 ps
CPU time 40.79 seconds
Started Jun 26 07:05:30 PM PDT 24
Finished Jun 26 07:06:12 PM PDT 24
Peak memory 244832 kb
Host smart-d466f03a-fadc-4bec-abb2-7a25c467a80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2480737797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2480737797
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3849671833
Short name T114
Test name
Test status
Simulation time 11830335819 ps
CPU time 140.48 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:07:45 PM PDT 24
Peak memory 265380 kb
Host smart-f3adecc6-3fab-4afb-94ed-d7a708b3d64b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3849671833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3849671833
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3593546072
Short name T124
Test name
Test status
Simulation time 8834904572 ps
CPU time 618.15 seconds
Started Jun 26 07:05:23 PM PDT 24
Finished Jun 26 07:15:43 PM PDT 24
Peak memory 265652 kb
Host smart-30f66be3-6376-40a5-bbca-a368138755d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593546072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3593546072
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2156659317
Short name T819
Test name
Test status
Simulation time 929605987 ps
CPU time 12.07 seconds
Started Jun 26 07:05:20 PM PDT 24
Finished Jun 26 07:05:34 PM PDT 24
Peak memory 252472 kb
Host smart-7a0a64ce-58f2-4257-83f0-c1ef1b68c178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2156659317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2156659317
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1674663091
Short name T813
Test name
Test status
Simulation time 22948599 ps
CPU time 1.52 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 236844 kb
Host smart-b2f59b64-ef6c-42eb-a67e-ce69bbeb942c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1674663091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1674663091
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1108437067
Short name T711
Test name
Test status
Simulation time 15427554 ps
CPU time 1.43 seconds
Started Jun 26 07:05:59 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 237640 kb
Host smart-506c76a9-fa9b-4fb2-940b-234c038f2647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108437067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1108437067
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.870658544
Short name T800
Test name
Test status
Simulation time 20217041 ps
CPU time 1.49 seconds
Started Jun 26 07:05:56 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 236708 kb
Host smart-9a991ebf-005e-4997-9272-8b2058da6faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=870658544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.870658544
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1026482308
Short name T343
Test name
Test status
Simulation time 15039354 ps
CPU time 1.5 seconds
Started Jun 26 07:05:59 PM PDT 24
Finished Jun 26 07:06:05 PM PDT 24
Peak memory 235656 kb
Host smart-dd11d450-fccf-46c7-994f-7a6cc4ebc055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026482308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1026482308
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.370860503
Short name T158
Test name
Test status
Simulation time 15309508 ps
CPU time 1.38 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 235760 kb
Host smart-b49d417d-9fd0-472b-a869-925f59156aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=370860503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.370860503
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2192063933
Short name T340
Test name
Test status
Simulation time 23041355 ps
CPU time 1.38 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:06 PM PDT 24
Peak memory 237480 kb
Host smart-9193b6f9-120a-401d-9db5-bb60395fd46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2192063933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2192063933
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.739890496
Short name T760
Test name
Test status
Simulation time 7565930 ps
CPU time 1.56 seconds
Started Jun 26 07:05:58 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 237628 kb
Host smart-d02ddae7-a686-49fa-a441-3b2562c198b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=739890496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.739890496
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3099760359
Short name T709
Test name
Test status
Simulation time 6758341 ps
CPU time 1.49 seconds
Started Jun 26 07:05:57 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 237652 kb
Host smart-5cd0ddea-0b60-47c0-82ad-54f5c6c7b6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3099760359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3099760359
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2768176589
Short name T823
Test name
Test status
Simulation time 6259463 ps
CPU time 1.5 seconds
Started Jun 26 07:06:00 PM PDT 24
Finished Jun 26 07:06:05 PM PDT 24
Peak memory 237748 kb
Host smart-8aabab29-349c-4469-aaab-89b46ffcaec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2768176589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2768176589
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.406483051
Short name T816
Test name
Test status
Simulation time 152316216 ps
CPU time 13.34 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:47 PM PDT 24
Peak memory 244472 kb
Host smart-1ade8d63-c255-4caf-8ec3-cfb9a644d418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406483051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.406483051
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1294594898
Short name T766
Test name
Test status
Simulation time 22169987 ps
CPU time 3.54 seconds
Started Jun 26 07:05:35 PM PDT 24
Finished Jun 26 07:05:40 PM PDT 24
Peak memory 237592 kb
Host smart-f05ef6a5-0767-41ec-a917-85eb717c6f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1294594898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1294594898
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1272626083
Short name T339
Test name
Test status
Simulation time 13453734 ps
CPU time 1.79 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:05:35 PM PDT 24
Peak memory 236708 kb
Host smart-519831b7-27b2-430b-820f-bfe7a2d13c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1272626083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1272626083
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2490767225
Short name T172
Test name
Test status
Simulation time 2148704061 ps
CPU time 44.15 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:06:19 PM PDT 24
Peak memory 248820 kb
Host smart-9161e02f-b2d5-4fc3-9e48-b190d0691672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2490767225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2490767225
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3942714601
Short name T142
Test name
Test status
Simulation time 1891337774 ps
CPU time 195.94 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:08:52 PM PDT 24
Peak memory 265400 kb
Host smart-3353bd89-b2d7-4053-bd83-b7043ae8e4e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3942714601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3942714601
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.747832306
Short name T139
Test name
Test status
Simulation time 27707487709 ps
CPU time 515.67 seconds
Started Jun 26 07:05:30 PM PDT 24
Finished Jun 26 07:14:07 PM PDT 24
Peak memory 268584 kb
Host smart-43c40cb3-c342-43a2-a3ad-21ec5bd3fd6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747832306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.747832306
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.311769918
Short name T713
Test name
Test status
Simulation time 1206764383 ps
CPU time 20.88 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:05:56 PM PDT 24
Peak memory 248800 kb
Host smart-352be466-8673-4614-b7b7-02e06c25bec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311769918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.311769918
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2980654734
Short name T719
Test name
Test status
Simulation time 345305000 ps
CPU time 9.54 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:05:43 PM PDT 24
Peak memory 256964 kb
Host smart-c5bb6c37-e4f8-4150-bd96-ffaf55bb00bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980654734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2980654734
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1647327154
Short name T347
Test name
Test status
Simulation time 94843894 ps
CPU time 4.64 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:05:39 PM PDT 24
Peak memory 237636 kb
Host smart-8f531e1b-1253-4eae-a3d6-1c2b92d0f21b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1647327154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1647327154
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3688754489
Short name T156
Test name
Test status
Simulation time 10581227 ps
CPU time 1.31 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:05:34 PM PDT 24
Peak memory 237644 kb
Host smart-4edeb05d-76bb-4425-a0c7-434818ae4d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3688754489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3688754489
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4228443080
Short name T720
Test name
Test status
Simulation time 481364242 ps
CPU time 28.28 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:06:03 PM PDT 24
Peak memory 240520 kb
Host smart-22cdc616-7614-428f-bf77-d2678423fc72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4228443080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4228443080
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4092000190
Short name T148
Test name
Test status
Simulation time 11971289343 ps
CPU time 519.8 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:14:14 PM PDT 24
Peak memory 265468 kb
Host smart-be4beaed-7347-432a-bda4-0252a115a817
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092000190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4092000190
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2598450791
Short name T704
Test name
Test status
Simulation time 352636349 ps
CPU time 11.58 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:05:47 PM PDT 24
Peak memory 247492 kb
Host smart-9448bb27-9a0f-44aa-a7db-3a05b28fb511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2598450791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2598450791
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.343576523
Short name T772
Test name
Test status
Simulation time 130895882 ps
CPU time 6.31 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:05:42 PM PDT 24
Peak memory 237636 kb
Host smart-78889c3b-fefa-44a3-927f-be0bbf177462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=343576523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.343576523
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4198664231
Short name T802
Test name
Test status
Simulation time 52764434 ps
CPU time 5.09 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:05:40 PM PDT 24
Peak memory 240624 kb
Host smart-da80be01-c432-4595-ada1-1bd8192beeca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198664231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.4198664231
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2814803141
Short name T798
Test name
Test status
Simulation time 22903149 ps
CPU time 3.73 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:05:39 PM PDT 24
Peak memory 237448 kb
Host smart-eafdfec8-3bf6-4601-9551-a5626df712c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2814803141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2814803141
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3578325699
Short name T759
Test name
Test status
Simulation time 8128026 ps
CPU time 1.47 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:36 PM PDT 24
Peak memory 237616 kb
Host smart-7582c9bd-bdb8-42eb-b905-2758d235bc6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3578325699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3578325699
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2756790343
Short name T731
Test name
Test status
Simulation time 164216718 ps
CPU time 11.44 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:05:47 PM PDT 24
Peak memory 244812 kb
Host smart-b8c8ec1a-2f30-45c0-bc3e-6a45dc5c849b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2756790343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2756790343
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4289465525
Short name T123
Test name
Test status
Simulation time 6848592935 ps
CPU time 225.26 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:09:18 PM PDT 24
Peak memory 265468 kb
Host smart-61afaf37-bffc-4235-a147-be770aba10e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4289465525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4289465525
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1352760989
Short name T730
Test name
Test status
Simulation time 332073914 ps
CPU time 7.43 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:42 PM PDT 24
Peak memory 248784 kb
Host smart-0f41b71f-be4b-4e15-865b-0ed1d1befba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1352760989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1352760989
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4140580861
Short name T739
Test name
Test status
Simulation time 221602590 ps
CPU time 7.67 seconds
Started Jun 26 07:05:32 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 256484 kb
Host smart-4c4cfdb3-0a9f-4dcb-aeb7-b97369a5206f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140580861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4140580861
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2257281414
Short name T177
Test name
Test status
Simulation time 62331662 ps
CPU time 5.99 seconds
Started Jun 26 07:05:33 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 237588 kb
Host smart-c589641c-ed47-4ec9-aff4-ceff0b59849f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2257281414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2257281414
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4058069203
Short name T341
Test name
Test status
Simulation time 10889308 ps
CPU time 1.3 seconds
Started Jun 26 07:05:34 PM PDT 24
Finished Jun 26 07:05:37 PM PDT 24
Peak memory 235640 kb
Host smart-b5f6997d-3bd2-4384-a382-9aebccfc3fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4058069203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.4058069203
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1442622645
Short name T722
Test name
Test status
Simulation time 259277300 ps
CPU time 17.85 seconds
Started Jun 26 07:05:30 PM PDT 24
Finished Jun 26 07:05:49 PM PDT 24
Peak memory 245768 kb
Host smart-9b993edb-7fe5-4d3b-9daf-4328e37abd73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1442622645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1442622645
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2653717980
Short name T150
Test name
Test status
Simulation time 2765820575 ps
CPU time 206.6 seconds
Started Jun 26 07:05:29 PM PDT 24
Finished Jun 26 07:08:57 PM PDT 24
Peak memory 268264 kb
Host smart-cd1b2e6e-77e6-4fe3-80f2-0a7d249d8451
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2653717980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2653717980
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3082349095
Short name T803
Test name
Test status
Simulation time 453984950 ps
CPU time 25.04 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:05:58 PM PDT 24
Peak memory 248812 kb
Host smart-95e47be5-41b2-419e-961e-e8fad9c795d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3082349095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3082349095
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3535077740
Short name T786
Test name
Test status
Simulation time 24089690 ps
CPU time 2.66 seconds
Started Jun 26 07:05:31 PM PDT 24
Finished Jun 26 07:05:35 PM PDT 24
Peak memory 236708 kb
Host smart-1a80420b-b94c-49b6-b01f-07c3404fa23b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3535077740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3535077740
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3865537588
Short name T757
Test name
Test status
Simulation time 209967963 ps
CPU time 6.07 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:05:51 PM PDT 24
Peak memory 256992 kb
Host smart-ecc5de3c-7c21-4f18-9c1c-daa3355b6df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865537588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3865537588
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.24502406
Short name T173
Test name
Test status
Simulation time 59935863 ps
CPU time 5.38 seconds
Started Jun 26 07:05:48 PM PDT 24
Finished Jun 26 07:05:56 PM PDT 24
Peak memory 240588 kb
Host smart-d36f0197-ed18-45a5-abb1-40128365bc8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=24502406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.24502406
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.120382708
Short name T219
Test name
Test status
Simulation time 10667053 ps
CPU time 1.61 seconds
Started Jun 26 07:05:43 PM PDT 24
Finished Jun 26 07:05:46 PM PDT 24
Peak memory 237636 kb
Host smart-6ab7f1d5-4139-4cca-9153-04eef608ffd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=120382708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.120382708
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2963845842
Short name T178
Test name
Test status
Simulation time 1750886921 ps
CPU time 48.48 seconds
Started Jun 26 07:05:46 PM PDT 24
Finished Jun 26 07:06:38 PM PDT 24
Peak memory 245848 kb
Host smart-096c5a9f-8dd4-426f-bd11-c0e804141b3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963845842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2963845842
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2581477811
Short name T147
Test name
Test status
Simulation time 4207228752 ps
CPU time 178.41 seconds
Started Jun 26 07:05:42 PM PDT 24
Finished Jun 26 07:08:42 PM PDT 24
Peak memory 265468 kb
Host smart-41ed993e-e914-4e32-b599-914ad35669ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581477811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2581477811
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4143038102
Short name T129
Test name
Test status
Simulation time 47933852966 ps
CPU time 1013.88 seconds
Started Jun 26 07:05:48 PM PDT 24
Finished Jun 26 07:22:45 PM PDT 24
Peak memory 265580 kb
Host smart-8592a001-4669-47da-8a6a-84f2e4aec409
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143038102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4143038102
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3162285471
Short name T703
Test name
Test status
Simulation time 268230952 ps
CPU time 16.3 seconds
Started Jun 26 07:05:44 PM PDT 24
Finished Jun 26 07:06:04 PM PDT 24
Peak memory 254244 kb
Host smart-771ab825-81f0-44ea-bc4d-0e66e5b1b90a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3162285471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3162285471
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1578072126
Short name T500
Test name
Test status
Simulation time 40524963525 ps
CPU time 1187 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:26:00 PM PDT 24
Peak memory 287792 kb
Host smart-9b7ae616-e027-4368-8737-9031749b3f47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578072126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1578072126
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1653978152
Short name T418
Test name
Test status
Simulation time 175517585 ps
CPU time 10.67 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:25 PM PDT 24
Peak memory 249272 kb
Host smart-cc554415-424a-444e-93d6-fbdec928b59a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1653978152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1653978152
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1711792271
Short name T497
Test name
Test status
Simulation time 3929642436 ps
CPU time 110.37 seconds
Started Jun 26 07:06:23 PM PDT 24
Finished Jun 26 07:08:15 PM PDT 24
Peak memory 257032 kb
Host smart-40771631-dffe-416d-bcd3-c09f125e0ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17117
92271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1711792271
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.720547880
Short name T415
Test name
Test status
Simulation time 319749196 ps
CPU time 37.29 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:06:56 PM PDT 24
Peak memory 255976 kb
Host smart-702696cc-92c1-4c64-99f1-3a267cf34896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72054
7880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.720547880
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1375554730
Short name T582
Test name
Test status
Simulation time 52534206101 ps
CPU time 1300.14 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:27:53 PM PDT 24
Peak memory 290256 kb
Host smart-cee44f30-75cf-4e83-9120-50b91c209edc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375554730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1375554730
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3021610600
Short name T263
Test name
Test status
Simulation time 312522957 ps
CPU time 33.13 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:06:52 PM PDT 24
Peak memory 249264 kb
Host smart-e8dacf0c-f208-4fe0-988a-7ec27777cc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
10600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3021610600
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3211249444
Short name T74
Test name
Test status
Simulation time 1291242554 ps
CPU time 33.39 seconds
Started Jun 26 07:06:07 PM PDT 24
Finished Jun 26 07:06:41 PM PDT 24
Peak memory 249024 kb
Host smart-43de98fc-072d-413c-b5d3-9908f888484b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32112
49444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3211249444
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3158954574
Short name T27
Test name
Test status
Simulation time 933424198 ps
CPU time 25.79 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:06:43 PM PDT 24
Peak memory 274964 kb
Host smart-f6d51be4-4868-4f33-8c13-f143ce35f8ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3158954574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3158954574
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1298107024
Short name T392
Test name
Test status
Simulation time 1593055848 ps
CPU time 29.44 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:44 PM PDT 24
Peak memory 248552 kb
Host smart-f2c4df97-a659-4d35-ac24-30d52664ddd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
07024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1298107024
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.187684675
Short name T522
Test name
Test status
Simulation time 2912304497 ps
CPU time 30.58 seconds
Started Jun 26 07:06:10 PM PDT 24
Finished Jun 26 07:06:42 PM PDT 24
Peak memory 249888 kb
Host smart-d46fe443-3908-43c9-b96e-cf77de8ef984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
4675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.187684675
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4287629632
Short name T37
Test name
Test status
Simulation time 26898742197 ps
CPU time 233.48 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:10:12 PM PDT 24
Peak memory 257568 kb
Host smart-4fb86481-4313-4740-b484-7b63fe258551
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287629632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4287629632
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4047642362
Short name T589
Test name
Test status
Simulation time 350105666970 ps
CPU time 2761.43 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:52:15 PM PDT 24
Peak memory 287468 kb
Host smart-175f3dea-d85a-421c-9a98-cd98d42e21de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047642362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4047642362
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1229051785
Short name T541
Test name
Test status
Simulation time 478048520 ps
CPU time 21.74 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:06:37 PM PDT 24
Peak memory 249324 kb
Host smart-a64a5308-280f-494c-bb36-90ef3b6a6a1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1229051785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1229051785
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.317353316
Short name T398
Test name
Test status
Simulation time 1631460602 ps
CPU time 122.34 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:08:20 PM PDT 24
Peak memory 256876 kb
Host smart-5be57902-b2b8-4be1-8049-628e82aae87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
3316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.317353316
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2526710372
Short name T555
Test name
Test status
Simulation time 3869390654 ps
CPU time 43.97 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:07:02 PM PDT 24
Peak memory 256652 kb
Host smart-90b811eb-3226-41d2-98ab-2191fb49b6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25267
10372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2526710372
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.719613579
Short name T560
Test name
Test status
Simulation time 196705654019 ps
CPU time 1321.46 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:28:16 PM PDT 24
Peak memory 282240 kb
Host smart-54b40697-5464-443e-89b8-9396a3e8d56d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719613579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.719613579
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2430668240
Short name T321
Test name
Test status
Simulation time 90442717824 ps
CPU time 500.53 seconds
Started Jun 26 07:06:24 PM PDT 24
Finished Jun 26 07:14:45 PM PDT 24
Peak memory 249372 kb
Host smart-cb11bb24-e3b9-4e9d-a014-da60513de8d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430668240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2430668240
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1180487689
Short name T383
Test name
Test status
Simulation time 165593689 ps
CPU time 10.51 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:06:26 PM PDT 24
Peak memory 255628 kb
Host smart-e4473cd1-473e-4b47-8a05-b76e6989ff60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
87689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1180487689
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.402266229
Short name T603
Test name
Test status
Simulation time 3215474602 ps
CPU time 45.81 seconds
Started Jun 26 07:06:21 PM PDT 24
Finished Jun 26 07:07:08 PM PDT 24
Peak memory 257116 kb
Host smart-fac38605-bc1f-4c83-aea0-9976a743f5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
6229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.402266229
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2411032066
Short name T44
Test name
Test status
Simulation time 513203302 ps
CPU time 17.88 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:06:31 PM PDT 24
Peak memory 249232 kb
Host smart-fbefde6a-7710-4b15-8071-44f61830f3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24110
32066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2411032066
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1767790377
Short name T427
Test name
Test status
Simulation time 1511348190 ps
CPU time 47.22 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:07:03 PM PDT 24
Peak memory 249200 kb
Host smart-105c3310-951a-4c72-819c-bf9599845b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17677
90377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1767790377
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.995779744
Short name T248
Test name
Test status
Simulation time 15857937447 ps
CPU time 185.32 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:09:19 PM PDT 24
Peak memory 253756 kb
Host smart-84dcf48d-8d8a-4fba-84b1-36d06578c82b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995779744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.995779744
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3827362736
Short name T109
Test name
Test status
Simulation time 83008771085 ps
CPU time 5127.04 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 08:31:44 PM PDT 24
Peak memory 322540 kb
Host smart-6b23c878-148f-4191-ae74-03ce3b840669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827362736 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3827362736
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.54254763
Short name T564
Test name
Test status
Simulation time 29464464339 ps
CPU time 2015.94 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:40:44 PM PDT 24
Peak memory 290092 kb
Host smart-c71a223f-672a-4fb0-99e9-18452850a1e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54254763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.54254763
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3117306756
Short name T387
Test name
Test status
Simulation time 166343026 ps
CPU time 11.23 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:18 PM PDT 24
Peak memory 249204 kb
Host smart-86286adf-2996-4648-9cc7-953524bec9e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3117306756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3117306756
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2071265664
Short name T573
Test name
Test status
Simulation time 3542866953 ps
CPU time 236.32 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:10:58 PM PDT 24
Peak memory 252472 kb
Host smart-54181b93-0b1b-40c2-a264-4d2c3c326f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20712
65664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2071265664
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3986761773
Short name T16
Test name
Test status
Simulation time 5770232143 ps
CPU time 73.47 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:08:18 PM PDT 24
Peak memory 257156 kb
Host smart-b2b084f7-9902-4b55-b977-90148c0c40da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
61773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3986761773
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4109652611
Short name T656
Test name
Test status
Simulation time 49407997506 ps
CPU time 850.29 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:21:16 PM PDT 24
Peak memory 273840 kb
Host smart-35ea8bbb-b2b6-4df3-a570-be371090a5ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109652611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4109652611
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1050709999
Short name T309
Test name
Test status
Simulation time 8043821492 ps
CPU time 176.87 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:10:02 PM PDT 24
Peak memory 249472 kb
Host smart-9059727a-ebb4-45d9-8375-0eb40bce64e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050709999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1050709999
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.903971943
Short name T683
Test name
Test status
Simulation time 99224737 ps
CPU time 11.85 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:18 PM PDT 24
Peak memory 256380 kb
Host smart-8315a7a9-2002-456f-97d8-860fe2d755bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90397
1943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.903971943
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2795474917
Short name T101
Test name
Test status
Simulation time 384947292 ps
CPU time 44.1 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:07:48 PM PDT 24
Peak memory 249120 kb
Host smart-f69ef479-47ad-4fe5-801e-b94bccbf7bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27954
74917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2795474917
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.877947114
Short name T433
Test name
Test status
Simulation time 234192207 ps
CPU time 22.24 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:07:26 PM PDT 24
Peak memory 250040 kb
Host smart-d36152a4-f338-48c3-bceb-b4e9df68f84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87794
7114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.877947114
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3129620948
Short name T592
Test name
Test status
Simulation time 863098420 ps
CPU time 51.28 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:07:56 PM PDT 24
Peak memory 257432 kb
Host smart-52456bd8-b566-47d6-a1f4-bf38121f4d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
20948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3129620948
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2547476025
Short name T200
Test name
Test status
Simulation time 56532369 ps
CPU time 2.82 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:07:07 PM PDT 24
Peak memory 249544 kb
Host smart-754c9fb4-3af1-4e90-82e3-1214b7e0a1fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2547476025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2547476025
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3929901975
Short name T669
Test name
Test status
Simulation time 118698697805 ps
CPU time 2120.73 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:42:25 PM PDT 24
Peak memory 284820 kb
Host smart-5a0fbeec-4d98-4a10-9368-ced2ae05eaa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929901975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3929901975
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1545512925
Short name T390
Test name
Test status
Simulation time 716010904 ps
CPU time 18.29 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:07:23 PM PDT 24
Peak memory 249248 kb
Host smart-3e3ee210-2754-44a1-8e9c-67906ca1b62e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1545512925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1545512925
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.239340087
Short name T464
Test name
Test status
Simulation time 1265416619 ps
CPU time 27.55 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:07:32 PM PDT 24
Peak memory 256640 kb
Host smart-c190aa22-4142-4c74-ba49-71e3dbc98b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23934
0087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.239340087
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2593967620
Short name T352
Test name
Test status
Simulation time 784627559 ps
CPU time 57.3 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:08:02 PM PDT 24
Peak memory 248868 kb
Host smart-675a0259-640e-403d-a2f7-8816a41eaa25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
67620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2593967620
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.912071452
Short name T325
Test name
Test status
Simulation time 15610170569 ps
CPU time 1443.41 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:31:07 PM PDT 24
Peak memory 286996 kb
Host smart-5addbe63-3b99-4d84-8144-f64620ea9e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912071452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.912071452
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1926093679
Short name T210
Test name
Test status
Simulation time 22878363975 ps
CPU time 1154.77 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:26:20 PM PDT 24
Peak memory 284584 kb
Host smart-eae65f84-c4fc-4b08-b01f-9bc5148492ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926093679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1926093679
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3082392747
Short name T563
Test name
Test status
Simulation time 3597958410 ps
CPU time 76.89 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:08:20 PM PDT 24
Peak memory 249364 kb
Host smart-65e67fcd-05e6-4d3c-90f4-3d4d435c03fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082392747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3082392747
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3741335874
Short name T385
Test name
Test status
Simulation time 124906838 ps
CPU time 7.53 seconds
Started Jun 26 07:07:03 PM PDT 24
Finished Jun 26 07:07:12 PM PDT 24
Peak memory 249260 kb
Host smart-b27164c5-e07c-47b9-88a5-4677900f60c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37413
35874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3741335874
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2709805548
Short name T436
Test name
Test status
Simulation time 265980126 ps
CPU time 26.18 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:07:32 PM PDT 24
Peak memory 256660 kb
Host smart-974910eb-fe74-42c5-9cac-ab4031398538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27098
05548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2709805548
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1679979605
Short name T5
Test name
Test status
Simulation time 372855234 ps
CPU time 25.58 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:33 PM PDT 24
Peak memory 256276 kb
Host smart-6dc7a38d-c26f-4d51-939b-a77b362ddf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
79605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1679979605
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1685985188
Short name T477
Test name
Test status
Simulation time 497322739 ps
CPU time 32.33 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:07:36 PM PDT 24
Peak memory 257472 kb
Host smart-dd19d4bb-9314-42d0-ba17-4e7589ddbb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16859
85188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1685985188
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3209832624
Short name T639
Test name
Test status
Simulation time 355664311 ps
CPU time 15.66 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:07:18 PM PDT 24
Peak memory 254676 kb
Host smart-eb98a2b6-e5e9-4d32-b113-77b2e2c19d30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209832624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3209832624
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1211464577
Short name T202
Test name
Test status
Simulation time 122506666 ps
CPU time 2.42 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:07:11 PM PDT 24
Peak memory 249640 kb
Host smart-f42bbd9a-49b1-4695-a7da-1416aab4d923
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1211464577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1211464577
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2926987825
Short name T534
Test name
Test status
Simulation time 68782335337 ps
CPU time 1186.2 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:26:50 PM PDT 24
Peak memory 281680 kb
Host smart-0ad832fd-615f-4726-a3fc-a49848d3a758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926987825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2926987825
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3224874674
Short name T213
Test name
Test status
Simulation time 839002579 ps
CPU time 11.53 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:20 PM PDT 24
Peak memory 249416 kb
Host smart-5419b47c-080c-4aa5-a020-18e634a11551
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3224874674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3224874674
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1117895012
Short name T461
Test name
Test status
Simulation time 3951612418 ps
CPU time 293.33 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:12:01 PM PDT 24
Peak memory 257556 kb
Host smart-3624ce3d-8f5b-46d9-9f07-0a0583338d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
95012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1117895012
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3063880837
Short name T429
Test name
Test status
Simulation time 2498733029 ps
CPU time 41.44 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:49 PM PDT 24
Peak memory 250036 kb
Host smart-30f12561-7b02-40a9-92a9-8333b6bccdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
80837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3063880837
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3011179547
Short name T60
Test name
Test status
Simulation time 8641429631 ps
CPU time 1022.25 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:24:09 PM PDT 24
Peak memory 273920 kb
Host smart-97b01856-c1cd-4bd7-a566-58a7ab5237b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011179547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3011179547
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1003031922
Short name T590
Test name
Test status
Simulation time 11746096712 ps
CPU time 132.91 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:09:21 PM PDT 24
Peak memory 256008 kb
Host smart-0f0f9a41-2bae-4ec7-8db6-19605e620c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003031922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1003031922
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3262404568
Short name T404
Test name
Test status
Simulation time 1460133553 ps
CPU time 65.52 seconds
Started Jun 26 07:07:01 PM PDT 24
Finished Jun 26 07:08:09 PM PDT 24
Peak memory 256816 kb
Host smart-61f1dcce-b323-41b9-98c4-6b9ca3d35ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32624
04568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3262404568
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1062340864
Short name T441
Test name
Test status
Simulation time 3778295282 ps
CPU time 56.7 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:08:02 PM PDT 24
Peak memory 249424 kb
Host smart-9122eb37-e512-4ad2-a24c-0ad69b05316d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10623
40864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1062340864
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.817528658
Short name T540
Test name
Test status
Simulation time 2298814801 ps
CPU time 31.12 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:38 PM PDT 24
Peak memory 249784 kb
Host smart-039bc002-4462-4807-9320-1e836fc723ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81752
8658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.817528658
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2801962192
Short name T279
Test name
Test status
Simulation time 2318600644 ps
CPU time 33.64 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:41 PM PDT 24
Peak memory 257608 kb
Host smart-f41d20f4-1dc8-402b-94e7-acacf57e5eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
62192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2801962192
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3329173827
Short name T198
Test name
Test status
Simulation time 38683838 ps
CPU time 2.33 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:11 PM PDT 24
Peak memory 249580 kb
Host smart-d2a0cd57-9827-48f0-96eb-03c61159d344
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3329173827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3329173827
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.705830802
Short name T58
Test name
Test status
Simulation time 448740846150 ps
CPU time 2066.95 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:41:36 PM PDT 24
Peak memory 282044 kb
Host smart-fa148f9b-22f7-4346-b03c-d41acdbf6389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705830802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.705830802
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2697611353
Short name T215
Test name
Test status
Simulation time 6978619628 ps
CPU time 20.27 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:07:26 PM PDT 24
Peak memory 249376 kb
Host smart-14084296-0fb4-4080-8161-666a9a270d4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2697611353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2697611353
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1722374556
Short name T506
Test name
Test status
Simulation time 5665332189 ps
CPU time 97.73 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:08:46 PM PDT 24
Peak memory 257200 kb
Host smart-c87cebce-d4ae-4c72-807e-f407a91313d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223
74556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1722374556
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3005775264
Short name T35
Test name
Test status
Simulation time 631010835 ps
CPU time 20.23 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:28 PM PDT 24
Peak memory 257008 kb
Host smart-196f404f-3931-4e84-acb0-fbf749807502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
75264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3005775264
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3719626260
Short name T599
Test name
Test status
Simulation time 37206901268 ps
CPU time 2160.76 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:43:10 PM PDT 24
Peak memory 286276 kb
Host smart-096c8ee3-835d-440b-b770-cf377dde0ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719626260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3719626260
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2856667094
Short name T557
Test name
Test status
Simulation time 44557489041 ps
CPU time 2468.46 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:48:17 PM PDT 24
Peak memory 286996 kb
Host smart-a81f205b-3547-49c3-a7ce-201c8bac919d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856667094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2856667094
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1346697024
Short name T61
Test name
Test status
Simulation time 8708006799 ps
CPU time 368.01 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:13:16 PM PDT 24
Peak memory 249152 kb
Host smart-76f1c49e-22ab-443a-b2e6-a260808dc947
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346697024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1346697024
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3713567699
Short name T370
Test name
Test status
Simulation time 866605291 ps
CPU time 51.16 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:08:00 PM PDT 24
Peak memory 256352 kb
Host smart-e556cfa2-1e59-4ae3-bf04-4c5a3bba53b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37135
67699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3713567699
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1946861309
Short name T55
Test name
Test status
Simulation time 392329106 ps
CPU time 38.2 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:46 PM PDT 24
Peak memory 248644 kb
Host smart-66a91b38-1489-426f-9ac6-59bc10543050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19468
61309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1946861309
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3368451297
Short name T663
Test name
Test status
Simulation time 791557122 ps
CPU time 18.87 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:26 PM PDT 24
Peak memory 256456 kb
Host smart-c97cb168-caa2-400c-9152-97d1647ae889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33684
51297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3368451297
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1360983253
Short name T570
Test name
Test status
Simulation time 275835251 ps
CPU time 18.37 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:26 PM PDT 24
Peak memory 255704 kb
Host smart-ff3fe6bc-50f7-4062-8615-e1f7a002189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13609
83253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1360983253
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1877541366
Short name T597
Test name
Test status
Simulation time 28018873458 ps
CPU time 248.46 seconds
Started Jun 26 07:08:26 PM PDT 24
Finished Jun 26 07:12:36 PM PDT 24
Peak memory 257664 kb
Host smart-f1257822-fc64-46a4-b02b-52120d6b900e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877541366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1877541366
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1684455239
Short name T195
Test name
Test status
Simulation time 15373518 ps
CPU time 2.43 seconds
Started Jun 26 07:07:34 PM PDT 24
Finished Jun 26 07:07:37 PM PDT 24
Peak memory 249508 kb
Host smart-3229544b-513e-4a48-a6c8-1383733924dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1684455239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1684455239
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1061347703
Short name T57
Test name
Test status
Simulation time 56059116568 ps
CPU time 714.77 seconds
Started Jun 26 07:07:08 PM PDT 24
Finished Jun 26 07:19:04 PM PDT 24
Peak memory 273992 kb
Host smart-a2104193-ceab-4c39-936b-0ad33b39d6a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061347703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1061347703
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3389630399
Short name T568
Test name
Test status
Simulation time 2141796721 ps
CPU time 49.68 seconds
Started Jun 26 07:07:08 PM PDT 24
Finished Jun 26 07:07:59 PM PDT 24
Peak memory 249256 kb
Host smart-09b2006f-909d-4727-af2c-24a5e68eb41e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3389630399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3389630399
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3053826920
Short name T595
Test name
Test status
Simulation time 3957261392 ps
CPU time 70.01 seconds
Started Jun 26 07:07:09 PM PDT 24
Finished Jun 26 07:08:20 PM PDT 24
Peak memory 257072 kb
Host smart-48c65c4b-b163-46fb-bded-a9cd6edf0444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30538
26920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3053826920
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3584051838
Short name T187
Test name
Test status
Simulation time 405718984 ps
CPU time 24.49 seconds
Started Jun 26 07:07:06 PM PDT 24
Finished Jun 26 07:07:32 PM PDT 24
Peak memory 249292 kb
Host smart-77a2d447-362d-40e5-a03c-c73184e0048e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840
51838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3584051838
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2532632504
Short name T267
Test name
Test status
Simulation time 27089926781 ps
CPU time 604.66 seconds
Started Jun 26 07:07:07 PM PDT 24
Finished Jun 26 07:17:13 PM PDT 24
Peak memory 273836 kb
Host smart-bcfe11a3-7e53-4db1-b64e-d130344bfb10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532632504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2532632504
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1855338932
Short name T216
Test name
Test status
Simulation time 9444320700 ps
CPU time 396.07 seconds
Started Jun 26 07:07:10 PM PDT 24
Finished Jun 26 07:13:47 PM PDT 24
Peak memory 256432 kb
Host smart-509ced7b-53af-4243-a46b-7aeaf7c0ed5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855338932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1855338932
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.849623196
Short name T65
Test name
Test status
Simulation time 2157959150 ps
CPU time 60.01 seconds
Started Jun 26 07:07:11 PM PDT 24
Finished Jun 26 07:08:11 PM PDT 24
Peak memory 256532 kb
Host smart-cf6df32d-a8da-4a9f-819f-62dddad4c4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84962
3196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.849623196
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2659729418
Short name T695
Test name
Test status
Simulation time 666416785 ps
CPU time 44.42 seconds
Started Jun 26 07:07:11 PM PDT 24
Finished Jun 26 07:07:56 PM PDT 24
Peak memory 249240 kb
Host smart-fd38730d-e525-4309-a178-1e0367bb62ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26597
29418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2659729418
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.444046223
Short name T184
Test name
Test status
Simulation time 55944743 ps
CPU time 10.58 seconds
Started Jun 26 07:07:09 PM PDT 24
Finished Jun 26 07:07:20 PM PDT 24
Peak memory 248812 kb
Host smart-f42e5a59-01e9-42c1-a8b1-f48177718a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44404
6223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.444046223
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.526748987
Short name T593
Test name
Test status
Simulation time 1367324456 ps
CPU time 25.57 seconds
Started Jun 26 07:07:09 PM PDT 24
Finished Jun 26 07:07:36 PM PDT 24
Peak memory 257372 kb
Host smart-75f7117d-0abd-4d9d-b6e8-174a43ceb35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52674
8987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.526748987
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3804066655
Short name T30
Test name
Test status
Simulation time 39512672 ps
CPU time 2.53 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:07:33 PM PDT 24
Peak memory 249568 kb
Host smart-9973cda8-7f2a-4c90-aedb-ab23bb005ee8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3804066655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3804066655
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.791682372
Short name T232
Test name
Test status
Simulation time 30890119456 ps
CPU time 1705.63 seconds
Started Jun 26 07:07:27 PM PDT 24
Finished Jun 26 07:35:54 PM PDT 24
Peak memory 274176 kb
Host smart-22184b28-6a93-4e18-b0f8-c12b011ecd01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791682372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.791682372
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2380946399
Short name T696
Test name
Test status
Simulation time 591327831 ps
CPU time 9.52 seconds
Started Jun 26 07:07:32 PM PDT 24
Finished Jun 26 07:07:43 PM PDT 24
Peak memory 249268 kb
Host smart-46e529bb-d887-4119-9c13-5c61e1f63ab8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2380946399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2380946399
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4035453862
Short name T348
Test name
Test status
Simulation time 18316998370 ps
CPU time 111.45 seconds
Started Jun 26 07:07:33 PM PDT 24
Finished Jun 26 07:09:26 PM PDT 24
Peak memory 257032 kb
Host smart-7ada51e3-1aca-494a-9f14-67d1f7beaa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40354
53862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4035453862
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3822916844
Short name T449
Test name
Test status
Simulation time 164990767 ps
CPU time 3.97 seconds
Started Jun 26 07:07:31 PM PDT 24
Finished Jun 26 07:07:37 PM PDT 24
Peak memory 240368 kb
Host smart-a7bfbcf5-1490-4152-b459-8fcd9733dab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
16844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3822916844
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2731572704
Short name T633
Test name
Test status
Simulation time 20751562373 ps
CPU time 1376.21 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:30:26 PM PDT 24
Peak memory 273128 kb
Host smart-7fbbdab8-245b-48ee-8ec8-a477eb55babd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731572704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2731572704
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3966709912
Short name T264
Test name
Test status
Simulation time 10592663144 ps
CPU time 433.85 seconds
Started Jun 26 07:07:33 PM PDT 24
Finished Jun 26 07:14:48 PM PDT 24
Peak memory 255740 kb
Host smart-2b9d5783-f8cc-46f4-953d-4a3d146e1b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966709912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3966709912
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3914801769
Short name T211
Test name
Test status
Simulation time 560382151 ps
CPU time 23.79 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:07:56 PM PDT 24
Peak memory 257044 kb
Host smart-125c596a-2cf8-4602-8d52-1d28560ca183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
01769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3914801769
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.421084747
Short name T471
Test name
Test status
Simulation time 744485844 ps
CPU time 14.38 seconds
Started Jun 26 07:07:29 PM PDT 24
Finished Jun 26 07:07:46 PM PDT 24
Peak memory 248608 kb
Host smart-81cb9a90-54c0-4d60-9b2f-330f5ce33da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42108
4747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.421084747
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3952673260
Short name T626
Test name
Test status
Simulation time 313421320 ps
CPU time 34.85 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:08:05 PM PDT 24
Peak memory 249184 kb
Host smart-7869c35d-12e0-4d68-85f8-946518ad10f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
73260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3952673260
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3448793290
Short name T643
Test name
Test status
Simulation time 860135407 ps
CPU time 58.5 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:08:31 PM PDT 24
Peak memory 257444 kb
Host smart-87475ca8-f7b3-432b-ad6e-bfde45eec62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34487
93290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3448793290
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2711334618
Short name T176
Test name
Test status
Simulation time 198756603789 ps
CPU time 4262.54 seconds
Started Jun 26 07:07:29 PM PDT 24
Finished Jun 26 08:18:35 PM PDT 24
Peak memory 306596 kb
Host smart-6fd0e8ed-a890-483e-8610-435bfb2162fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711334618 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2711334618
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3626314469
Short name T226
Test name
Test status
Simulation time 15553152238 ps
CPU time 1296.66 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:29:07 PM PDT 24
Peak memory 290152 kb
Host smart-4c6fd920-031d-4dfe-870e-539552adb110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626314469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3626314469
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1938144868
Short name T685
Test name
Test status
Simulation time 1668474797 ps
CPU time 11.68 seconds
Started Jun 26 07:07:33 PM PDT 24
Finished Jun 26 07:07:46 PM PDT 24
Peak memory 249256 kb
Host smart-8fdbba83-c6d1-4e50-82b0-3a87acac1118
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1938144868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1938144868
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3951942131
Short name T635
Test name
Test status
Simulation time 7832918024 ps
CPU time 154.1 seconds
Started Jun 26 07:07:31 PM PDT 24
Finished Jun 26 07:10:07 PM PDT 24
Peak memory 257596 kb
Host smart-baeaf99f-0ca2-444c-95f9-6624eb66caf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
42131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3951942131
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.597949483
Short name T33
Test name
Test status
Simulation time 1231890556 ps
CPU time 21.53 seconds
Started Jun 26 07:07:29 PM PDT 24
Finished Jun 26 07:07:53 PM PDT 24
Peak memory 257048 kb
Host smart-49f5af48-428b-4e16-8021-0166648105b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59794
9483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.597949483
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3639911121
Short name T502
Test name
Test status
Simulation time 51429304745 ps
CPU time 1185.08 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:27:17 PM PDT 24
Peak memory 282256 kb
Host smart-54a52e4f-e839-4838-8be5-0cdbaff30e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639911121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3639911121
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1996468003
Short name T287
Test name
Test status
Simulation time 10513265782 ps
CPU time 416.82 seconds
Started Jun 26 07:07:33 PM PDT 24
Finished Jun 26 07:14:31 PM PDT 24
Peak memory 256180 kb
Host smart-fa46da32-25e4-4ffd-8b6c-1111fe402430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996468003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1996468003
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1792824505
Short name T666
Test name
Test status
Simulation time 780306559 ps
CPU time 46.92 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:08:18 PM PDT 24
Peak memory 256788 kb
Host smart-e8bc910d-6ad0-4a8c-a2ad-a3716558c217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928
24505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1792824505
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3337306686
Short name T527
Test name
Test status
Simulation time 902726986 ps
CPU time 18.62 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:07:48 PM PDT 24
Peak memory 255148 kb
Host smart-e3d09b1a-1b5d-4340-b5f6-ed1bf4383a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33373
06686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3337306686
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1606376767
Short name T243
Test name
Test status
Simulation time 3446435053 ps
CPU time 26.04 seconds
Started Jun 26 07:07:29 PM PDT 24
Finished Jun 26 07:07:58 PM PDT 24
Peak memory 257608 kb
Host smart-c4cd395b-327e-4a34-bea6-ca4d2fd6225c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16063
76767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1606376767
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2337476371
Short name T600
Test name
Test status
Simulation time 287515288 ps
CPU time 27.57 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:08:00 PM PDT 24
Peak memory 249304 kb
Host smart-2a482f7c-fe94-422d-a66d-578d50bcaa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
76371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2337476371
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.822796477
Short name T349
Test name
Test status
Simulation time 15076330459 ps
CPU time 219.12 seconds
Started Jun 26 07:07:27 PM PDT 24
Finished Jun 26 07:11:08 PM PDT 24
Peak memory 257540 kb
Host smart-3fb213d3-1ed9-4516-87d0-d9b4c43dafb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822796477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.822796477
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2013002375
Short name T197
Test name
Test status
Simulation time 23569716 ps
CPU time 2.98 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:08:15 PM PDT 24
Peak memory 249576 kb
Host smart-3e0bff48-ff87-48bf-baff-df87d1dfce4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2013002375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2013002375
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.746580019
Short name T87
Test name
Test status
Simulation time 40081043857 ps
CPU time 2265.08 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:45:54 PM PDT 24
Peak memory 287168 kb
Host smart-3ae95c0b-26c3-4b3a-84d5-ff1cc3b29eeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746580019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.746580019
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2938155939
Short name T672
Test name
Test status
Simulation time 92053298 ps
CPU time 6.73 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:08:12 PM PDT 24
Peak memory 249320 kb
Host smart-e77c2c65-a148-4c11-a4f5-46c72e863c19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2938155939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2938155939
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1814212334
Short name T646
Test name
Test status
Simulation time 720261236 ps
CPU time 61.16 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:08:32 PM PDT 24
Peak memory 257492 kb
Host smart-99d08cc6-5cd9-4483-8f1b-756705803096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
12334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1814212334
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1201503225
Short name T244
Test name
Test status
Simulation time 413637541 ps
CPU time 31.53 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:08:03 PM PDT 24
Peak memory 249216 kb
Host smart-ae91fcef-a92d-4b88-8008-7d197910b968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12015
03225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1201503225
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3068475845
Short name T307
Test name
Test status
Simulation time 16954457958 ps
CPU time 984.54 seconds
Started Jun 26 07:09:14 PM PDT 24
Finished Jun 26 07:25:40 PM PDT 24
Peak memory 273952 kb
Host smart-17c1c8d6-7b65-4798-809f-4d039a7bfe06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068475845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3068475845
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3152718763
Short name T355
Test name
Test status
Simulation time 41027330821 ps
CPU time 1456.85 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:32:25 PM PDT 24
Peak memory 290532 kb
Host smart-a27809ad-6b0d-4db8-8884-a2da285b30ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152718763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3152718763
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1636366265
Short name T620
Test name
Test status
Simulation time 397147938 ps
CPU time 34.37 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:08:07 PM PDT 24
Peak memory 256692 kb
Host smart-a36a7bd5-2072-45e3-bb1a-f1497e2f3f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16363
66265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1636366265
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3039919323
Short name T67
Test name
Test status
Simulation time 372459962 ps
CPU time 20.98 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:07:54 PM PDT 24
Peak memory 248636 kb
Host smart-38cd874a-4cc2-475c-9ccc-56cf09b55bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30399
19323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3039919323
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2939342150
Short name T660
Test name
Test status
Simulation time 1857249792 ps
CPU time 32.42 seconds
Started Jun 26 07:07:28 PM PDT 24
Finished Jun 26 07:08:03 PM PDT 24
Peak memory 257048 kb
Host smart-874c9830-f962-4c49-b067-482b8982c02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29393
42150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2939342150
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1124221195
Short name T397
Test name
Test status
Simulation time 739037637 ps
CPU time 22.12 seconds
Started Jun 26 07:07:30 PM PDT 24
Finished Jun 26 07:07:55 PM PDT 24
Peak memory 249304 kb
Host smart-07c677cd-e7a5-4ac2-b8ce-c8b4d08c8ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11242
21195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1124221195
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.90483089
Short name T379
Test name
Test status
Simulation time 50199431243 ps
CPU time 3300.21 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 08:03:11 PM PDT 24
Peak memory 306360 kb
Host smart-04e9d12b-a6f4-4837-b16c-aec2308086bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90483089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_hand
ler_stress_all.90483089
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3915914936
Short name T206
Test name
Test status
Simulation time 66103205 ps
CPU time 3.39 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:08:09 PM PDT 24
Peak memory 249496 kb
Host smart-dbbd7ab6-a583-423f-9e5f-986898894b57
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3915914936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3915914936
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1904812247
Short name T277
Test name
Test status
Simulation time 52679491066 ps
CPU time 3055.2 seconds
Started Jun 26 07:08:03 PM PDT 24
Finished Jun 26 07:59:00 PM PDT 24
Peak memory 290244 kb
Host smart-1d3bbc68-8fd1-4f56-aea8-8c5b737ab614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904812247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1904812247
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3574849996
Short name T112
Test name
Test status
Simulation time 1187795871 ps
CPU time 28.1 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:08:34 PM PDT 24
Peak memory 249216 kb
Host smart-8c6c6ea0-6a07-496a-8272-b02702b45e88
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574849996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3574849996
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1459045370
Short name T690
Test name
Test status
Simulation time 5964172954 ps
CPU time 113.38 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:10:01 PM PDT 24
Peak memory 257152 kb
Host smart-684e97bd-bbd4-453f-9ad9-609390957365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14590
45370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1459045370
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3952534589
Short name T605
Test name
Test status
Simulation time 1408927683 ps
CPU time 30.15 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:38 PM PDT 24
Peak memory 249260 kb
Host smart-2bcb9287-8150-4a8e-a9c6-af787ec3dd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
34589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3952534589
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1268267439
Short name T577
Test name
Test status
Simulation time 37231307148 ps
CPU time 1174.27 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:27:41 PM PDT 24
Peak memory 274020 kb
Host smart-69ba09a9-188f-4848-800b-1ab9b69c1694
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268267439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1268267439
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2819968940
Short name T225
Test name
Test status
Simulation time 68770575131 ps
CPU time 1869.02 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:39:14 PM PDT 24
Peak memory 273704 kb
Host smart-246453e0-3b68-42ec-9c1f-11db40ea7538
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819968940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2819968940
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2978735160
Short name T596
Test name
Test status
Simulation time 138592716 ps
CPU time 5.82 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:08:20 PM PDT 24
Peak memory 249392 kb
Host smart-eecb4405-fcb6-4262-98b8-348cfec65918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29787
35160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2978735160
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1870534059
Short name T594
Test name
Test status
Simulation time 251549592 ps
CPU time 23.56 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:08:32 PM PDT 24
Peak memory 248724 kb
Host smart-3e6cdc11-60a5-461d-a900-4ab37d28eebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18705
34059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1870534059
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.590382687
Short name T185
Test name
Test status
Simulation time 351028947 ps
CPU time 13.73 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:20 PM PDT 24
Peak memory 248684 kb
Host smart-9d21d27e-1447-4e3f-a776-f4b3dd9fd3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59038
2687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.590382687
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2953142456
Short name T375
Test name
Test status
Simulation time 5360245507 ps
CPU time 44.62 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:08:59 PM PDT 24
Peak memory 257680 kb
Host smart-23081787-b80a-4a6a-a408-291c79e0a359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29531
42456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2953142456
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3258427235
Short name T18
Test name
Test status
Simulation time 4283918701 ps
CPU time 392.03 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:14:40 PM PDT 24
Peak memory 257580 kb
Host smart-8bdf9347-4b15-41f2-b753-1792c41eaf86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258427235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3258427235
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2908407649
Short name T619
Test name
Test status
Simulation time 19549801657 ps
CPU time 1537.56 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:33:45 PM PDT 24
Peak memory 290356 kb
Host smart-2f96e1b2-701f-4a0c-b157-2dc51b2d89de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908407649 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2908407649
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2651523737
Short name T196
Test name
Test status
Simulation time 14831162 ps
CPU time 2.68 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:11 PM PDT 24
Peak memory 249608 kb
Host smart-a6540f6f-4121-47b6-8e27-40a26b7cb1d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2651523737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2651523737
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.543776387
Short name T507
Test name
Test status
Simulation time 141132966765 ps
CPU time 2079.17 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:42:53 PM PDT 24
Peak memory 274048 kb
Host smart-1e3a7e6b-0e48-406f-ad14-e997bd99a6bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543776387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.543776387
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.528651162
Short name T637
Test name
Test status
Simulation time 413051886 ps
CPU time 11.81 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:08:21 PM PDT 24
Peak memory 249248 kb
Host smart-1dfce221-138c-48e8-b615-7bf4f6c163b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=528651162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.528651162
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3942462484
Short name T495
Test name
Test status
Simulation time 3280414236 ps
CPU time 70.66 seconds
Started Jun 26 07:08:03 PM PDT 24
Finished Jun 26 07:09:15 PM PDT 24
Peak memory 257168 kb
Host smart-1f5a7288-a0c2-4056-8fd2-d6cb30983c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
62484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3942462484
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.915246056
Short name T59
Test name
Test status
Simulation time 96312514 ps
CPU time 6.6 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:14 PM PDT 24
Peak memory 249688 kb
Host smart-b9944c31-a83f-429a-b2ae-3e504f4764aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91524
6056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.915246056
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3189906156
Short name T308
Test name
Test status
Simulation time 12621469304 ps
CPU time 1065.42 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:25:59 PM PDT 24
Peak memory 286876 kb
Host smart-baa017fd-1451-48d9-8e1a-142ffe483da4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189906156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3189906156
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.777544444
Short name T693
Test name
Test status
Simulation time 200633973038 ps
CPU time 1612.68 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:35:02 PM PDT 24
Peak memory 273752 kb
Host smart-1d1ad930-9a7d-4638-ae9e-e873241dc46d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777544444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.777544444
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3705602599
Short name T273
Test name
Test status
Simulation time 58191377177 ps
CPU time 169.59 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:10:59 PM PDT 24
Peak memory 249260 kb
Host smart-0ea8130f-e5b8-435b-819f-a872f6406f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705602599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3705602599
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2546136345
Short name T393
Test name
Test status
Simulation time 771493782 ps
CPU time 51.24 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:09:00 PM PDT 24
Peak memory 249216 kb
Host smart-580b894b-e346-4efe-ab79-ea9d1cd0273d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25461
36345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2546136345
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1453089167
Short name T78
Test name
Test status
Simulation time 208150876 ps
CPU time 15.39 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:08:25 PM PDT 24
Peak memory 255840 kb
Host smart-c0b813f2-aeef-44c9-ba67-a40a4e691ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
89167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1453089167
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4004525312
Short name T84
Test name
Test status
Simulation time 1144711928 ps
CPU time 25.12 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:08:31 PM PDT 24
Peak memory 257224 kb
Host smart-2bc4daa3-239e-4907-859c-24a14112b250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40045
25312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4004525312
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1805567242
Short name T204
Test name
Test status
Simulation time 45567248 ps
CPU time 3.75 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:06:17 PM PDT 24
Peak memory 249580 kb
Host smart-4feea9f0-26b1-4497-91da-1436ce3f8bef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1805567242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1805567242
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1330444149
Short name T186
Test name
Test status
Simulation time 7051609755 ps
CPU time 832.62 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:20:09 PM PDT 24
Peak memory 273428 kb
Host smart-4a1a2e29-a063-4a1f-9c18-84ec06d1b5b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330444149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1330444149
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.935320380
Short name T659
Test name
Test status
Simulation time 2027591061 ps
CPU time 24.79 seconds
Started Jun 26 07:06:23 PM PDT 24
Finished Jun 26 07:06:49 PM PDT 24
Peak memory 249196 kb
Host smart-552fc7f7-6b88-4961-b698-e242b0b38b58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=935320380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.935320380
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3891678681
Short name T618
Test name
Test status
Simulation time 2201691806 ps
CPU time 71.96 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:07:26 PM PDT 24
Peak memory 257652 kb
Host smart-2b428189-a507-4bf7-b1b2-1e7ab0af919d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38916
78681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3891678681
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2226377202
Short name T373
Test name
Test status
Simulation time 1832071841 ps
CPU time 55.75 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:07:12 PM PDT 24
Peak memory 256496 kb
Host smart-e1154124-9333-409d-b478-5c3ee610c36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
77202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2226377202
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1012598048
Short name T6
Test name
Test status
Simulation time 25962974639 ps
CPU time 1714.97 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:34:54 PM PDT 24
Peak memory 283424 kb
Host smart-de21e81c-9882-411d-b79d-13e2ebda8d6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012598048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1012598048
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4285362043
Short name T290
Test name
Test status
Simulation time 4702166958 ps
CPU time 189.02 seconds
Started Jun 26 07:06:15 PM PDT 24
Finished Jun 26 07:09:27 PM PDT 24
Peak memory 256912 kb
Host smart-339daeb0-519c-46f6-b597-9e62dafed3c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285362043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4285362043
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1167895930
Short name T93
Test name
Test status
Simulation time 2217332932 ps
CPU time 43.85 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:58 PM PDT 24
Peak memory 256932 kb
Host smart-bc2d9723-edab-421d-8600-9c15bf9778ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11678
95930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1167895930
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4171250080
Short name T676
Test name
Test status
Simulation time 96164880 ps
CPU time 7.8 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:23 PM PDT 24
Peak memory 255600 kb
Host smart-3694cf25-0426-4911-ae76-aff7223754c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
50080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4171250080
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3187028438
Short name T11
Test name
Test status
Simulation time 1255411854 ps
CPU time 17.58 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:31 PM PDT 24
Peak memory 279204 kb
Host smart-d5cce216-fa0c-42b7-8d45-ed2d49958dcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3187028438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3187028438
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.318912398
Short name T56
Test name
Test status
Simulation time 1277749557 ps
CPU time 47.87 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:07:07 PM PDT 24
Peak memory 248532 kb
Host smart-0d8183c1-5857-4be1-8764-3e92e6597606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
2398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.318912398
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3669194430
Short name T218
Test name
Test status
Simulation time 471669398 ps
CPU time 28.51 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:06:46 PM PDT 24
Peak memory 257288 kb
Host smart-a4c7b9a3-8ada-45eb-990b-4bea7f166cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691
94430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3669194430
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2345501118
Short name T648
Test name
Test status
Simulation time 64756698185 ps
CPU time 2037.17 seconds
Started Jun 26 07:06:12 PM PDT 24
Finished Jun 26 07:40:10 PM PDT 24
Peak memory 304080 kb
Host smart-d69e4ef1-db01-489a-92e1-a03b3688bdff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345501118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2345501118
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.10721297
Short name T598
Test name
Test status
Simulation time 39506933325 ps
CPU time 2197.76 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:44:44 PM PDT 24
Peak memory 282120 kb
Host smart-9eb39964-b01d-4f52-b49b-47ad1294a27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10721297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.10721297
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3796763589
Short name T188
Test name
Test status
Simulation time 3448418136 ps
CPU time 148.1 seconds
Started Jun 26 07:08:02 PM PDT 24
Finished Jun 26 07:10:32 PM PDT 24
Peak memory 257600 kb
Host smart-a41fce27-de1e-443f-b992-277a1ffc1615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
63589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3796763589
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3949185092
Short name T100
Test name
Test status
Simulation time 649193463 ps
CPU time 25.66 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:34 PM PDT 24
Peak memory 257024 kb
Host smart-06af2dab-b119-447b-8327-168e23dd9d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491
85092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3949185092
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.4067717556
Short name T71
Test name
Test status
Simulation time 28563905804 ps
CPU time 1750.6 seconds
Started Jun 26 07:08:14 PM PDT 24
Finished Jun 26 07:37:27 PM PDT 24
Peak memory 282896 kb
Host smart-b387fcc5-aed5-4b57-92b5-03ab64d18bf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067717556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4067717556
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2159113831
Short name T310
Test name
Test status
Simulation time 26982326979 ps
CPU time 260.13 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:12:32 PM PDT 24
Peak memory 249416 kb
Host smart-57aaf727-07b8-4dd5-be77-45c1fbd9769f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159113831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2159113831
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.170551642
Short name T623
Test name
Test status
Simulation time 455367210 ps
CPU time 7.81 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:16 PM PDT 24
Peak memory 249312 kb
Host smart-a21fb9f3-5c1b-4056-85e0-b5986d4e3869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
1642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.170551642
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1571083835
Short name T524
Test name
Test status
Simulation time 1118511587 ps
CPU time 45.28 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:08:56 PM PDT 24
Peak memory 249024 kb
Host smart-840f6d93-57f1-422d-b64a-601ec46e6ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
83835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1571083835
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2183572913
Short name T572
Test name
Test status
Simulation time 524163929 ps
CPU time 32.82 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:41 PM PDT 24
Peak memory 256748 kb
Host smart-f345eb94-94f9-4ba8-bf71-4a7c664d267a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
72913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2183572913
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2696115171
Short name T368
Test name
Test status
Simulation time 133192390 ps
CPU time 9.41 seconds
Started Jun 26 07:08:03 PM PDT 24
Finished Jun 26 07:08:14 PM PDT 24
Peak memory 252300 kb
Host smart-8652a4fc-4213-406e-bf5f-1f08955549f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
15171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2696115171
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3451489293
Short name T514
Test name
Test status
Simulation time 13217229526 ps
CPU time 219.57 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:11:49 PM PDT 24
Peak memory 257708 kb
Host smart-db5f4c14-3562-4c79-a409-23c127129c69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451489293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3451489293
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.684907826
Short name T228
Test name
Test status
Simulation time 69980629984 ps
CPU time 1466.72 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:32:39 PM PDT 24
Peak memory 282328 kb
Host smart-3f0e1013-b263-4a38-8d5d-d0983c54b557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684907826 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.684907826
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4207759148
Short name T90
Test name
Test status
Simulation time 31916586460 ps
CPU time 706.46 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:19:58 PM PDT 24
Peak memory 273440 kb
Host smart-7c456d0e-3921-4dbd-8935-5825f8cfc6b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207759148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4207759148
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.372500702
Short name T609
Test name
Test status
Simulation time 5684366246 ps
CPU time 149.7 seconds
Started Jun 26 07:08:02 PM PDT 24
Finished Jun 26 07:10:33 PM PDT 24
Peak memory 257116 kb
Host smart-0d0efbbf-46af-4754-a860-a3d646b82a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37250
0702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.372500702
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2342852278
Short name T485
Test name
Test status
Simulation time 5867588643 ps
CPU time 54.14 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:09:04 PM PDT 24
Peak memory 257160 kb
Host smart-d9e780df-49b3-4515-bddb-83541f10342b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428
52278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2342852278
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3855351415
Short name T482
Test name
Test status
Simulation time 17026855992 ps
CPU time 1522.55 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:33:33 PM PDT 24
Peak memory 289168 kb
Host smart-3cf0ade7-fb66-4504-a968-40353d5a9d8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855351415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3855351415
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2561823216
Short name T448
Test name
Test status
Simulation time 504449068 ps
CPU time 30.4 seconds
Started Jun 26 07:08:04 PM PDT 24
Finished Jun 26 07:08:36 PM PDT 24
Peak memory 257224 kb
Host smart-2c4acd9f-f133-4cd5-a532-ce5031610db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25618
23216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2561823216
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3091411795
Short name T682
Test name
Test status
Simulation time 2012432660 ps
CPU time 10.17 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:17 PM PDT 24
Peak memory 254296 kb
Host smart-3a9f29be-f337-4080-b102-545404a60ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30914
11795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3091411795
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2299725786
Short name T250
Test name
Test status
Simulation time 98653996 ps
CPU time 7.38 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:08:17 PM PDT 24
Peak memory 249324 kb
Host smart-8a1c3f11-0951-4b73-b18f-1ec320680366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
25786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2299725786
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3363271261
Short name T69
Test name
Test status
Simulation time 62166745 ps
CPU time 5.61 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:08:17 PM PDT 24
Peak memory 251660 kb
Host smart-a7908e94-9ba4-4eff-b17f-7e04e7040932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632
71261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3363271261
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.494243081
Short name T463
Test name
Test status
Simulation time 179256356284 ps
CPU time 2824.41 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:55:16 PM PDT 24
Peak memory 282140 kb
Host smart-66e8cf94-7b0e-44f9-ba63-89287903e1cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494243081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.494243081
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.678971472
Short name T520
Test name
Test status
Simulation time 4241529364 ps
CPU time 133.49 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:10:22 PM PDT 24
Peak memory 257632 kb
Host smart-b26acba0-9440-4130-a4ef-85f98f943660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67897
1472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.678971472
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4259322790
Short name T462
Test name
Test status
Simulation time 546075520 ps
CPU time 18.14 seconds
Started Jun 26 07:08:03 PM PDT 24
Finished Jun 26 07:08:22 PM PDT 24
Peak memory 249220 kb
Host smart-47a478b7-7a65-43a9-a2df-e7d6be4076f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
22790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4259322790
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2318508454
Short name T447
Test name
Test status
Simulation time 23449959961 ps
CPU time 1397.25 seconds
Started Jun 26 07:08:13 PM PDT 24
Finished Jun 26 07:31:32 PM PDT 24
Peak memory 272724 kb
Host smart-327baf94-b91f-4ab9-8199-3c78398d8700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318508454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2318508454
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3007362867
Short name T680
Test name
Test status
Simulation time 12540950916 ps
CPU time 517.21 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:16:45 PM PDT 24
Peak memory 255880 kb
Host smart-c23d6cfb-624a-4c7d-9d88-b149c75ce64d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007362867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3007362867
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.301502549
Short name T483
Test name
Test status
Simulation time 405275405 ps
CPU time 35.21 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:43 PM PDT 24
Peak memory 249288 kb
Host smart-be11a0ac-e64a-4f70-a516-ef7fb398a3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
2549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.301502549
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1609479769
Short name T499
Test name
Test status
Simulation time 987154245 ps
CPU time 36.82 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:08:46 PM PDT 24
Peak memory 256776 kb
Host smart-0b7fdb83-1fa4-4491-9575-079ae5c877b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094
79769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1609479769
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2458500881
Short name T567
Test name
Test status
Simulation time 158867221 ps
CPU time 6.9 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:08:18 PM PDT 24
Peak memory 251300 kb
Host smart-4903d9c1-cf28-4f60-9996-1c4218be087d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
00881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2458500881
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.601813800
Short name T402
Test name
Test status
Simulation time 4221631601 ps
CPU time 47.35 seconds
Started Jun 26 07:08:02 PM PDT 24
Finished Jun 26 07:08:51 PM PDT 24
Peak memory 256532 kb
Host smart-9077832f-1f47-4931-9158-b057eb4b42e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60181
3800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.601813800
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4044161017
Short name T420
Test name
Test status
Simulation time 33405578318 ps
CPU time 2072.32 seconds
Started Jun 26 07:08:06 PM PDT 24
Finished Jun 26 07:42:41 PM PDT 24
Peak memory 289908 kb
Host smart-22816a89-576e-402b-9d38-9fca56a43b96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044161017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4044161017
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.48557769
Short name T437
Test name
Test status
Simulation time 44451351899 ps
CPU time 2522.33 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:50:15 PM PDT 24
Peak memory 287104 kb
Host smart-8ac01d05-293f-4365-80c8-a1e95a63a2e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48557769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.48557769
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.477570076
Short name T661
Test name
Test status
Simulation time 26876645 ps
CPU time 4.59 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:08:11 PM PDT 24
Peak memory 251288 kb
Host smart-107ebc44-04d8-49e6-af2f-1936b9d22dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47757
0076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.477570076
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3235437934
Short name T209
Test name
Test status
Simulation time 127804971 ps
CPU time 9.46 seconds
Started Jun 26 07:08:13 PM PDT 24
Finished Jun 26 07:08:24 PM PDT 24
Peak memory 255468 kb
Host smart-6b1c5316-c6b9-494d-8279-6aac4ff37189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354
37934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3235437934
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1817681094
Short name T94
Test name
Test status
Simulation time 34670903825 ps
CPU time 727.46 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:20:19 PM PDT 24
Peak memory 273884 kb
Host smart-67627dd0-0bb1-4176-b475-f59cd962f9cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817681094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1817681094
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.730634877
Short name T510
Test name
Test status
Simulation time 7956669423 ps
CPU time 331.95 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:13:46 PM PDT 24
Peak memory 257352 kb
Host smart-7f46f7f6-85a1-4fe9-9931-43784f6e88a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730634877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.730634877
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2232053817
Short name T490
Test name
Test status
Simulation time 4402809184 ps
CPU time 70.11 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:09:20 PM PDT 24
Peak memory 257028 kb
Host smart-ce70502c-55fc-43c0-a251-235377fe2b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22320
53817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2232053817
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3963743109
Short name T486
Test name
Test status
Simulation time 3045551758 ps
CPU time 42.37 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:08:53 PM PDT 24
Peak memory 257580 kb
Host smart-5b500651-e082-4555-8196-b39c5ad04497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
43109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3963743109
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2377989516
Short name T610
Test name
Test status
Simulation time 236785840 ps
CPU time 4.4 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:08:15 PM PDT 24
Peak memory 240268 kb
Host smart-013d0984-c8d0-4ec2-a32c-69a4780481c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
89516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2377989516
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3376882593
Short name T569
Test name
Test status
Simulation time 797626428 ps
CPU time 37.49 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:08:49 PM PDT 24
Peak memory 256788 kb
Host smart-48a28b69-daee-4acd-93be-792af5f80967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33768
82593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3376882593
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2656555872
Short name T488
Test name
Test status
Simulation time 162209425997 ps
CPU time 2314.96 seconds
Started Jun 26 07:08:13 PM PDT 24
Finished Jun 26 07:46:50 PM PDT 24
Peak memory 289952 kb
Host smart-ba92e80f-35b6-4195-9988-88f3bff5a185
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656555872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2656555872
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1751728619
Short name T50
Test name
Test status
Simulation time 135323452181 ps
CPU time 6867.56 seconds
Started Jun 26 07:08:13 PM PDT 24
Finished Jun 26 09:02:43 PM PDT 24
Peak memory 396100 kb
Host smart-32f2e8ce-621b-45e9-b767-78a9cd658aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751728619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1751728619
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1169843758
Short name T642
Test name
Test status
Simulation time 148117670036 ps
CPU time 2018.1 seconds
Started Jun 26 07:08:14 PM PDT 24
Finished Jun 26 07:41:54 PM PDT 24
Peak memory 284012 kb
Host smart-7c61b4d5-d3e1-49cb-ace8-1a57284fd6b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169843758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1169843758
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4036486394
Short name T629
Test name
Test status
Simulation time 3573071586 ps
CPU time 82.59 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:09:33 PM PDT 24
Peak memory 257180 kb
Host smart-df8f9b5e-daa4-4f1a-b212-8a2645cac2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
86394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4036486394
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.42003770
Short name T363
Test name
Test status
Simulation time 174609812 ps
CPU time 17.96 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:08:30 PM PDT 24
Peak memory 257104 kb
Host smart-99cddeb4-90e4-4bbb-adbe-8e768fa0acf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42003
770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.42003770
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4157611777
Short name T333
Test name
Test status
Simulation time 73289007551 ps
CPU time 1327.47 seconds
Started Jun 26 07:08:10 PM PDT 24
Finished Jun 26 07:30:20 PM PDT 24
Peak memory 272984 kb
Host smart-536f390a-de66-4cc6-81d7-db27f4eaffb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157611777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4157611777
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2473983730
Short name T581
Test name
Test status
Simulation time 7768082089 ps
CPU time 823.63 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:21:58 PM PDT 24
Peak memory 274020 kb
Host smart-149baade-6cee-4109-bdea-783c373d7f48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473983730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2473983730
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2913823261
Short name T299
Test name
Test status
Simulation time 17990340344 ps
CPU time 501.74 seconds
Started Jun 26 07:08:07 PM PDT 24
Finished Jun 26 07:16:32 PM PDT 24
Peak memory 249416 kb
Host smart-77178313-b340-416d-a1ae-ebc9673f9973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913823261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2913823261
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3037621364
Short name T214
Test name
Test status
Simulation time 3821366828 ps
CPU time 65 seconds
Started Jun 26 07:08:08 PM PDT 24
Finished Jun 26 07:09:17 PM PDT 24
Peak memory 257552 kb
Host smart-0c8001cb-3411-4d9c-8d03-4ba1e4c808b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
21364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3037621364
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2162830095
Short name T4
Test name
Test status
Simulation time 4706153516 ps
CPU time 76.04 seconds
Started Jun 26 07:08:09 PM PDT 24
Finished Jun 26 07:09:28 PM PDT 24
Peak memory 257008 kb
Host smart-021d7c7e-3d57-4d3e-86b3-833e216bcfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628
30095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2162830095
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1791721552
Short name T459
Test name
Test status
Simulation time 263492333 ps
CPU time 10.2 seconds
Started Jun 26 07:08:13 PM PDT 24
Finished Jun 26 07:08:24 PM PDT 24
Peak memory 248784 kb
Host smart-dcbc5587-eadd-4016-a53f-b373e8d2409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
21552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1791721552
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2649012661
Short name T411
Test name
Test status
Simulation time 1036036239 ps
CPU time 33.84 seconds
Started Jun 26 07:08:10 PM PDT 24
Finished Jun 26 07:08:46 PM PDT 24
Peak memory 256604 kb
Host smart-ae88ea27-a50b-46ae-b452-688cc50d5071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
12661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2649012661
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2686249672
Short name T274
Test name
Test status
Simulation time 4172322225 ps
CPU time 373.22 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:14:21 PM PDT 24
Peak memory 265916 kb
Host smart-8147e943-d098-422d-97dd-2d4706a57930
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686249672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2686249672
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1224734026
Short name T553
Test name
Test status
Simulation time 35934973402 ps
CPU time 908.76 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:24:00 PM PDT 24
Peak memory 272072 kb
Host smart-4898b10e-1f7e-4d55-89bb-0d8ee1961e23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224734026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1224734026
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.257305636
Short name T419
Test name
Test status
Simulation time 879838571 ps
CPU time 78.34 seconds
Started Jun 26 07:08:05 PM PDT 24
Finished Jun 26 07:09:25 PM PDT 24
Peak memory 257468 kb
Host smart-847b5f29-0592-406e-98b6-cc2f2cc2dd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
5636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.257305636
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2002340750
Short name T359
Test name
Test status
Simulation time 334260392 ps
CPU time 26.45 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:08:40 PM PDT 24
Peak memory 249720 kb
Host smart-48dc85fa-b581-4319-80d2-6a1ac8f88ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20023
40750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2002340750
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3215032066
Short name T223
Test name
Test status
Simulation time 153790842648 ps
CPU time 2526.49 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:50:57 PM PDT 24
Peak memory 289804 kb
Host smart-86352057-8d77-4d31-9b97-3e2ef48c90d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215032066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3215032066
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2357939370
Short name T698
Test name
Test status
Simulation time 2410561402 ps
CPU time 43.34 seconds
Started Jun 26 07:08:10 PM PDT 24
Finished Jun 26 07:08:56 PM PDT 24
Peak memory 257108 kb
Host smart-c53e93c9-d8fb-4ee8-8705-0ac85877c683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
39370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2357939370
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.523346635
Short name T658
Test name
Test status
Simulation time 313312106 ps
CPU time 29.67 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:08:43 PM PDT 24
Peak memory 256844 kb
Host smart-cf2e9d3e-7a98-4a32-a3a6-e328fb91be29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52334
6635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.523346635
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2764396908
Short name T62
Test name
Test status
Simulation time 134589694 ps
CPU time 9.24 seconds
Started Jun 26 07:08:12 PM PDT 24
Finished Jun 26 07:08:23 PM PDT 24
Peak memory 248668 kb
Host smart-ca28c375-56dc-4c88-8301-bf2eacaaf53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
96908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2764396908
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4036464830
Short name T578
Test name
Test status
Simulation time 413314784 ps
CPU time 42.7 seconds
Started Jun 26 07:08:10 PM PDT 24
Finished Jun 26 07:08:55 PM PDT 24
Peak memory 257468 kb
Host smart-f6e5d3b0-9f7b-466a-bdbb-7ee439b8b95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
64830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4036464830
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.4283042792
Short name T453
Test name
Test status
Simulation time 35031109102 ps
CPU time 2298.14 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:47:09 PM PDT 24
Peak memory 290416 kb
Host smart-246b1f55-6ef9-4417-a85c-c1e9f7683362
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283042792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.4283042792
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1436714488
Short name T25
Test name
Test status
Simulation time 40421336589 ps
CPU time 124.48 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:10:59 PM PDT 24
Peak memory 256684 kb
Host smart-4fceb83a-f063-401a-93ad-d8c5b9748ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367
14488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1436714488
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1267704450
Short name T358
Test name
Test status
Simulation time 227143813 ps
CPU time 25.09 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:20 PM PDT 24
Peak memory 249272 kb
Host smart-7db02c7d-dc03-45e6-b586-8b844e1f4e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12677
04450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1267704450
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.218883484
Short name T270
Test name
Test status
Simulation time 49379236674 ps
CPU time 1086.85 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:27:05 PM PDT 24
Peak memory 273948 kb
Host smart-81c0612e-3c2d-4871-8dfb-dc14dda4c5ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218883484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.218883484
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2405621851
Short name T588
Test name
Test status
Simulation time 45406789689 ps
CPU time 1740.45 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:37:54 PM PDT 24
Peak memory 273820 kb
Host smart-b7c6c197-2c5a-4817-89bf-9827ba250ffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405621851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2405621851
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3461898486
Short name T40
Test name
Test status
Simulation time 7665699667 ps
CPU time 161.07 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:11:35 PM PDT 24
Peak memory 249244 kb
Host smart-ecfb8683-43f5-4e0b-9f03-1b7aca174c43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461898486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3461898486
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2542545129
Short name T580
Test name
Test status
Simulation time 1812371559 ps
CPU time 60.02 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:09:50 PM PDT 24
Peak memory 257196 kb
Host smart-4b7902d9-e144-47dc-9048-38ccd2fe2dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25425
45129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2542545129
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4149834277
Short name T362
Test name
Test status
Simulation time 395846780 ps
CPU time 13.52 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:11 PM PDT 24
Peak memory 248828 kb
Host smart-015459f9-7f31-4b38-9edd-ae200a49be75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41498
34277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4149834277
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1531169291
Short name T103
Test name
Test status
Simulation time 335881311 ps
CPU time 48.91 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:09:40 PM PDT 24
Peak memory 250352 kb
Host smart-958d4b15-c28c-4a4e-af3d-667afe2ecda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
69291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1531169291
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2444597790
Short name T479
Test name
Test status
Simulation time 429414504 ps
CPU time 26.82 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:09:18 PM PDT 24
Peak memory 256536 kb
Host smart-5e6e82c2-6865-4010-9717-66d2c6f4c211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24445
97790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2444597790
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1793634685
Short name T86
Test name
Test status
Simulation time 49529379691 ps
CPU time 1006.37 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:25:38 PM PDT 24
Peak memory 286392 kb
Host smart-cdbf0898-8843-4b4f-ab1a-25b810ca270b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793634685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1793634685
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3252932232
Short name T632
Test name
Test status
Simulation time 41769193455 ps
CPU time 1245.63 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:29:43 PM PDT 24
Peak memory 285088 kb
Host smart-3dd99529-153f-4451-b6b8-2e532bedc987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252932232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3252932232
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2697023378
Short name T440
Test name
Test status
Simulation time 980545099 ps
CPU time 66.81 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:10:02 PM PDT 24
Peak memory 257032 kb
Host smart-8a66fe94-2596-4449-9660-8cd12943d3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
23378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2697023378
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1677210734
Short name T622
Test name
Test status
Simulation time 208958600 ps
CPU time 22.14 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:19 PM PDT 24
Peak memory 249272 kb
Host smart-3d3ed53c-3497-451b-b628-aa8f86de65b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772
10734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1677210734
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.490360941
Short name T699
Test name
Test status
Simulation time 57537159088 ps
CPU time 995.13 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:25:27 PM PDT 24
Peak memory 270948 kb
Host smart-7ba38b7d-cb40-47a0-9d1d-d608f0895107
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490360941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.490360941
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1516766335
Short name T311
Test name
Test status
Simulation time 2916320392 ps
CPU time 120.95 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:10:59 PM PDT 24
Peak memory 249364 kb
Host smart-6ea41a2b-274e-4d76-81bc-4f09585e56ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516766335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1516766335
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2035530020
Short name T52
Test name
Test status
Simulation time 593007856 ps
CPU time 30.91 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:09:22 PM PDT 24
Peak memory 249244 kb
Host smart-10f4dbaf-089b-4505-a990-b8b54c000d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20355
30020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2035530020
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3649372242
Short name T272
Test name
Test status
Simulation time 150830096 ps
CPU time 11.07 seconds
Started Jun 26 07:08:57 PM PDT 24
Finished Jun 26 07:09:13 PM PDT 24
Peak memory 248576 kb
Host smart-8265498a-2fe5-4534-9ed6-e27e6a242558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
72242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3649372242
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3688959290
Short name T562
Test name
Test status
Simulation time 101599883 ps
CPU time 11.32 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:09 PM PDT 24
Peak memory 256704 kb
Host smart-7878db02-afed-40e0-86d4-19982d5ff1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36889
59290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3688959290
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.639383080
Short name T517
Test name
Test status
Simulation time 1446976301 ps
CPU time 29.06 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:25 PM PDT 24
Peak memory 257416 kb
Host smart-336f5f2d-22bd-4ab5-8386-406e3116b080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63938
3080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.639383080
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2195574288
Short name T668
Test name
Test status
Simulation time 16409038266 ps
CPU time 250.16 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:13:07 PM PDT 24
Peak memory 257508 kb
Host smart-c0b38418-2072-4463-93f9-0698fe06b606
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195574288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2195574288
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.272708798
Short name T254
Test name
Test status
Simulation time 192914900403 ps
CPU time 7130.27 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 09:07:48 PM PDT 24
Peak memory 339352 kb
Host smart-c2e302b2-8e56-42bc-9688-45d557850bf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272708798 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.272708798
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1365605826
Short name T503
Test name
Test status
Simulation time 43147643361 ps
CPU time 1058.42 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:26:35 PM PDT 24
Peak memory 273988 kb
Host smart-017819dd-d55e-4e85-a2f8-c8db8a8ca9d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365605826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1365605826
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1579307345
Short name T426
Test name
Test status
Simulation time 4381925098 ps
CPU time 99.16 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:10:31 PM PDT 24
Peak memory 257564 kb
Host smart-f12ae162-7621-420f-9df1-87e56fb7bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15793
07345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1579307345
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.291731952
Short name T545
Test name
Test status
Simulation time 883394538 ps
CPU time 56.12 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:09:48 PM PDT 24
Peak memory 249868 kb
Host smart-cd85537a-5f87-4c6e-80ea-bc171d8a39d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
1952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.291731952
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3571590662
Short name T306
Test name
Test status
Simulation time 43073540488 ps
CPU time 1563.01 seconds
Started Jun 26 07:08:57 PM PDT 24
Finished Jun 26 07:35:04 PM PDT 24
Peak memory 273860 kb
Host smart-209f1cad-4d2f-4e02-b1d9-fc591b8b7a95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571590662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3571590662
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.955002793
Short name T372
Test name
Test status
Simulation time 52011869843 ps
CPU time 1302.27 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:30:40 PM PDT 24
Peak memory 288000 kb
Host smart-4f15648d-beba-47ff-ab04-eccfa2594bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955002793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.955002793
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1075507468
Short name T645
Test name
Test status
Simulation time 785494238 ps
CPU time 19.77 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:15 PM PDT 24
Peak memory 249328 kb
Host smart-5616d3bc-a095-4832-8932-b1185fede8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
07468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1075507468
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3392744848
Short name T382
Test name
Test status
Simulation time 224314364 ps
CPU time 15.79 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:11 PM PDT 24
Peak memory 248692 kb
Host smart-07706980-7dc6-44e4-8aea-8da493d6e277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
44848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3392744848
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4180437968
Short name T253
Test name
Test status
Simulation time 307536127 ps
CPU time 19.35 seconds
Started Jun 26 07:08:49 PM PDT 24
Finished Jun 26 07:09:09 PM PDT 24
Peak memory 256096 kb
Host smart-615ed737-5ab4-49c7-9b0c-3cd91d54d252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
37968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4180437968
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3973459937
Short name T657
Test name
Test status
Simulation time 478933380 ps
CPU time 16.16 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:10 PM PDT 24
Peak memory 257208 kb
Host smart-76afd796-4901-4239-a2df-a27ade7208ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
59937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3973459937
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3920942969
Short name T452
Test name
Test status
Simulation time 60391985371 ps
CPU time 3868.62 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 08:13:24 PM PDT 24
Peak memory 297956 kb
Host smart-1a062e1c-930a-437c-a378-967a6d109ad9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920942969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3920942969
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3124885918
Short name T575
Test name
Test status
Simulation time 253814752319 ps
CPU time 6369.71 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 08:55:06 PM PDT 24
Peak memory 355696 kb
Host smart-16cb03b3-6b41-4f47-bcd3-050fdfdaa68e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124885918 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3124885918
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.273199691
Short name T271
Test name
Test status
Simulation time 35301442408 ps
CPU time 2041.6 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:42:54 PM PDT 24
Peak memory 273876 kb
Host smart-0c9e5f9c-1882-40ee-a197-5b725b112655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273199691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.273199691
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1402103600
Short name T550
Test name
Test status
Simulation time 3272209916 ps
CPU time 179.94 seconds
Started Jun 26 07:08:54 PM PDT 24
Finished Jun 26 07:11:58 PM PDT 24
Peak memory 257184 kb
Host smart-4a18cd12-f77d-47a3-970c-d294720a1152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14021
03600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1402103600
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2413720741
Short name T579
Test name
Test status
Simulation time 455086302 ps
CPU time 10.83 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:08 PM PDT 24
Peak memory 249300 kb
Host smart-54261325-a792-4fd2-9419-b18e41606d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137
20741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2413720741
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1840242035
Short name T183
Test name
Test status
Simulation time 19929332954 ps
CPU time 1319.2 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:30:56 PM PDT 24
Peak memory 289808 kb
Host smart-a48bf9c6-a779-4db8-9182-df8f5f01ba7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840242035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1840242035
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1889499173
Short name T621
Test name
Test status
Simulation time 10667081049 ps
CPU time 389 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:15:26 PM PDT 24
Peak memory 256452 kb
Host smart-b74b3180-9120-4f2e-b946-41af6916fd7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889499173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1889499173
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2226438865
Short name T591
Test name
Test status
Simulation time 1587124081 ps
CPU time 28.05 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:22 PM PDT 24
Peak memory 257500 kb
Host smart-5648ed42-634f-4f0d-8d17-648dc25c0674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22264
38865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2226438865
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3022072542
Short name T47
Test name
Test status
Simulation time 770128879 ps
CPU time 36.55 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:30 PM PDT 24
Peak memory 257476 kb
Host smart-d2645714-06d1-41a7-a979-518ca24c786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
72542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3022072542
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2192115799
Short name T651
Test name
Test status
Simulation time 3795282941 ps
CPU time 61.96 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:56 PM PDT 24
Peak memory 249384 kb
Host smart-e661e65b-848d-4d65-9f81-9a38d53183b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21921
15799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2192115799
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4193133591
Short name T529
Test name
Test status
Simulation time 1708338710 ps
CPU time 59.93 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:58 PM PDT 24
Peak memory 249508 kb
Host smart-c30f3071-23e5-4cbb-a49c-8ac12655a514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41931
33591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4193133591
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.710656367
Short name T104
Test name
Test status
Simulation time 36798531290 ps
CPU time 854.25 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:23:08 PM PDT 24
Peak memory 271040 kb
Host smart-e6b2c7e6-a703-4b7d-97ff-0666cd4e3022
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710656367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.710656367
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2157397140
Short name T75
Test name
Test status
Simulation time 18890724998 ps
CPU time 2040.33 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:42:56 PM PDT 24
Peak memory 290356 kb
Host smart-70286736-148e-44d1-84c2-cb28ae940fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157397140 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2157397140
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1546729263
Short name T199
Test name
Test status
Simulation time 47756653 ps
CPU time 3.34 seconds
Started Jun 26 07:06:16 PM PDT 24
Finished Jun 26 07:06:22 PM PDT 24
Peak memory 249492 kb
Host smart-43fea5a6-f5f5-4a6c-bdbf-681e8de22c19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1546729263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1546729263
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1818883713
Short name T460
Test name
Test status
Simulation time 33002211896 ps
CPU time 2095.62 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:41:15 PM PDT 24
Peak memory 290148 kb
Host smart-f14adc10-a7de-4e49-add2-21ed03d05d8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818883713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1818883713
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2547092626
Short name T445
Test name
Test status
Simulation time 314927883 ps
CPU time 17.13 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:06:37 PM PDT 24
Peak memory 248172 kb
Host smart-34c78443-957d-4b99-a23d-07cb63a08bb6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2547092626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2547092626
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.361585240
Short name T525
Test name
Test status
Simulation time 6912094855 ps
CPU time 164.5 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:09:04 PM PDT 24
Peak memory 257588 kb
Host smart-1a66a930-5527-4356-b927-9b6145ed6cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158
5240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.361585240
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3489696117
Short name T587
Test name
Test status
Simulation time 316457655 ps
CPU time 8.18 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:06:27 PM PDT 24
Peak memory 248708 kb
Host smart-42013ac1-7f1d-444c-a504-90ee7033591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34896
96117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3489696117
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1330992152
Short name T337
Test name
Test status
Simulation time 321100733730 ps
CPU time 2055.51 seconds
Started Jun 26 07:06:17 PM PDT 24
Finished Jun 26 07:40:35 PM PDT 24
Peak memory 289620 kb
Host smart-e71dd43d-731f-416d-a04b-98c9a40cafd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330992152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1330992152
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.147198
Short name T396
Test name
Test status
Simulation time 24260721511 ps
CPU time 1328.58 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:28:25 PM PDT 24
Peak memory 273720 kb
Host smart-8ea21c6f-9a52-4ce9-8675-f50e35f6af11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.147198
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2949405685
Short name T294
Test name
Test status
Simulation time 47748246071 ps
CPU time 565.95 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:15:41 PM PDT 24
Peak memory 249420 kb
Host smart-48103368-daee-46d0-a9cb-326a270b927a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949405685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2949405685
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.814195004
Short name T13
Test name
Test status
Simulation time 2233240875 ps
CPU time 88.37 seconds
Started Jun 26 07:06:37 PM PDT 24
Finished Jun 26 07:08:06 PM PDT 24
Peak memory 271612 kb
Host smart-c5e35b35-baef-4776-b31f-4516d54f54f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=814195004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.814195004
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1186657489
Short name T364
Test name
Test status
Simulation time 214116043 ps
CPU time 8 seconds
Started Jun 26 07:06:13 PM PDT 24
Finished Jun 26 07:06:23 PM PDT 24
Peak memory 255440 kb
Host smart-9b143427-cc49-473b-b15a-a4d968aacf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11866
57489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1186657489
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3939273061
Short name T395
Test name
Test status
Simulation time 234779944 ps
CPU time 8.92 seconds
Started Jun 26 07:06:14 PM PDT 24
Finished Jun 26 07:06:25 PM PDT 24
Peak memory 249220 kb
Host smart-20520a53-432a-492d-9140-8a3070710899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392
73061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3939273061
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.63081401
Short name T473
Test name
Test status
Simulation time 428134110580 ps
CPU time 1671.89 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:36:47 PM PDT 24
Peak memory 283240 kb
Host smart-ed9eb1b9-61e3-4d20-85c4-c52a81fa343f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63081401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.63081401
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2873660500
Short name T611
Test name
Test status
Simulation time 2149200882 ps
CPU time 149.6 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:11:23 PM PDT 24
Peak memory 257140 kb
Host smart-b1eb4805-9aa0-40eb-be5e-9868f5cc8c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28736
60500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2873660500
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.244293572
Short name T376
Test name
Test status
Simulation time 556294021 ps
CPU time 25 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:20 PM PDT 24
Peak memory 257100 kb
Host smart-3b6d851c-f346-4e2a-ae87-09a3d540376c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24429
3572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.244293572
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2886859249
Short name T329
Test name
Test status
Simulation time 211610005570 ps
CPU time 1853.44 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:39:48 PM PDT 24
Peak memory 273648 kb
Host smart-7964206f-ae9d-442f-a456-8ef5c43390ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886859249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2886859249
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2951205343
Short name T687
Test name
Test status
Simulation time 19464403562 ps
CPU time 1814.84 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:39:10 PM PDT 24
Peak memory 289612 kb
Host smart-d812cc3a-2817-4bc6-bbaf-12e40de6cc30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951205343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2951205343
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3887293987
Short name T532
Test name
Test status
Simulation time 43718579322 ps
CPU time 409.08 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:15:45 PM PDT 24
Peak memory 256812 kb
Host smart-365084dc-c788-4dc4-93bb-98c8d956d094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887293987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3887293987
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1536831637
Short name T29
Test name
Test status
Simulation time 87656139 ps
CPU time 5.21 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:01 PM PDT 24
Peak memory 241016 kb
Host smart-fb607a3b-a4a7-4737-8fe6-ebbe720fab35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15368
31637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1536831637
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2983855629
Short name T576
Test name
Test status
Simulation time 212462735 ps
CPU time 11.32 seconds
Started Jun 26 07:08:50 PM PDT 24
Finished Jun 26 07:09:05 PM PDT 24
Peak memory 248876 kb
Host smart-09665b77-c944-47f7-b0ad-ce0b98e60525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
55629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2983855629
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.146538648
Short name T481
Test name
Test status
Simulation time 1579529910 ps
CPU time 35.37 seconds
Started Jun 26 07:08:54 PM PDT 24
Finished Jun 26 07:09:34 PM PDT 24
Peak memory 249648 kb
Host smart-04cb31e2-53cb-4029-87a4-d5837632eb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
8648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.146538648
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3106139617
Short name T431
Test name
Test status
Simulation time 1123780131 ps
CPU time 19.33 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:14 PM PDT 24
Peak memory 256592 kb
Host smart-84c24e1f-2269-4741-9ce0-cc363d78f44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
39617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3106139617
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.727710035
Short name T98
Test name
Test status
Simulation time 398593237713 ps
CPU time 3510.62 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 08:07:27 PM PDT 24
Peak memory 289752 kb
Host smart-4f78d0ab-d3bd-4250-91a0-2e89b4094504
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727710035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.727710035
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3092311618
Short name T413
Test name
Test status
Simulation time 19996385890 ps
CPU time 300.3 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:13:57 PM PDT 24
Peak memory 252504 kb
Host smart-6f75feb2-d436-47c6-a69c-8ad53625e7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
11618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3092311618
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2535519688
Short name T421
Test name
Test status
Simulation time 329461668 ps
CPU time 22.33 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:20 PM PDT 24
Peak memory 248880 kb
Host smart-9adfe42b-46fe-4ee1-a591-3a79cef7baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
19688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2535519688
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3156192618
Short name T327
Test name
Test status
Simulation time 29513884580 ps
CPU time 1606.67 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:35:44 PM PDT 24
Peak memory 273300 kb
Host smart-da9a0308-0001-45c4-b17a-e8b48ea838ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156192618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3156192618
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1405299324
Short name T692
Test name
Test status
Simulation time 63497171681 ps
CPU time 1398.42 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:32:15 PM PDT 24
Peak memory 273636 kb
Host smart-f6b08618-6767-40b8-90b9-40c483dac809
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405299324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1405299324
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1909735775
Short name T456
Test name
Test status
Simulation time 21422086446 ps
CPU time 146.31 seconds
Started Jun 26 07:08:57 PM PDT 24
Finished Jun 26 07:11:27 PM PDT 24
Peak memory 256780 kb
Host smart-0bf43fdb-991d-4e9f-a999-5909ae1dd183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909735775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1909735775
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2953161633
Short name T472
Test name
Test status
Simulation time 360887049 ps
CPU time 31.74 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:28 PM PDT 24
Peak memory 256764 kb
Host smart-e09e4179-1113-4917-b46c-09575191e826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29531
61633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2953161633
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1556041986
Short name T627
Test name
Test status
Simulation time 658420368 ps
CPU time 19.54 seconds
Started Jun 26 07:08:51 PM PDT 24
Finished Jun 26 07:09:15 PM PDT 24
Peak memory 257524 kb
Host smart-b7ab8eb6-240d-47d7-bb66-1b7d127e4be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
41986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1556041986
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4240096366
Short name T399
Test name
Test status
Simulation time 1296648380 ps
CPU time 42.51 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:09:39 PM PDT 24
Peak memory 257236 kb
Host smart-2bf43665-7e8a-4a6b-a74c-ea0267aed165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
96366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4240096366
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.971976667
Short name T674
Test name
Test status
Simulation time 4677854951 ps
CPU time 71.22 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:10:09 PM PDT 24
Peak memory 257596 kb
Host smart-b99f8b04-1dc4-475e-92ec-14529c28d585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97197
6667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.971976667
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2134078022
Short name T416
Test name
Test status
Simulation time 36855817682 ps
CPU time 2027.92 seconds
Started Jun 26 07:08:57 PM PDT 24
Finished Jun 26 07:42:50 PM PDT 24
Peak memory 284160 kb
Host smart-69e48df8-e7c4-4ede-a9a6-23a36958f121
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134078022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2134078022
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.392104272
Short name T476
Test name
Test status
Simulation time 129815536746 ps
CPU time 1662.43 seconds
Started Jun 26 07:09:15 PM PDT 24
Finished Jun 26 07:36:59 PM PDT 24
Peak memory 273748 kb
Host smart-8a69088b-8629-4e9e-a375-c6f5d46e06e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392104272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.392104272
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1771928619
Short name T400
Test name
Test status
Simulation time 2753590774 ps
CPU time 193.53 seconds
Started Jun 26 07:08:52 PM PDT 24
Finished Jun 26 07:12:10 PM PDT 24
Peak memory 257580 kb
Host smart-df21c7ed-dcc3-45f0-86e0-675108ed174a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
28619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1771928619
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.101806579
Short name T380
Test name
Test status
Simulation time 191614422 ps
CPU time 12.74 seconds
Started Jun 26 07:08:54 PM PDT 24
Finished Jun 26 07:09:11 PM PDT 24
Peak memory 248876 kb
Host smart-052db3bb-0fb4-4737-babf-5ee6a80d4a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
6579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.101806579
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1379893024
Short name T315
Test name
Test status
Simulation time 155123354776 ps
CPU time 1732.26 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:38:13 PM PDT 24
Peak memory 274024 kb
Host smart-99c1574d-e484-4ff5-8d12-4d6ded48563a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379893024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1379893024
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2264059034
Short name T377
Test name
Test status
Simulation time 25881671550 ps
CPU time 1718.13 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:37:58 PM PDT 24
Peak memory 274028 kb
Host smart-6e78efc7-fdf8-4280-a949-4885f72d231b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264059034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2264059034
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3720474217
Short name T297
Test name
Test status
Simulation time 35644380638 ps
CPU time 401.83 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:16:04 PM PDT 24
Peak memory 248992 kb
Host smart-917c61c1-4f4c-404c-a74d-6aae193a7575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720474217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3720474217
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1185122900
Short name T406
Test name
Test status
Simulation time 774281244 ps
CPU time 41.37 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:39 PM PDT 24
Peak memory 256744 kb
Host smart-d87d44d5-a86d-4cef-85a0-da5455b196f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
22900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1185122900
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3541727855
Short name T451
Test name
Test status
Simulation time 742088150 ps
CPU time 41.74 seconds
Started Jun 26 07:08:54 PM PDT 24
Finished Jun 26 07:09:40 PM PDT 24
Peak memory 249296 kb
Host smart-1cb31a3d-bf12-4937-b87c-0a41cd0516c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
27855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3541727855
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.222017741
Short name T544
Test name
Test status
Simulation time 2356833263 ps
CPU time 39.79 seconds
Started Jun 26 07:08:57 PM PDT 24
Finished Jun 26 07:09:41 PM PDT 24
Peak memory 256952 kb
Host smart-ca75d967-de31-4627-878c-246c6f4ea9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
7741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.222017741
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.828397517
Short name T501
Test name
Test status
Simulation time 143457296 ps
CPU time 9.73 seconds
Started Jun 26 07:08:53 PM PDT 24
Finished Jun 26 07:09:07 PM PDT 24
Peak memory 252240 kb
Host smart-c6b0ad70-b782-44b7-9960-cb28de93c04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82839
7517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.828397517
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3778867597
Short name T256
Test name
Test status
Simulation time 41825126110 ps
CPU time 2374.91 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:48:56 PM PDT 24
Peak memory 288836 kb
Host smart-6d89a9cb-a830-4d5b-bbec-67e8de2dd6dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778867597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3778867597
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.130467982
Short name T43
Test name
Test status
Simulation time 95690480234 ps
CPU time 9588.97 seconds
Started Jun 26 07:09:20 PM PDT 24
Finished Jun 26 09:49:13 PM PDT 24
Peak memory 394980 kb
Host smart-95d8b410-9df9-4a94-b160-29037acdf4c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130467982 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.130467982
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3806328870
Short name T496
Test name
Test status
Simulation time 17026685212 ps
CPU time 1069.93 seconds
Started Jun 26 07:09:15 PM PDT 24
Finished Jun 26 07:27:07 PM PDT 24
Peak memory 265832 kb
Host smart-02df06bf-3036-4661-b140-3e74b9f103ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806328870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3806328870
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4280018166
Short name T494
Test name
Test status
Simulation time 18131479431 ps
CPU time 143.9 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:11:43 PM PDT 24
Peak memory 257144 kb
Host smart-df8d2819-8f3b-403c-8ad1-24a0c785080f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
18166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4280018166
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1247293882
Short name T640
Test name
Test status
Simulation time 222820093 ps
CPU time 25.29 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 07:09:47 PM PDT 24
Peak memory 256556 kb
Host smart-32c6a10a-8260-4450-a7ff-16b3ecfbb39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12472
93882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1247293882
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4099470853
Short name T539
Test name
Test status
Simulation time 59752283204 ps
CPU time 1871.14 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:40:31 PM PDT 24
Peak memory 282704 kb
Host smart-2dd1e300-c35a-41f2-8af3-8fae7e6072b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099470853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4099470853
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3218756014
Short name T446
Test name
Test status
Simulation time 37783731141 ps
CPU time 2408.16 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:49:29 PM PDT 24
Peak memory 289912 kb
Host smart-72c59d9a-6db6-4b17-907f-477155ec0bd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218756014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3218756014
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3782120028
Short name T292
Test name
Test status
Simulation time 34724043853 ps
CPU time 340.08 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 07:15:02 PM PDT 24
Peak memory 249320 kb
Host smart-07c69406-5e08-47c4-bb2d-99b4fe427fdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782120028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3782120028
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2067710653
Short name T230
Test name
Test status
Simulation time 1131095046 ps
CPU time 54.35 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:10:13 PM PDT 24
Peak memory 256872 kb
Host smart-052d44e3-4581-415a-9f5f-cef0b178d135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
10653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2067710653
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3005476379
Short name T526
Test name
Test status
Simulation time 1499041840 ps
CPU time 49.35 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:10:09 PM PDT 24
Peak memory 248832 kb
Host smart-118dfcfa-dcca-4bb1-a23c-8c0b2d03c30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30054
76379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3005476379
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2982684213
Short name T68
Test name
Test status
Simulation time 1237727772 ps
CPU time 22.36 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:41 PM PDT 24
Peak memory 249332 kb
Host smart-778ab911-4f77-498c-a3e4-6d9906160e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29826
84213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2982684213
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1399104711
Short name T360
Test name
Test status
Simulation time 336072859 ps
CPU time 28.95 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:09:50 PM PDT 24
Peak memory 257136 kb
Host smart-380594e4-57a3-4ef1-ab9a-36a4b6f70d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
04711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1399104711
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4124003490
Short name T547
Test name
Test status
Simulation time 1808562214 ps
CPU time 108.41 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 07:11:10 PM PDT 24
Peak memory 257380 kb
Host smart-764dd303-f9ae-45c6-9638-97daf9e96dab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124003490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4124003490
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2035087155
Short name T88
Test name
Test status
Simulation time 301533134501 ps
CPU time 7642.28 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 09:16:44 PM PDT 24
Peak memory 395560 kb
Host smart-16ce4f97-03dc-45c2-ab54-5639f4c4f5a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035087155 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2035087155
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2498045701
Short name T686
Test name
Test status
Simulation time 241347615 ps
CPU time 20.66 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:40 PM PDT 24
Peak memory 256508 kb
Host smart-aa1fde0f-5d7c-4fc9-a57a-abca2d622d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
45701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2498045701
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2560848153
Short name T350
Test name
Test status
Simulation time 443981485 ps
CPU time 10.08 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:30 PM PDT 24
Peak memory 255432 kb
Host smart-a794799c-72ee-49dc-b5d8-1e5638ece4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
48153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2560848153
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1198319486
Short name T332
Test name
Test status
Simulation time 27145855501 ps
CPU time 1610.97 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:36:10 PM PDT 24
Peak memory 273964 kb
Host smart-0b254527-3428-46f3-93ad-d801e3dda7e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198319486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1198319486
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.435370210
Short name T97
Test name
Test status
Simulation time 31852081676 ps
CPU time 2013.07 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:42:55 PM PDT 24
Peak memory 286920 kb
Host smart-7beee053-b600-4061-9a4a-dba8561ff1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435370210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.435370210
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1773289114
Short name T289
Test name
Test status
Simulation time 9656948653 ps
CPU time 106.34 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:11:07 PM PDT 24
Peak memory 255364 kb
Host smart-96e751f2-241b-4b92-9124-ad88db85c648
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773289114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1773289114
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.542807980
Short name T644
Test name
Test status
Simulation time 222579698 ps
CPU time 14.58 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 07:09:36 PM PDT 24
Peak memory 249280 kb
Host smart-e661a2b8-b50e-4106-b306-bbdcfd0d438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54280
7980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.542807980
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.247965493
Short name T604
Test name
Test status
Simulation time 1884501549 ps
CPU time 18.28 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:09:39 PM PDT 24
Peak memory 248980 kb
Host smart-6ecc0dc1-fc1a-4c78-b627-fba497b4c4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
5493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.247965493
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1553002350
Short name T249
Test name
Test status
Simulation time 484379028 ps
CPU time 16.17 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:09:37 PM PDT 24
Peak memory 254956 kb
Host smart-d14031b6-eda9-4aec-a4aa-725f9cd82145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530
02350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1553002350
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1851110769
Short name T528
Test name
Test status
Simulation time 931765156 ps
CPU time 14.25 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:33 PM PDT 24
Peak memory 255876 kb
Host smart-6b9ae2ce-4ffc-4657-bd5b-a02033a2785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18511
10769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1851110769
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2865924777
Short name T102
Test name
Test status
Simulation time 381680220962 ps
CPU time 5292.9 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 08:37:33 PM PDT 24
Peak memory 354924 kb
Host smart-61c78037-5bd3-4f5c-a32c-1ba83fa228ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865924777 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2865924777
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3381022207
Short name T655
Test name
Test status
Simulation time 700331128374 ps
CPU time 3090.12 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 08:00:51 PM PDT 24
Peak memory 282188 kb
Host smart-b4dae3d0-713e-495c-818f-9a70fdadabab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381022207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3381022207
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1830752002
Short name T36
Test name
Test status
Simulation time 17476882044 ps
CPU time 216.55 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:12:57 PM PDT 24
Peak memory 257164 kb
Host smart-799ea681-8efa-4ba8-a5f0-66f5c0d7f902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
52002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1830752002
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2751412875
Short name T584
Test name
Test status
Simulation time 5289835499 ps
CPU time 52.95 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:10:12 PM PDT 24
Peak memory 249404 kb
Host smart-c8ba2b05-7f32-42d9-a3e0-b09727d78302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
12875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2751412875
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4284407699
Short name T265
Test name
Test status
Simulation time 24319094701 ps
CPU time 1376.23 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 07:32:17 PM PDT 24
Peak memory 273940 kb
Host smart-2f349c61-3c0d-431e-b7c8-f56eb8fe4f94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284407699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4284407699
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.864397396
Short name T638
Test name
Test status
Simulation time 21699218254 ps
CPU time 806.14 seconds
Started Jun 26 07:09:20 PM PDT 24
Finished Jun 26 07:22:49 PM PDT 24
Peak memory 269868 kb
Host smart-a5b357b4-f930-4c68-8086-c4a28e983db9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864397396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.864397396
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2297135067
Short name T301
Test name
Test status
Simulation time 25825324600 ps
CPU time 267.96 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:13:50 PM PDT 24
Peak memory 249420 kb
Host smart-1f7d2022-015e-46ea-a5f7-fb37ca7b0de0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297135067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2297135067
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3778413664
Short name T554
Test name
Test status
Simulation time 637630543 ps
CPU time 35.34 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:09:57 PM PDT 24
Peak memory 256716 kb
Host smart-219f941a-9e71-4937-abd6-a54083bc5028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37784
13664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3778413664
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2723573435
Short name T423
Test name
Test status
Simulation time 381261127 ps
CPU time 8.02 seconds
Started Jun 26 07:09:15 PM PDT 24
Finished Jun 26 07:09:25 PM PDT 24
Peak memory 248532 kb
Host smart-d7fddb97-c07b-41b8-a824-5c06414a17d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
73435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2723573435
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.687063702
Short name T561
Test name
Test status
Simulation time 1062371816 ps
CPU time 32.22 seconds
Started Jun 26 07:09:17 PM PDT 24
Finished Jun 26 07:09:53 PM PDT 24
Peak memory 249216 kb
Host smart-348c6cd1-9275-4134-a24b-23a494b94180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68706
3702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.687063702
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1644643916
Short name T384
Test name
Test status
Simulation time 218272272 ps
CPU time 9.76 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:29 PM PDT 24
Peak memory 255376 kb
Host smart-d7c1f403-06c2-46b5-8bd5-cbaf63142321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446
43916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1644643916
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.769689659
Short name T111
Test name
Test status
Simulation time 26031346684 ps
CPU time 1854.45 seconds
Started Jun 26 07:09:15 PM PDT 24
Finished Jun 26 07:40:11 PM PDT 24
Peak memory 284144 kb
Host smart-65fa02d3-730a-4d6b-89ae-2fa6a4313da4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769689659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.769689659
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2894171187
Short name T240
Test name
Test status
Simulation time 115443918970 ps
CPU time 9977.34 seconds
Started Jun 26 07:09:18 PM PDT 24
Finished Jun 26 09:55:39 PM PDT 24
Peak memory 404072 kb
Host smart-5dce5ad9-1276-4791-a44d-b017d7fd7bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894171187 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2894171187
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2280439237
Short name T504
Test name
Test status
Simulation time 32951686274 ps
CPU time 1607.66 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:36:22 PM PDT 24
Peak memory 273936 kb
Host smart-95550165-043b-49b3-ba3b-7592fae43e99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280439237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2280439237
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3449321150
Short name T468
Test name
Test status
Simulation time 1950584624 ps
CPU time 184.9 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:12:38 PM PDT 24
Peak memory 257500 kb
Host smart-a6f439cb-6245-4f6c-8655-9e5d0f2f8439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34493
21150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3449321150
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3340514622
Short name T34
Test name
Test status
Simulation time 330031689 ps
CPU time 37.44 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:57 PM PDT 24
Peak memory 257384 kb
Host smart-948d318c-a7d2-48c3-8d7e-369b5b0dc57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
14622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3340514622
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3253524195
Short name T231
Test name
Test status
Simulation time 78635505226 ps
CPU time 1373.51 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:32:27 PM PDT 24
Peak memory 286580 kb
Host smart-51199a64-82a9-4927-85e1-320f5e125363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253524195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3253524195
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3723908164
Short name T32
Test name
Test status
Simulation time 56272086541 ps
CPU time 1434.56 seconds
Started Jun 26 07:10:15 PM PDT 24
Finished Jun 26 07:34:11 PM PDT 24
Peak memory 289364 kb
Host smart-4588359d-7930-4ee8-84c8-a9adf420f894
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723908164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3723908164
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3618898618
Short name T286
Test name
Test status
Simulation time 13853087905 ps
CPU time 289.38 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:14:24 PM PDT 24
Peak memory 257396 kb
Host smart-86ab6cf2-eb80-4f59-816d-ee8697c0ed67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618898618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3618898618
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1810455291
Short name T51
Test name
Test status
Simulation time 387062169 ps
CPU time 23.73 seconds
Started Jun 26 07:09:16 PM PDT 24
Finished Jun 26 07:09:43 PM PDT 24
Peak memory 256752 kb
Host smart-167544f4-b637-49e1-98b6-4eeaf5150bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
55291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1810455291
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.509392779
Short name T613
Test name
Test status
Simulation time 1224221655 ps
CPU time 24.85 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:09:59 PM PDT 24
Peak memory 256540 kb
Host smart-0cc8c31b-3011-4a07-9833-d24a1765060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50939
2779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.509392779
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1895980121
Short name T351
Test name
Test status
Simulation time 1525961647 ps
CPU time 22.49 seconds
Started Jun 26 07:09:19 PM PDT 24
Finished Jun 26 07:09:45 PM PDT 24
Peak memory 249716 kb
Host smart-e4adde6a-6f17-4147-9750-a219ff847fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959
80121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1895980121
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1811609700
Short name T259
Test name
Test status
Simulation time 12768441303 ps
CPU time 1165.08 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:28:59 PM PDT 24
Peak memory 287220 kb
Host smart-68e4c8e4-4eb9-44ba-9401-11ae2ea7b9b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811609700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1811609700
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.646794018
Short name T276
Test name
Test status
Simulation time 11252399846 ps
CPU time 1071.32 seconds
Started Jun 26 07:09:31 PM PDT 24
Finished Jun 26 07:27:26 PM PDT 24
Peak memory 273976 kb
Host smart-e4c98774-b05f-453d-8316-7d33fee8f96a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646794018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.646794018
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3962573974
Short name T408
Test name
Test status
Simulation time 6435413793 ps
CPU time 270.76 seconds
Started Jun 26 07:09:33 PM PDT 24
Finished Jun 26 07:14:06 PM PDT 24
Peak memory 256972 kb
Host smart-5d287f90-16bd-4d49-83ee-504a118d43fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
73974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3962573974
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1885864980
Short name T391
Test name
Test status
Simulation time 2056107858 ps
CPU time 30.42 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:10:03 PM PDT 24
Peak memory 249892 kb
Host smart-0ea7b722-57a9-41fe-935d-70d9717f8b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
64980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1885864980
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2754025486
Short name T688
Test name
Test status
Simulation time 28405855494 ps
CPU time 1161.55 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:28:55 PM PDT 24
Peak memory 288576 kb
Host smart-df9b7e57-c7ea-4b4d-a285-557a88d3930e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754025486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2754025486
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3589239604
Short name T403
Test name
Test status
Simulation time 9265298067 ps
CPU time 821.74 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:23:15 PM PDT 24
Peak memory 273336 kb
Host smart-05f1dbab-b08e-4815-9e1a-f16710256fbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589239604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3589239604
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2407075003
Short name T300
Test name
Test status
Simulation time 12832022027 ps
CPU time 515.46 seconds
Started Jun 26 07:09:33 PM PDT 24
Finished Jun 26 07:18:11 PM PDT 24
Peak memory 256316 kb
Host smart-9c655dbf-c031-4ce1-91cc-a8c6d9881e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407075003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2407075003
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2481538396
Short name T523
Test name
Test status
Simulation time 1391060068 ps
CPU time 13.66 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:09:47 PM PDT 24
Peak memory 249508 kb
Host smart-3a595c68-537f-4813-a767-9455d2b50338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
38396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2481538396
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1871108384
Short name T614
Test name
Test status
Simulation time 462032304 ps
CPU time 13.23 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:09:46 PM PDT 24
Peak memory 248944 kb
Host smart-b9d46399-74e8-4481-80ab-afef9660f2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18711
08384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1871108384
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1606651495
Short name T552
Test name
Test status
Simulation time 758925517 ps
CPU time 28.43 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:10:01 PM PDT 24
Peak memory 248756 kb
Host smart-03976b3e-0088-43c1-bc4b-ffa720a6ff51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
51495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1606651495
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3245030322
Short name T546
Test name
Test status
Simulation time 845853501 ps
CPU time 29.62 seconds
Started Jun 26 07:09:30 PM PDT 24
Finished Jun 26 07:10:03 PM PDT 24
Peak memory 256812 kb
Host smart-3caeafea-7e60-4435-a77a-0a6806e52c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32450
30322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3245030322
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.496373633
Short name T442
Test name
Test status
Simulation time 32393935975 ps
CPU time 798.87 seconds
Started Jun 26 07:09:43 PM PDT 24
Finished Jun 26 07:23:04 PM PDT 24
Peak memory 273368 kb
Host smart-9f146a03-106a-4ee8-abe4-61d03f434d45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496373633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.496373633
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.250425312
Short name T480
Test name
Test status
Simulation time 208076754002 ps
CPU time 3262.08 seconds
Started Jun 26 07:09:41 PM PDT 24
Finished Jun 26 08:04:06 PM PDT 24
Peak memory 290364 kb
Host smart-dfcf650a-7812-408e-ae80-28a2745ac486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250425312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.250425312
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1383342089
Short name T80
Test name
Test status
Simulation time 3442191466 ps
CPU time 223.52 seconds
Started Jun 26 07:09:42 PM PDT 24
Finished Jun 26 07:13:28 PM PDT 24
Peak memory 257220 kb
Host smart-f862e31f-8801-42f3-ad8a-4ffac9123d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13833
42089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1383342089
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.405000635
Short name T354
Test name
Test status
Simulation time 354581778 ps
CPU time 18.82 seconds
Started Jun 26 07:09:42 PM PDT 24
Finished Jun 26 07:10:04 PM PDT 24
Peak memory 249032 kb
Host smart-c9877df4-1240-44d2-a109-092da0faa618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40500
0635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.405000635
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.929834972
Short name T331
Test name
Test status
Simulation time 198236017574 ps
CPU time 2943.82 seconds
Started Jun 26 07:09:42 PM PDT 24
Finished Jun 26 07:58:49 PM PDT 24
Peak memory 288156 kb
Host smart-7805c8f2-80ab-420f-be92-f3368da3dcd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929834972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.929834972
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3175449291
Short name T356
Test name
Test status
Simulation time 18983326484 ps
CPU time 946.72 seconds
Started Jun 26 07:09:43 PM PDT 24
Finished Jun 26 07:25:32 PM PDT 24
Peak memory 273940 kb
Host smart-f3146973-8774-443b-a598-e662d262fb51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175449291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3175449291
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3491691413
Short name T571
Test name
Test status
Simulation time 15442616052 ps
CPU time 656.31 seconds
Started Jun 26 07:09:40 PM PDT 24
Finished Jun 26 07:20:39 PM PDT 24
Peak memory 249372 kb
Host smart-1dd4f4f4-c1ed-4114-bce4-bbd4dd7ab4df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491691413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3491691413
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.4179286084
Short name T374
Test name
Test status
Simulation time 790902608 ps
CPU time 29.8 seconds
Started Jun 26 07:09:43 PM PDT 24
Finished Jun 26 07:10:15 PM PDT 24
Peak memory 249236 kb
Host smart-bac26325-462d-4ee4-b603-29185a3351dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41792
86084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.4179286084
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2206076461
Short name T455
Test name
Test status
Simulation time 203309941 ps
CPU time 14.3 seconds
Started Jun 26 07:09:42 PM PDT 24
Finished Jun 26 07:09:59 PM PDT 24
Peak memory 249292 kb
Host smart-8fc41695-6026-4e20-8e72-f5947ebdc6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
76461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2206076461
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4164575409
Short name T543
Test name
Test status
Simulation time 1115021043 ps
CPU time 37.11 seconds
Started Jun 26 07:09:41 PM PDT 24
Finished Jun 26 07:10:21 PM PDT 24
Peak memory 256412 kb
Host smart-9f0cfec1-75de-46d9-8883-ed6dcfec5cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
75409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4164575409
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3787113574
Short name T498
Test name
Test status
Simulation time 495845537 ps
CPU time 9.99 seconds
Started Jun 26 07:09:41 PM PDT 24
Finished Jun 26 07:09:54 PM PDT 24
Peak memory 249600 kb
Host smart-334da8f0-e5e4-452d-8815-7cef8b0a21d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871
13574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3787113574
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3088702234
Short name T322
Test name
Test status
Simulation time 87938748933 ps
CPU time 3247.3 seconds
Started Jun 26 07:09:40 PM PDT 24
Finished Jun 26 08:03:51 PM PDT 24
Peak memory 302324 kb
Host smart-844e9204-5264-47e8-88f3-d09c12765f56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088702234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3088702234
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2181971554
Short name T91
Test name
Test status
Simulation time 44848953331 ps
CPU time 2735.53 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:55:34 PM PDT 24
Peak memory 289272 kb
Host smart-f95a4211-f08a-4d3d-a209-3bbbd6b3ebbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181971554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2181971554
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3175017025
Short name T353
Test name
Test status
Simulation time 1834707634 ps
CPU time 143.08 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:12:19 PM PDT 24
Peak memory 257292 kb
Host smart-1b60f234-2e7d-49b0-8f03-ea219ee7006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
17025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3175017025
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.820870530
Short name T616
Test name
Test status
Simulation time 380628453 ps
CPU time 11.34 seconds
Started Jun 26 07:09:40 PM PDT 24
Finished Jun 26 07:09:54 PM PDT 24
Peak memory 248852 kb
Host smart-0a336816-2a03-4ee0-9df6-580615f0b14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82087
0530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.820870530
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.183024799
Short name T335
Test name
Test status
Simulation time 26733308517 ps
CPU time 1426.38 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:33:46 PM PDT 24
Peak memory 289316 kb
Host smart-a9e5c288-5932-4397-b1e9-6c03f424b1ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183024799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.183024799
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.453325575
Short name T548
Test name
Test status
Simulation time 74946336989 ps
CPU time 2451.47 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:50:48 PM PDT 24
Peak memory 290320 kb
Host smart-4979e538-137f-44de-91e8-221d2d8693d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453325575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.453325575
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1858080029
Short name T412
Test name
Test status
Simulation time 3130741969 ps
CPU time 36.25 seconds
Started Jun 26 07:09:41 PM PDT 24
Finished Jun 26 07:10:20 PM PDT 24
Peak memory 257064 kb
Host smart-76b256e8-3fb9-42d6-a02e-9a1250252e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
80029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1858080029
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4009100018
Short name T394
Test name
Test status
Simulation time 612742635 ps
CPU time 37.74 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:10:35 PM PDT 24
Peak memory 257524 kb
Host smart-4cc78d00-9b44-43e2-9a88-d325f406d293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
00018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4009100018
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3900088573
Short name T409
Test name
Test status
Simulation time 13604130081 ps
CPU time 53.75 seconds
Started Jun 26 07:09:43 PM PDT 24
Finished Jun 26 07:10:39 PM PDT 24
Peak memory 249576 kb
Host smart-4a67e76b-7595-4d7e-a9f5-24359f4608b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000
88573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3900088573
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1695597322
Short name T66
Test name
Test status
Simulation time 90120750515 ps
CPU time 920.43 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:25:17 PM PDT 24
Peak memory 290124 kb
Host smart-70f777e6-54fe-4855-a279-024b675f69ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695597322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1695597322
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2256220995
Short name T203
Test name
Test status
Simulation time 26202162 ps
CPU time 2.65 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:06:33 PM PDT 24
Peak memory 249560 kb
Host smart-3971eb50-a851-4671-922c-a064b7c8f529
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2256220995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2256220995
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2273231709
Short name T428
Test name
Test status
Simulation time 183982719679 ps
CPU time 1714.86 seconds
Started Jun 26 07:06:30 PM PDT 24
Finished Jun 26 07:35:07 PM PDT 24
Peak memory 274024 kb
Host smart-e4a58eae-833d-4eb2-8dd9-d5f4dc7767ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273231709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2273231709
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2266387052
Short name T559
Test name
Test status
Simulation time 2572159923 ps
CPU time 30.12 seconds
Started Jun 26 07:06:30 PM PDT 24
Finished Jun 26 07:07:02 PM PDT 24
Peak memory 249416 kb
Host smart-8b6b29ef-492a-44f5-a0f5-78a75bb40998
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2266387052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2266387052
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2860497672
Short name T357
Test name
Test status
Simulation time 1181265302 ps
CPU time 68.31 seconds
Started Jun 26 07:06:37 PM PDT 24
Finished Jun 26 07:07:46 PM PDT 24
Peak memory 257044 kb
Host smart-6fba47c4-35a7-4fca-9320-4b3587c92849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
97672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2860497672
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3082986170
Short name T702
Test name
Test status
Simulation time 1345786305 ps
CPU time 42.02 seconds
Started Jun 26 07:06:37 PM PDT 24
Finished Jun 26 07:07:20 PM PDT 24
Peak memory 256612 kb
Host smart-a786f47b-3cac-4004-a296-b7193ee734ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30829
86170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3082986170
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3133184127
Short name T31
Test name
Test status
Simulation time 23201867572 ps
CPU time 1435.34 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:30:27 PM PDT 24
Peak memory 273712 kb
Host smart-5817f2a6-68f5-4689-8568-dcc186c0fdaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133184127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3133184127
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4103593793
Short name T630
Test name
Test status
Simulation time 38367157 ps
CPU time 4.98 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:06:39 PM PDT 24
Peak memory 249288 kb
Host smart-76892a3b-f3b8-4a11-9e93-76da110e3708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41035
93793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4103593793
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.436813039
Short name T10
Test name
Test status
Simulation time 396029366 ps
CPU time 29.89 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:07:03 PM PDT 24
Peak memory 256944 kb
Host smart-4057e032-6b8b-4da0-b723-de725c26b8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43681
3039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.436813039
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.389511375
Short name T28
Test name
Test status
Simulation time 1521122952 ps
CPU time 25.25 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:06:55 PM PDT 24
Peak memory 270652 kb
Host smart-b9f033aa-1eac-4205-9421-d27ca7913fd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=389511375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.389511375
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1978469210
Short name T20
Test name
Test status
Simulation time 3440932538 ps
CPU time 44.43 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:07:14 PM PDT 24
Peak memory 256744 kb
Host smart-8e62051a-4d77-4b9d-8f7a-807821043462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19784
69210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1978469210
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2508174006
Short name T366
Test name
Test status
Simulation time 773301497 ps
CPU time 30.22 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:06:59 PM PDT 24
Peak memory 249320 kb
Host smart-2bbaeb40-968e-4e4f-9601-c240703d4398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25081
74006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2508174006
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3337448715
Short name T92
Test name
Test status
Simulation time 22172616388 ps
CPU time 1167.87 seconds
Started Jun 26 07:06:26 PM PDT 24
Finished Jun 26 07:25:55 PM PDT 24
Peak memory 290088 kb
Host smart-bc1a4b2c-898c-4283-92a5-4f414e75ffdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337448715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3337448715
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1181647113
Short name T227
Test name
Test status
Simulation time 25607470015 ps
CPU time 410.61 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:13:24 PM PDT 24
Peak memory 266972 kb
Host smart-73a2fa0f-66ae-4db3-beb2-eda9ef1186d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181647113 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1181647113
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1844105714
Short name T410
Test name
Test status
Simulation time 17581203890 ps
CPU time 1115.01 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:28:34 PM PDT 24
Peak memory 267816 kb
Host smart-3de201ba-9041-4365-b8d1-2e5827048b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844105714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1844105714
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.108541252
Short name T85
Test name
Test status
Simulation time 244307265 ps
CPU time 25.01 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:10:24 PM PDT 24
Peak memory 257412 kb
Host smart-dc2f8b80-3aa6-4dc0-9170-243d9d85739f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854
1252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.108541252
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1191897413
Short name T424
Test name
Test status
Simulation time 3576138702 ps
CPU time 50.27 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:10:48 PM PDT 24
Peak memory 248836 kb
Host smart-748d1119-4fe5-4a7d-9869-04c605dae9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
97413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1191897413
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4235021538
Short name T334
Test name
Test status
Simulation time 16834162069 ps
CPU time 895.3 seconds
Started Jun 26 07:09:57 PM PDT 24
Finished Jun 26 07:24:55 PM PDT 24
Peak memory 273972 kb
Host smart-6529e85c-4595-403c-8f28-bacf3e1af95e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235021538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4235021538
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4116718212
Short name T224
Test name
Test status
Simulation time 126042950673 ps
CPU time 1958.81 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:42:37 PM PDT 24
Peak memory 284068 kb
Host smart-6e0f4ec9-9640-4b8c-aa34-01f62724e71d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116718212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4116718212
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2519741968
Short name T313
Test name
Test status
Simulation time 49985662440 ps
CPU time 483.01 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:18:00 PM PDT 24
Peak memory 255956 kb
Host smart-18865c14-da7e-4474-9202-363d7f799e9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519741968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2519741968
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3610864679
Short name T189
Test name
Test status
Simulation time 776110933 ps
CPU time 22.02 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:10:20 PM PDT 24
Peak memory 249224 kb
Host smart-d3328230-1d06-4aee-937a-cbf789e6e69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
64679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3610864679
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2145148315
Short name T48
Test name
Test status
Simulation time 250298739 ps
CPU time 25.09 seconds
Started Jun 26 07:09:53 PM PDT 24
Finished Jun 26 07:10:20 PM PDT 24
Peak memory 249320 kb
Host smart-15c6fe1b-cdb6-45ea-854c-9759400d5083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
48315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2145148315
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3217987462
Short name T8
Test name
Test status
Simulation time 187122105 ps
CPU time 25.99 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:10:24 PM PDT 24
Peak memory 249228 kb
Host smart-7a3be371-7c98-42d5-b8d8-74e92651b297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32179
87462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3217987462
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3694852382
Short name T511
Test name
Test status
Simulation time 723160557 ps
CPU time 54.42 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:10:53 PM PDT 24
Peak memory 249240 kb
Host smart-af040e46-dce0-4f09-bd9b-4fe060505a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
52382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3694852382
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.852556793
Short name T625
Test name
Test status
Simulation time 96382598701 ps
CPU time 2953.27 seconds
Started Jun 26 07:09:56 PM PDT 24
Finished Jun 26 07:59:12 PM PDT 24
Peak memory 281776 kb
Host smart-3490985e-e659-4e73-82df-bb8129d6892f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852556793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.852556793
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2119953532
Short name T489
Test name
Test status
Simulation time 37597789470 ps
CPU time 2304.69 seconds
Started Jun 26 07:10:09 PM PDT 24
Finished Jun 26 07:48:35 PM PDT 24
Peak memory 283048 kb
Host smart-23d1016a-dce5-4221-8d01-23860ffcffa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119953532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2119953532
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2273860021
Short name T519
Test name
Test status
Simulation time 910270929 ps
CPU time 38.49 seconds
Started Jun 26 07:10:09 PM PDT 24
Finished Jun 26 07:10:49 PM PDT 24
Peak memory 256844 kb
Host smart-3f4f0323-515a-449a-b5c9-0a9614b76a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22738
60021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2273860021
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3494567154
Short name T457
Test name
Test status
Simulation time 1566079990 ps
CPU time 40.37 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:10:54 PM PDT 24
Peak memory 256620 kb
Host smart-bb10fabc-540d-4651-a013-ba28f68dfeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
67154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3494567154
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3387927923
Short name T320
Test name
Test status
Simulation time 36906267341 ps
CPU time 1028.51 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:27:23 PM PDT 24
Peak memory 273344 kb
Host smart-55ee5cfa-179b-4d6b-b411-3a36e1e3d022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387927923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3387927923
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2845594594
Short name T673
Test name
Test status
Simulation time 95421328508 ps
CPU time 2858.6 seconds
Started Jun 26 07:10:09 PM PDT 24
Finished Jun 26 07:57:49 PM PDT 24
Peak memory 289556 kb
Host smart-1b7cae0c-ce15-4c8c-bdb8-52450965111d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845594594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2845594594
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.781223375
Short name T318
Test name
Test status
Simulation time 25218806562 ps
CPU time 502.94 seconds
Started Jun 26 07:10:10 PM PDT 24
Finished Jun 26 07:18:35 PM PDT 24
Peak memory 249404 kb
Host smart-9fd1080b-3a71-4745-8715-87522369ac84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781223375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.781223375
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.407004977
Short name T684
Test name
Test status
Simulation time 289052303 ps
CPU time 27.85 seconds
Started Jun 26 07:10:10 PM PDT 24
Finished Jun 26 07:10:39 PM PDT 24
Peak memory 257444 kb
Host smart-de1b4002-3d35-423e-81bf-286cddead156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40700
4977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.407004977
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3185295788
Short name T491
Test name
Test status
Simulation time 351348455 ps
CPU time 30.4 seconds
Started Jun 26 07:10:09 PM PDT 24
Finished Jun 26 07:10:41 PM PDT 24
Peak memory 248752 kb
Host smart-437bd43b-32a8-4cd9-b3e9-791324484fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
95788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3185295788
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1109670645
Short name T367
Test name
Test status
Simulation time 54050752 ps
CPU time 5.31 seconds
Started Jun 26 07:09:55 PM PDT 24
Finished Jun 26 07:10:02 PM PDT 24
Peak memory 249296 kb
Host smart-ab635fe6-caef-472b-ad8e-f6beb078e7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11096
70645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1109670645
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1499741946
Short name T647
Test name
Test status
Simulation time 40017334350 ps
CPU time 2357.08 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:49:32 PM PDT 24
Peak memory 290168 kb
Host smart-f08eab1d-4223-4904-be45-e0dbd1994cf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499741946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1499741946
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3503810197
Short name T278
Test name
Test status
Simulation time 2664644371 ps
CPU time 168.34 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:13:03 PM PDT 24
Peak memory 257180 kb
Host smart-8d3a627a-0cb2-47ac-a786-db38de5f8c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35038
10197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3503810197
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4112871410
Short name T469
Test name
Test status
Simulation time 904070805 ps
CPU time 48.76 seconds
Started Jun 26 07:10:12 PM PDT 24
Finished Jun 26 07:11:02 PM PDT 24
Peak memory 257236 kb
Host smart-8aeb1fa5-3d98-4b9a-8c55-28868aaaad3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
71410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4112871410
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2384439386
Short name T691
Test name
Test status
Simulation time 297342045755 ps
CPU time 2070.33 seconds
Started Jun 26 07:10:12 PM PDT 24
Finished Jun 26 07:44:44 PM PDT 24
Peak memory 282152 kb
Host smart-586f0520-695f-4ead-823d-f1bc53c47b61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384439386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2384439386
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.735443456
Short name T530
Test name
Test status
Simulation time 58803113916 ps
CPU time 1747.86 seconds
Started Jun 26 07:10:12 PM PDT 24
Finished Jun 26 07:39:21 PM PDT 24
Peak memory 284464 kb
Host smart-eabb7ea9-44a0-4831-a6d9-6d84567c0188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735443456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.735443456
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1627273160
Short name T649
Test name
Test status
Simulation time 13685207169 ps
CPU time 587.97 seconds
Started Jun 26 07:10:11 PM PDT 24
Finished Jun 26 07:20:00 PM PDT 24
Peak memory 249660 kb
Host smart-dc354c33-598c-4dd4-a0ad-0873538d051f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627273160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1627273160
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4067411226
Short name T513
Test name
Test status
Simulation time 295026121 ps
CPU time 11.28 seconds
Started Jun 26 07:10:10 PM PDT 24
Finished Jun 26 07:10:22 PM PDT 24
Peak memory 249288 kb
Host smart-4d409ed7-73d8-4536-9953-46a21333b4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
11226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4067411226
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2304904042
Short name T262
Test name
Test status
Simulation time 1866013586 ps
CPU time 53.75 seconds
Started Jun 26 07:10:10 PM PDT 24
Finished Jun 26 07:11:05 PM PDT 24
Peak memory 249276 kb
Host smart-4b394feb-d1a5-441d-b88a-6b97db320242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23049
04042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2304904042
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3540671968
Short name T76
Test name
Test status
Simulation time 169935751 ps
CPU time 24.98 seconds
Started Jun 26 07:10:11 PM PDT 24
Finished Jun 26 07:10:37 PM PDT 24
Peak memory 248780 kb
Host smart-0be81a0d-5dac-408a-a56e-845c7a35b33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
71968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3540671968
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2147484397
Short name T487
Test name
Test status
Simulation time 718412491 ps
CPU time 12.89 seconds
Started Jun 26 07:10:13 PM PDT 24
Finished Jun 26 07:10:27 PM PDT 24
Peak memory 249328 kb
Host smart-054df0f0-d771-4caa-8f8b-8ca7f824255b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21474
84397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2147484397
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.974100635
Short name T217
Test name
Test status
Simulation time 25646422280 ps
CPU time 397.73 seconds
Started Jun 26 07:10:11 PM PDT 24
Finished Jun 26 07:16:50 PM PDT 24
Peak memory 257596 kb
Host smart-1b3e1be1-613c-4db9-ba63-2a91e74c09e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974100635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.974100635
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1993635428
Short name T110
Test name
Test status
Simulation time 10054998126 ps
CPU time 908.38 seconds
Started Jun 26 07:10:28 PM PDT 24
Finished Jun 26 07:25:39 PM PDT 24
Peak memory 273368 kb
Host smart-ba64e3c1-32e5-44a4-8b15-785f879f2f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993635428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1993635428
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.4236258112
Short name T234
Test name
Test status
Simulation time 6627948973 ps
CPU time 115.56 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:12:27 PM PDT 24
Peak memory 257096 kb
Host smart-70b75b8a-45e9-4e29-a612-44fd49ba0340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
58112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4236258112
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2094396759
Short name T474
Test name
Test status
Simulation time 188588108 ps
CPU time 18.01 seconds
Started Jun 26 07:10:28 PM PDT 24
Finished Jun 26 07:10:48 PM PDT 24
Peak memory 257028 kb
Host smart-6f9c575c-f5ee-424a-8831-226b2e0a64c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
96759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2094396759
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.620343402
Short name T283
Test name
Test status
Simulation time 23691841348 ps
CPU time 1133.47 seconds
Started Jun 26 07:10:31 PM PDT 24
Finished Jun 26 07:29:26 PM PDT 24
Peak memory 274028 kb
Host smart-0630f3a5-7a5e-4637-be5a-32c1364f9da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620343402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.620343402
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1540765534
Short name T72
Test name
Test status
Simulation time 52456222543 ps
CPU time 1966.91 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:43:18 PM PDT 24
Peak memory 283404 kb
Host smart-0a763306-73f9-45a3-9819-2c76642a8c42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540765534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1540765534
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2080390186
Short name T302
Test name
Test status
Simulation time 15054334825 ps
CPU time 153.05 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:13:04 PM PDT 24
Peak memory 249404 kb
Host smart-2b7aaac4-f78f-42ba-909e-3601f13cc3c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080390186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2080390186
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2505711808
Short name T361
Test name
Test status
Simulation time 1762612701 ps
CPU time 19.16 seconds
Started Jun 26 07:10:11 PM PDT 24
Finished Jun 26 07:10:32 PM PDT 24
Peak memory 249280 kb
Host smart-56972c83-a522-4b94-b023-91320215f499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057
11808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2505711808
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3127852575
Short name T432
Test name
Test status
Simulation time 558026990 ps
CPU time 40.14 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:11:11 PM PDT 24
Peak memory 249388 kb
Host smart-c36abdb6-63f0-4d4b-b0fd-90d722578f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
52575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3127852575
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.797190933
Short name T538
Test name
Test status
Simulation time 1120035663 ps
CPU time 30.05 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:11:01 PM PDT 24
Peak memory 257340 kb
Host smart-8e46b049-18b2-41ef-8c78-912d8f39a55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79719
0933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.797190933
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2470038312
Short name T435
Test name
Test status
Simulation time 536396615 ps
CPU time 31.84 seconds
Started Jun 26 07:10:11 PM PDT 24
Finished Jun 26 07:10:44 PM PDT 24
Peak memory 257248 kb
Host smart-54b4f2e0-83df-423d-b1fd-ec3fe1237d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
38312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2470038312
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.141549092
Short name T46
Test name
Test status
Simulation time 70840288595 ps
CPU time 1338.3 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:32:49 PM PDT 24
Peak memory 290024 kb
Host smart-518c2aa8-ace2-4dc3-a579-b3f313b6ccd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141549092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.141549092
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.189971430
Short name T221
Test name
Test status
Simulation time 7028285396 ps
CPU time 722.8 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:22:34 PM PDT 24
Peak memory 273800 kb
Host smart-732df6aa-67d3-49c4-a8a3-bcd1245ded64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189971430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.189971430
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1560191492
Short name T444
Test name
Test status
Simulation time 2571061333 ps
CPU time 77.11 seconds
Started Jun 26 07:10:30 PM PDT 24
Finished Jun 26 07:11:49 PM PDT 24
Peak memory 257052 kb
Host smart-7ae64da9-a3a9-4826-ad19-d76bc1ee9c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
91492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1560191492
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1274655466
Short name T466
Test name
Test status
Simulation time 384933774 ps
CPU time 7.94 seconds
Started Jun 26 07:10:27 PM PDT 24
Finished Jun 26 07:10:37 PM PDT 24
Peak memory 249212 kb
Host smart-8a411791-a956-44f8-bf66-7b8f57d4d3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12746
55466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1274655466
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.820805959
Short name T602
Test name
Test status
Simulation time 13086917207 ps
CPU time 1404.3 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:33:56 PM PDT 24
Peak memory 282636 kb
Host smart-53655a67-76f2-4e79-87bc-37f823e4b7af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820805959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.820805959
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.360957507
Short name T508
Test name
Test status
Simulation time 116758530940 ps
CPU time 2581.85 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:53:33 PM PDT 24
Peak memory 290176 kb
Host smart-64acc573-9b18-474b-ad2d-0d2ac7246d48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360957507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.360957507
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3363084816
Short name T549
Test name
Test status
Simulation time 277337997 ps
CPU time 17.85 seconds
Started Jun 26 07:10:31 PM PDT 24
Finished Jun 26 07:10:50 PM PDT 24
Peak memory 249420 kb
Host smart-59c613c7-bb67-4714-897a-5bce8943f194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33630
84816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3363084816
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.4272474028
Short name T612
Test name
Test status
Simulation time 3501124633 ps
CPU time 50.11 seconds
Started Jun 26 07:10:27 PM PDT 24
Finished Jun 26 07:11:20 PM PDT 24
Peak memory 257596 kb
Host smart-94c00c15-2826-4356-aa01-308ae56dc790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
74028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4272474028
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.107638867
Short name T246
Test name
Test status
Simulation time 2439060104 ps
CPU time 40.86 seconds
Started Jun 26 07:10:30 PM PDT 24
Finished Jun 26 07:11:13 PM PDT 24
Peak memory 249116 kb
Host smart-ae952a2d-5a96-49e4-98f8-8e80b7df7ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10763
8867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.107638867
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3886342376
Short name T607
Test name
Test status
Simulation time 3456936491 ps
CPU time 52.42 seconds
Started Jun 26 07:10:31 PM PDT 24
Finished Jun 26 07:11:25 PM PDT 24
Peak memory 257636 kb
Host smart-98b4efac-c039-44f0-ba60-4f10fe58b0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
42376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3886342376
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3763859590
Short name T386
Test name
Test status
Simulation time 183116043 ps
CPU time 23.02 seconds
Started Jun 26 07:10:30 PM PDT 24
Finished Jun 26 07:10:55 PM PDT 24
Peak memory 257508 kb
Host smart-151d448c-714f-42c7-a792-bc0d90b67407
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763859590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3763859590
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1408413151
Short name T365
Test name
Test status
Simulation time 1597792833 ps
CPU time 105.81 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:12:32 PM PDT 24
Peak memory 256652 kb
Host smart-a178e7e3-ad65-40da-ab27-5fac7747d7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
13151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1408413151
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1280255233
Short name T694
Test name
Test status
Simulation time 58421262 ps
CPU time 8.9 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:10:54 PM PDT 24
Peak memory 249012 kb
Host smart-e0d6a972-3fc5-4d81-936c-c01ff81e1433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
55233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1280255233
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3790993165
Short name T336
Test name
Test status
Simulation time 18685113919 ps
CPU time 1113.01 seconds
Started Jun 26 07:10:49 PM PDT 24
Finished Jun 26 07:29:23 PM PDT 24
Peak memory 273968 kb
Host smart-ce4630f3-3def-46b4-aa9a-bfcc4fef1b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790993165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3790993165
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2539510280
Short name T675
Test name
Test status
Simulation time 174920984904 ps
CPU time 2641.84 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:54:48 PM PDT 24
Peak memory 290408 kb
Host smart-869e7d99-e102-49ee-828b-5fcdc9cfafd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539510280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2539510280
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3232915519
Short name T316
Test name
Test status
Simulation time 33283797146 ps
CPU time 346.25 seconds
Started Jun 26 07:10:43 PM PDT 24
Finished Jun 26 07:16:30 PM PDT 24
Peak memory 249380 kb
Host smart-47d59924-ee63-43af-aa8b-1076e999d338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232915519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3232915519
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.167134994
Short name T439
Test name
Test status
Simulation time 681586186 ps
CPU time 51.43 seconds
Started Jun 26 07:10:28 PM PDT 24
Finished Jun 26 07:11:22 PM PDT 24
Peak memory 256752 kb
Host smart-0c61ab62-f099-4ade-a89f-d0d39f9e805a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
4994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.167134994
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3832143553
Short name T107
Test name
Test status
Simulation time 707062226 ps
CPU time 27.28 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:11:13 PM PDT 24
Peak memory 256840 kb
Host smart-e3e6c674-6ca4-4f05-ab94-1cfa96ab5915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
43553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3832143553
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4043600848
Short name T558
Test name
Test status
Simulation time 3022670979 ps
CPU time 47.95 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:11:33 PM PDT 24
Peak memory 249464 kb
Host smart-53d0187a-b344-4274-90f6-5c727953829e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
00848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4043600848
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3524970315
Short name T2
Test name
Test status
Simulation time 340325606 ps
CPU time 14.27 seconds
Started Jun 26 07:10:29 PM PDT 24
Finished Jun 26 07:10:45 PM PDT 24
Peak memory 256124 kb
Host smart-7469399d-d557-4c02-a00b-99c0599a9ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35249
70315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3524970315
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1503733895
Short name T255
Test name
Test status
Simulation time 58528871236 ps
CPU time 3436.22 seconds
Started Jun 26 07:10:45 PM PDT 24
Finished Jun 26 08:08:03 PM PDT 24
Peak memory 290492 kb
Host smart-263df318-7f5f-4c0b-9efe-a90d91abce43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503733895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1503733895
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4278415167
Short name T624
Test name
Test status
Simulation time 187744657647 ps
CPU time 2424.73 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:51:14 PM PDT 24
Peak memory 289696 kb
Host smart-28142aed-4bac-44c6-927e-6aa1e97fe80d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278415167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4278415167
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.892139117
Short name T697
Test name
Test status
Simulation time 4152149206 ps
CPU time 172.49 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:13:42 PM PDT 24
Peak memory 256764 kb
Host smart-7941d7a0-f590-4032-a7f9-76b825abefed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89213
9117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.892139117
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2530878274
Short name T566
Test name
Test status
Simulation time 282958758 ps
CPU time 20.91 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:11:10 PM PDT 24
Peak memory 249272 kb
Host smart-f0598a3b-daea-44e4-b35a-7687f798cf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25308
78274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2530878274
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2109313341
Short name T81
Test name
Test status
Simulation time 45117306431 ps
CPU time 1542.18 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:36:28 PM PDT 24
Peak memory 273712 kb
Host smart-543a8114-d9c1-4536-bcd1-42d38f7d758e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109313341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2109313341
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1054968832
Short name T641
Test name
Test status
Simulation time 11740686303 ps
CPU time 1188.03 seconds
Started Jun 26 07:10:46 PM PDT 24
Finished Jun 26 07:30:35 PM PDT 24
Peak memory 283204 kb
Host smart-3710bca3-9afd-42aa-9f4c-51890b201235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054968832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1054968832
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1363249596
Short name T314
Test name
Test status
Simulation time 13463519834 ps
CPU time 285.43 seconds
Started Jun 26 07:10:45 PM PDT 24
Finished Jun 26 07:15:32 PM PDT 24
Peak memory 255260 kb
Host smart-479f993c-e29e-4aa4-a6a9-e9d6e3ad7413
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363249596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1363249596
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3739757492
Short name T574
Test name
Test status
Simulation time 404828774 ps
CPU time 15.04 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:11:04 PM PDT 24
Peak memory 255060 kb
Host smart-e8138ce6-a39c-46b2-a95b-6a382c97fd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
57492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3739757492
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2910425462
Short name T565
Test name
Test status
Simulation time 2355998025 ps
CPU time 70.84 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:11:57 PM PDT 24
Peak memory 248700 kb
Host smart-5c76512a-f5ce-42bc-87f1-502a95dae95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29104
25462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2910425462
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3635865426
Short name T389
Test name
Test status
Simulation time 400002883 ps
CPU time 26.4 seconds
Started Jun 26 07:10:44 PM PDT 24
Finished Jun 26 07:11:12 PM PDT 24
Peak memory 256184 kb
Host smart-082ac55e-f0b3-420b-984d-f32bac18e0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36358
65426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3635865426
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1845424689
Short name T38
Test name
Test status
Simulation time 1950225184 ps
CPU time 20.48 seconds
Started Jun 26 07:10:45 PM PDT 24
Finished Jun 26 07:11:07 PM PDT 24
Peak memory 256732 kb
Host smart-4a5fda6a-a2a5-449c-b049-84bd3937ed9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18454
24689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1845424689
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.791855221
Short name T45
Test name
Test status
Simulation time 1655557768 ps
CPU time 157.46 seconds
Started Jun 26 07:10:49 PM PDT 24
Finished Jun 26 07:13:27 PM PDT 24
Peak memory 257536 kb
Host smart-acd48eb2-d72a-4189-8db1-c0e0833651b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791855221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.791855221
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2179045230
Short name T54
Test name
Test status
Simulation time 240362941326 ps
CPU time 3700.32 seconds
Started Jun 26 07:10:47 PM PDT 24
Finished Jun 26 08:12:30 PM PDT 24
Peak memory 331532 kb
Host smart-1b22b1cd-3ea8-4f01-b4f0-1d6ddc70f645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179045230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2179045230
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1078520345
Short name T531
Test name
Test status
Simulation time 105699900982 ps
CPU time 1477.54 seconds
Started Jun 26 07:10:56 PM PDT 24
Finished Jun 26 07:35:35 PM PDT 24
Peak memory 274024 kb
Host smart-d2b39f24-cc6e-4bc0-b8f9-522e81785f80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078520345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1078520345
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1250666535
Short name T425
Test name
Test status
Simulation time 11124040295 ps
CPU time 251.16 seconds
Started Jun 26 07:10:58 PM PDT 24
Finished Jun 26 07:15:11 PM PDT 24
Peak memory 257596 kb
Host smart-03aa6d6f-ffd8-4125-9ae1-f0e91f6dc92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
66535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1250666535
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.174068626
Short name T212
Test name
Test status
Simulation time 1799680036 ps
CPU time 14.74 seconds
Started Jun 26 07:10:45 PM PDT 24
Finished Jun 26 07:11:01 PM PDT 24
Peak memory 248876 kb
Host smart-a155d855-6ca8-4af6-b7e3-b1ff96bd9f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
8626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.174068626
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.377668440
Short name T282
Test name
Test status
Simulation time 31584107606 ps
CPU time 1724.31 seconds
Started Jun 26 07:10:58 PM PDT 24
Finished Jun 26 07:39:44 PM PDT 24
Peak memory 273956 kb
Host smart-bb9cab4c-db3c-47ac-8c04-da6d142d3c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377668440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.377668440
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.796880716
Short name T222
Test name
Test status
Simulation time 12097601306 ps
CPU time 1122.53 seconds
Started Jun 26 07:11:08 PM PDT 24
Finished Jun 26 07:29:52 PM PDT 24
Peak memory 282140 kb
Host smart-fc34ba7a-5bab-43cf-8a11-d58119d691c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796880716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.796880716
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.896560650
Short name T634
Test name
Test status
Simulation time 46324828375 ps
CPU time 294.4 seconds
Started Jun 26 07:10:54 PM PDT 24
Finished Jun 26 07:15:50 PM PDT 24
Peak memory 249420 kb
Host smart-43ab02ad-110e-4ea0-b766-a2f9ff0b01d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896560650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.896560650
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.509412812
Short name T417
Test name
Test status
Simulation time 1194877724 ps
CPU time 60.46 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:11:50 PM PDT 24
Peak memory 256500 kb
Host smart-4d6e89c0-8b14-4078-ae43-305fc290ad8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50941
2812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.509412812
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3063265685
Short name T99
Test name
Test status
Simulation time 539941186 ps
CPU time 10.03 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:10:59 PM PDT 24
Peak memory 254304 kb
Host smart-97d6883c-fbb1-4b64-b8e6-a9db9629619d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632
65685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3063265685
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2618750033
Short name T22
Test name
Test status
Simulation time 611738951 ps
CPU time 37.55 seconds
Started Jun 26 07:10:56 PM PDT 24
Finished Jun 26 07:11:34 PM PDT 24
Peak memory 256448 kb
Host smart-2b254a35-4245-4597-bf3f-1e97f29ca0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187
50033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2618750033
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.664794154
Short name T467
Test name
Test status
Simulation time 58684621 ps
CPU time 3.99 seconds
Started Jun 26 07:10:48 PM PDT 24
Finished Jun 26 07:10:53 PM PDT 24
Peak memory 252048 kb
Host smart-5feef1c5-4f70-47f1-a7e5-2f05d29ea6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66479
4154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.664794154
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.170679059
Short name T434
Test name
Test status
Simulation time 148393344548 ps
CPU time 794.4 seconds
Started Jun 26 07:10:58 PM PDT 24
Finished Jun 26 07:24:14 PM PDT 24
Peak memory 273932 kb
Host smart-65480fd6-7ff6-40b4-b6f6-be6d19f97912
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170679059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.170679059
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.426872046
Short name T515
Test name
Test status
Simulation time 36636513330 ps
CPU time 1117.88 seconds
Started Jun 26 07:10:57 PM PDT 24
Finished Jun 26 07:29:36 PM PDT 24
Peak memory 289136 kb
Host smart-59639f4c-ca96-4528-a40f-f2db6b5da99f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426872046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.426872046
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1403384051
Short name T493
Test name
Test status
Simulation time 932819390 ps
CPU time 56.03 seconds
Started Jun 26 07:11:01 PM PDT 24
Finished Jun 26 07:11:58 PM PDT 24
Peak memory 256828 kb
Host smart-a24cd464-5180-4ef6-a63a-e60eb9bfbdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033
84051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1403384051
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.727735176
Short name T628
Test name
Test status
Simulation time 620035355 ps
CPU time 14.95 seconds
Started Jun 26 07:10:57 PM PDT 24
Finished Jun 26 07:11:13 PM PDT 24
Peak memory 256936 kb
Host smart-8a48204b-d0c5-484a-a803-f4b64af1abd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72773
5176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.727735176
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.269616419
Short name T671
Test name
Test status
Simulation time 46231858505 ps
CPU time 2960.26 seconds
Started Jun 26 07:11:00 PM PDT 24
Finished Jun 26 08:00:22 PM PDT 24
Peak memory 289388 kb
Host smart-6db95f59-f2ec-476f-8b99-b81d5fa45e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269616419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.269616419
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1984396344
Short name T505
Test name
Test status
Simulation time 35623908861 ps
CPU time 1686.03 seconds
Started Jun 26 07:10:57 PM PDT 24
Finished Jun 26 07:39:04 PM PDT 24
Peak memory 290252 kb
Host smart-9b99a7c8-86a0-4ac1-87e4-153988bb22b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984396344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1984396344
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3320715265
Short name T295
Test name
Test status
Simulation time 12818178162 ps
CPU time 529.58 seconds
Started Jun 26 07:11:08 PM PDT 24
Finished Jun 26 07:19:59 PM PDT 24
Peak memory 256460 kb
Host smart-12d767f6-9a93-4d78-ae17-2f5dc7f40ed9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320715265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3320715265
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.280125635
Short name T260
Test name
Test status
Simulation time 440826206 ps
CPU time 43.47 seconds
Started Jun 26 07:10:58 PM PDT 24
Finished Jun 26 07:11:42 PM PDT 24
Peak memory 257468 kb
Host smart-8c194ba6-9c0f-4c69-a290-e7ad9bf51c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28012
5635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.280125635
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2570151633
Short name T679
Test name
Test status
Simulation time 259539662 ps
CPU time 34.16 seconds
Started Jun 26 07:10:58 PM PDT 24
Finished Jun 26 07:11:33 PM PDT 24
Peak memory 256824 kb
Host smart-ee99549a-193f-441f-a9aa-77e5ba7d7b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
51633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2570151633
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1932962584
Short name T257
Test name
Test status
Simulation time 742184703 ps
CPU time 50.97 seconds
Started Jun 26 07:10:57 PM PDT 24
Finished Jun 26 07:11:49 PM PDT 24
Peak memory 248588 kb
Host smart-fc3b18c0-5b7a-40b6-853f-a3eca11510b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19329
62584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1932962584
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4025379068
Short name T484
Test name
Test status
Simulation time 324622848 ps
CPU time 15.09 seconds
Started Jun 26 07:11:08 PM PDT 24
Finished Jun 26 07:11:25 PM PDT 24
Peak memory 249696 kb
Host smart-3ab3969d-38f9-4ecd-b452-0a9b10fce6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
79068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4025379068
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4158737902
Short name T245
Test name
Test status
Simulation time 57737058572 ps
CPU time 1533.31 seconds
Started Jun 26 07:11:08 PM PDT 24
Finished Jun 26 07:36:43 PM PDT 24
Peak memory 290004 kb
Host smart-222d31e0-b38b-4a9c-b3e7-3a2f30b9e3e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158737902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4158737902
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1693722049
Short name T615
Test name
Test status
Simulation time 37867580197 ps
CPU time 2710.73 seconds
Started Jun 26 07:11:14 PM PDT 24
Finished Jun 26 07:56:26 PM PDT 24
Peak memory 286484 kb
Host smart-672de652-90a3-4828-a310-0f6ee6c38553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693722049 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1693722049
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3414870837
Short name T516
Test name
Test status
Simulation time 16105958190 ps
CPU time 809.81 seconds
Started Jun 26 07:11:13 PM PDT 24
Finished Jun 26 07:24:44 PM PDT 24
Peak memory 273964 kb
Host smart-7c692a2b-0ba8-4200-b99c-8bf637276574
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414870837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3414870837
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3389163176
Short name T371
Test name
Test status
Simulation time 1817943054 ps
CPU time 36.27 seconds
Started Jun 26 07:11:24 PM PDT 24
Finished Jun 26 07:12:01 PM PDT 24
Peak memory 256668 kb
Host smart-02ab3db8-d722-4c5e-9514-68d48ded05dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891
63176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3389163176
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3172707960
Short name T251
Test name
Test status
Simulation time 2286225322 ps
CPU time 28.57 seconds
Started Jun 26 07:11:14 PM PDT 24
Finished Jun 26 07:11:43 PM PDT 24
Peak memory 248880 kb
Host smart-14d53a24-6f24-4f27-a1a0-e297a80f4e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31727
07960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3172707960
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3414552153
Short name T556
Test name
Test status
Simulation time 565093730488 ps
CPU time 3075.11 seconds
Started Jun 26 07:11:25 PM PDT 24
Finished Jun 26 08:02:41 PM PDT 24
Peak memory 288584 kb
Host smart-01364134-8566-476d-a4cc-8fea38f879eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414552153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3414552153
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1622252812
Short name T665
Test name
Test status
Simulation time 90777663851 ps
CPU time 2035.85 seconds
Started Jun 26 07:11:13 PM PDT 24
Finished Jun 26 07:45:11 PM PDT 24
Peak memory 286212 kb
Host smart-e1f1d7f0-903b-4599-a12d-47a7c99bfc19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622252812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1622252812
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2669707594
Short name T291
Test name
Test status
Simulation time 37932156720 ps
CPU time 280.95 seconds
Started Jun 26 07:11:24 PM PDT 24
Finished Jun 26 07:16:06 PM PDT 24
Peak memory 249184 kb
Host smart-059b6644-136c-4248-8d6e-6593a35b24a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669707594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2669707594
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.289587936
Short name T677
Test name
Test status
Simulation time 1935578077 ps
CPU time 51.24 seconds
Started Jun 26 07:11:25 PM PDT 24
Finished Jun 26 07:12:17 PM PDT 24
Peak memory 256516 kb
Host smart-33262d40-cd08-4d4c-be82-69030364e9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
7936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.289587936
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3584106053
Short name T450
Test name
Test status
Simulation time 3748412511 ps
CPU time 59.76 seconds
Started Jun 26 07:11:11 PM PDT 24
Finished Jun 26 07:12:12 PM PDT 24
Peak memory 249244 kb
Host smart-f06a37d8-ac5d-4c8a-a8fe-55682848d4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
06053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3584106053
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3852355414
Short name T521
Test name
Test status
Simulation time 6336619477 ps
CPU time 31.22 seconds
Started Jun 26 07:11:12 PM PDT 24
Finished Jun 26 07:11:44 PM PDT 24
Peak memory 249040 kb
Host smart-cf3c5054-ccbf-4604-ad1e-81ab1e3e88d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
55414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3852355414
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1558832532
Short name T407
Test name
Test status
Simulation time 1515587513 ps
CPU time 53.07 seconds
Started Jun 26 07:11:24 PM PDT 24
Finished Jun 26 07:12:18 PM PDT 24
Peak memory 257476 kb
Host smart-bfd9a6f1-4c39-4c59-98fd-fc54725ae273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15588
32532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1558832532
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.852789441
Short name T537
Test name
Test status
Simulation time 61156677978 ps
CPU time 1871.88 seconds
Started Jun 26 07:11:12 PM PDT 24
Finished Jun 26 07:42:25 PM PDT 24
Peak memory 287840 kb
Host smart-edb0b423-a854-4ef8-a031-077218bb5a82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852789441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.852789441
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.811496396
Short name T207
Test name
Test status
Simulation time 131060170 ps
CPU time 3.77 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:06:38 PM PDT 24
Peak memory 249580 kb
Host smart-55a721e3-56bd-4909-9a7f-93955d736c02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=811496396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.811496396
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2536855107
Short name T422
Test name
Test status
Simulation time 202698269036 ps
CPU time 2907.4 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:54:57 PM PDT 24
Peak memory 289900 kb
Host smart-7192be3b-f812-40cc-b084-9c4441de3b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536855107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2536855107
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3018258221
Short name T478
Test name
Test status
Simulation time 585646206 ps
CPU time 9.21 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:06:43 PM PDT 24
Peak memory 249268 kb
Host smart-cd3620a5-3899-4087-8429-e8c7a626859f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3018258221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3018258221
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1392508670
Short name T23
Test name
Test status
Simulation time 10320702419 ps
CPU time 196.93 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:09:46 PM PDT 24
Peak memory 257696 kb
Host smart-fe45100a-1997-4fa2-8511-4cc2239d2297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13925
08670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1392508670
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1612440205
Short name T650
Test name
Test status
Simulation time 82161388 ps
CPU time 2.89 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:06:36 PM PDT 24
Peak memory 241148 kb
Host smart-582c23c0-5152-4c03-875f-fc4f37bc0161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124
40205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1612440205
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.120297770
Short name T330
Test name
Test status
Simulation time 32134448429 ps
CPU time 783.63 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:19:37 PM PDT 24
Peak memory 265784 kb
Host smart-869d7c75-66bc-492d-a534-99e92d2ab2a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120297770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.120297770
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1164873764
Short name T458
Test name
Test status
Simulation time 15978071430 ps
CPU time 1257.39 seconds
Started Jun 26 07:06:30 PM PDT 24
Finished Jun 26 07:27:29 PM PDT 24
Peak memory 273732 kb
Host smart-204947be-1871-41cb-86f5-1dc5b1a49d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164873764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1164873764
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3378766859
Short name T317
Test name
Test status
Simulation time 9451249724 ps
CPU time 390.31 seconds
Started Jun 26 07:06:27 PM PDT 24
Finished Jun 26 07:12:58 PM PDT 24
Peak memory 256204 kb
Host smart-df7c9d6f-fd2b-43e0-92c9-aed7b9c68a6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378766859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3378766859
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.446066886
Short name T617
Test name
Test status
Simulation time 203179189 ps
CPU time 15.57 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:06:48 PM PDT 24
Peak memory 249352 kb
Host smart-fc7083d1-2e6b-41b1-b93f-6f62cd0a0fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44606
6886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.446066886
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3652600311
Short name T443
Test name
Test status
Simulation time 1425322974 ps
CPU time 29.92 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:07:01 PM PDT 24
Peak memory 257036 kb
Host smart-592d9909-e0b2-410d-9f3d-14b0d4306e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526
00311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3652600311
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3739322641
Short name T252
Test name
Test status
Simulation time 3982984970 ps
CPU time 54.72 seconds
Started Jun 26 07:06:36 PM PDT 24
Finished Jun 26 07:07:32 PM PDT 24
Peak memory 257568 kb
Host smart-13332a10-27c5-4321-bea8-8fed4c76da31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
22641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3739322641
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.87539238
Short name T378
Test name
Test status
Simulation time 691930940 ps
CPU time 42.73 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:07:16 PM PDT 24
Peak memory 256472 kb
Host smart-1cce4b6a-6130-41a4-b1e9-968e4f04af83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87539
238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.87539238
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2256163909
Short name T238
Test name
Test status
Simulation time 107615929086 ps
CPU time 1864.13 seconds
Started Jun 26 07:06:32 PM PDT 24
Finished Jun 26 07:37:38 PM PDT 24
Peak memory 274036 kb
Host smart-b3817b88-4512-4f85-9791-252066b9a95a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256163909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2256163909
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1005642982
Short name T194
Test name
Test status
Simulation time 45094993 ps
CPU time 4.02 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:06:38 PM PDT 24
Peak memory 249612 kb
Host smart-2265e9e4-8585-4f7f-8c7d-9f3a1fb82071
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005642982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1005642982
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2393609659
Short name T405
Test name
Test status
Simulation time 98368901291 ps
CPU time 1674.72 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:34:24 PM PDT 24
Peak memory 273708 kb
Host smart-281ea0f4-6f46-47c5-8d62-d75a7678b520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393609659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2393609659
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3444768000
Short name T414
Test name
Test status
Simulation time 3677730503 ps
CPU time 38.95 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:07:13 PM PDT 24
Peak memory 249316 kb
Host smart-5be7c001-f360-46ea-8e0a-834c6c8f472c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3444768000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3444768000
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3176047111
Short name T678
Test name
Test status
Simulation time 8373257553 ps
CPU time 173.65 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:09:25 PM PDT 24
Peak memory 257604 kb
Host smart-03a1ada2-a9b5-44f5-b81a-67593b9f99b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
47111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3176047111
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.676302809
Short name T551
Test name
Test status
Simulation time 368430440 ps
CPU time 6.71 seconds
Started Jun 26 07:06:25 PM PDT 24
Finished Jun 26 07:06:33 PM PDT 24
Peak memory 249856 kb
Host smart-0a70384c-24eb-41ab-ab8e-88233cbc7f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67630
2809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.676302809
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3560791204
Short name T304
Test name
Test status
Simulation time 73838575550 ps
CPU time 1737.24 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:35:26 PM PDT 24
Peak memory 289788 kb
Host smart-548d8619-a7e1-489c-85d3-765bac958975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560791204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3560791204
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.720422049
Short name T606
Test name
Test status
Simulation time 51716399634 ps
CPU time 3449.26 seconds
Started Jun 26 07:06:27 PM PDT 24
Finished Jun 26 08:03:57 PM PDT 24
Peak memory 290356 kb
Host smart-31bae7d4-fe52-4f16-bb41-a4340a55e9aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720422049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.720422049
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2519079374
Short name T667
Test name
Test status
Simulation time 4401965786 ps
CPU time 185.41 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:09:37 PM PDT 24
Peak memory 255592 kb
Host smart-77f13899-c731-483e-8b08-438a71428006
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519079374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2519079374
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3457520091
Short name T533
Test name
Test status
Simulation time 54160711 ps
CPU time 8.5 seconds
Started Jun 26 07:06:29 PM PDT 24
Finished Jun 26 07:06:39 PM PDT 24
Peak memory 249348 kb
Host smart-a9a990ce-9797-4f49-865c-a1b9bb58789c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575
20091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3457520091
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.80791602
Short name T512
Test name
Test status
Simulation time 174620887 ps
CPU time 10.79 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:06:44 PM PDT 24
Peak memory 249272 kb
Host smart-5a6fd0d5-cb27-4577-9432-caa43031496b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80791
602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.80791602
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1570054482
Short name T670
Test name
Test status
Simulation time 187057536 ps
CPU time 22.49 seconds
Started Jun 26 07:06:33 PM PDT 24
Finished Jun 26 07:06:57 PM PDT 24
Peak memory 257452 kb
Host smart-6aa817be-3df8-4dae-bf95-00141c53089d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
54482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1570054482
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2696113347
Short name T401
Test name
Test status
Simulation time 105897065 ps
CPU time 7.87 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:06:37 PM PDT 24
Peak memory 252252 kb
Host smart-0b972c4e-850f-4678-9da4-7f7df98de663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
13347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2696113347
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4256838309
Short name T518
Test name
Test status
Simulation time 35386523384 ps
CPU time 534.77 seconds
Started Jun 26 07:06:31 PM PDT 24
Finished Jun 26 07:15:28 PM PDT 24
Peak memory 257652 kb
Host smart-59262b00-a44f-4503-956d-99c5a04015ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256838309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4256838309
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2453161590
Short name T208
Test name
Test status
Simulation time 55069003 ps
CPU time 4.61 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:06:51 PM PDT 24
Peak memory 249556 kb
Host smart-6e7fa47a-509a-41e0-a8da-45a3d9590d2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453161590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2453161590
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3928582820
Short name T601
Test name
Test status
Simulation time 64243935831 ps
CPU time 2438.3 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:47:24 PM PDT 24
Peak memory 288900 kb
Host smart-0a4efbc6-b38e-4f07-be92-6965a2c6a369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928582820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3928582820
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2772519877
Short name T220
Test name
Test status
Simulation time 277884627 ps
CPU time 9.16 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:06:55 PM PDT 24
Peak memory 249320 kb
Host smart-88a1c365-d3b2-4862-b9d7-86bb60059db3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2772519877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2772519877
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2182424794
Short name T681
Test name
Test status
Simulation time 1729275101 ps
CPU time 76.9 seconds
Started Jun 26 07:06:50 PM PDT 24
Finished Jun 26 07:08:07 PM PDT 24
Peak memory 257056 kb
Host smart-2f8bac8a-f6e3-404c-8090-097c4cd56db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
24794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2182424794
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2330442350
Short name T470
Test name
Test status
Simulation time 180873943 ps
CPU time 16.88 seconds
Started Jun 26 07:06:27 PM PDT 24
Finished Jun 26 07:06:45 PM PDT 24
Peak memory 248868 kb
Host smart-2d923cc7-6d3d-4b7d-8b2e-aa9fdef0b4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23304
42350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2330442350
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3169329929
Short name T475
Test name
Test status
Simulation time 65129978028 ps
CPU time 1421.66 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:30:27 PM PDT 24
Peak memory 284796 kb
Host smart-242daa33-105e-406e-a22a-94b0e0123b38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169329929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3169329929
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1426658572
Short name T586
Test name
Test status
Simulation time 304632433485 ps
CPU time 2785.06 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:53:10 PM PDT 24
Peak memory 290264 kb
Host smart-3f8bd3ad-a27a-49dd-8e73-2b6d3cab53e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426658572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1426658572
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2434420072
Short name T233
Test name
Test status
Simulation time 51627674678 ps
CPU time 529.22 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:15:36 PM PDT 24
Peak memory 255668 kb
Host smart-02691892-2d46-4dca-b095-cb1a635ecff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434420072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2434420072
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.519242189
Short name T652
Test name
Test status
Simulation time 1514442456 ps
CPU time 12.11 seconds
Started Jun 26 07:06:30 PM PDT 24
Finished Jun 26 07:06:44 PM PDT 24
Peak memory 249360 kb
Host smart-8184a084-ffe2-4ae8-acdd-031df84f78a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51924
2189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.519242189
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2323559199
Short name T454
Test name
Test status
Simulation time 2500524197 ps
CPU time 50.67 seconds
Started Jun 26 07:06:32 PM PDT 24
Finished Jun 26 07:07:24 PM PDT 24
Peak memory 257100 kb
Host smart-2203960a-0bc6-4ed1-b23b-3a2d995ea018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235
59199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2323559199
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.65592321
Short name T535
Test name
Test status
Simulation time 489849558 ps
CPU time 36.64 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:07:21 PM PDT 24
Peak memory 249280 kb
Host smart-4b729b83-706c-4666-a0f8-bf8e3dc4e2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65592
321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.65592321
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4052896810
Short name T83
Test name
Test status
Simulation time 1671219382 ps
CPU time 35.92 seconds
Started Jun 26 07:06:28 PM PDT 24
Finished Jun 26 07:07:06 PM PDT 24
Peak memory 249776 kb
Host smart-79bdbe54-a58e-4705-8ecd-7c5c9e3019ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
96810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4052896810
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.852261082
Short name T63
Test name
Test status
Simulation time 69602914691 ps
CPU time 2346.04 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:45:53 PM PDT 24
Peak memory 288888 kb
Host smart-191729b1-25e6-4445-9bd7-b78c02caa96b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852261082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.852261082
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2214690045
Short name T193
Test name
Test status
Simulation time 18050948 ps
CPU time 2.84 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:06:50 PM PDT 24
Peak memory 249616 kb
Host smart-ee8f767e-0c31-43a9-87d4-fba410607b44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2214690045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2214690045
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2311471424
Short name T381
Test name
Test status
Simulation time 12291097729 ps
CPU time 1444.94 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:30:50 PM PDT 24
Peak memory 289496 kb
Host smart-c32a04c2-6479-4ab4-8426-d999eb8e8802
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311471424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2311471424
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.30876286
Short name T542
Test name
Test status
Simulation time 1339107447 ps
CPU time 18.36 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:07:03 PM PDT 24
Peak memory 249320 kb
Host smart-4c13dcec-48c1-4a44-86cc-54b5e40fcadd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=30876286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.30876286
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2206886949
Short name T275
Test name
Test status
Simulation time 2449642077 ps
CPU time 54.88 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:07:42 PM PDT 24
Peak memory 257120 kb
Host smart-7614096a-290f-4969-80eb-ba22010e1c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22068
86949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2206886949
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1795407970
Short name T653
Test name
Test status
Simulation time 668475466 ps
CPU time 45.25 seconds
Started Jun 26 07:06:42 PM PDT 24
Finished Jun 26 07:07:28 PM PDT 24
Peak memory 249268 kb
Host smart-a2b6cafc-197c-493c-ad0a-f7f0c5b4e737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
07970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1795407970
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2771938369
Short name T465
Test name
Test status
Simulation time 34553276355 ps
CPU time 1610.2 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:33:37 PM PDT 24
Peak memory 290100 kb
Host smart-7178eca6-1381-4774-bd95-848cf6b5ac5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771938369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2771938369
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2442837975
Short name T636
Test name
Test status
Simulation time 20334026881 ps
CPU time 1817.91 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:37:06 PM PDT 24
Peak memory 290556 kb
Host smart-16d6dcfc-979a-47ac-874f-4b9d6a6f1fb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442837975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2442837975
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3607150648
Short name T269
Test name
Test status
Simulation time 19716276017 ps
CPU time 256.97 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:11:04 PM PDT 24
Peak memory 249404 kb
Host smart-5581b6ba-8517-4e25-b723-d7ca393deae7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607150648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3607150648
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.905283451
Short name T664
Test name
Test status
Simulation time 46378973 ps
CPU time 4.72 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:06:50 PM PDT 24
Peak memory 241016 kb
Host smart-d78932ed-a071-4e3c-b0fd-0086c38753ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90528
3451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.905283451
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2264694707
Short name T631
Test name
Test status
Simulation time 371485979 ps
CPU time 15.67 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:07:02 PM PDT 24
Peak memory 256880 kb
Host smart-71482226-05ca-4cb7-893a-dcc256f4b43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
94707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2264694707
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3652376965
Short name T369
Test name
Test status
Simulation time 1278179705 ps
CPU time 17.79 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:07:03 PM PDT 24
Peak memory 249004 kb
Host smart-58329e95-8f63-4d82-9d54-3c7a0883c499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
76965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3652376965
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1046588026
Short name T26
Test name
Test status
Simulation time 471069404 ps
CPU time 28.26 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:07:13 PM PDT 24
Peak memory 257460 kb
Host smart-55aa3638-b6c0-4d74-bcaf-1cf6190c44e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
88026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1046588026
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4117223580
Short name T201
Test name
Test status
Simulation time 95504996 ps
CPU time 4.28 seconds
Started Jun 26 07:07:05 PM PDT 24
Finished Jun 26 07:07:11 PM PDT 24
Peak memory 249580 kb
Host smart-fdb1859b-9ae4-4ba6-a477-7b885d7207c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4117223580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4117223580
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3355046919
Short name T536
Test name
Test status
Simulation time 64667081602 ps
CPU time 1603.05 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:33:29 PM PDT 24
Peak memory 289644 kb
Host smart-f39dd93c-36f5-492b-81ef-0aefb7746acc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355046919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3355046919
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.58845912
Short name T654
Test name
Test status
Simulation time 170511380 ps
CPU time 10.45 seconds
Started Jun 26 07:07:02 PM PDT 24
Finished Jun 26 07:07:14 PM PDT 24
Peak memory 249320 kb
Host smart-9c36f510-8a65-47b3-9a3c-dfe400fb5eed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=58845912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.58845912
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4270018060
Short name T509
Test name
Test status
Simulation time 11675093266 ps
CPU time 140.75 seconds
Started Jun 26 07:06:47 PM PDT 24
Finished Jun 26 07:09:09 PM PDT 24
Peak memory 256776 kb
Host smart-6526eb34-765c-4215-98ca-3732673de483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
18060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4270018060
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3284034866
Short name T64
Test name
Test status
Simulation time 294058978 ps
CPU time 21.14 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:07:09 PM PDT 24
Peak memory 257656 kb
Host smart-c5cf753d-4c33-4cd2-877b-2176bfc1ab3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
34866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3284034866
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.513822832
Short name T585
Test name
Test status
Simulation time 15114274058 ps
CPU time 1239.76 seconds
Started Jun 26 07:06:45 PM PDT 24
Finished Jun 26 07:27:27 PM PDT 24
Peak memory 290360 kb
Host smart-1c66a1bb-227f-445b-b461-bb74b93e3e06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513822832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.513822832
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3978440309
Short name T388
Test name
Test status
Simulation time 48127427735 ps
CPU time 2185.24 seconds
Started Jun 26 07:06:49 PM PDT 24
Finished Jun 26 07:43:15 PM PDT 24
Peak memory 287204 kb
Host smart-a7b8169b-190c-46fc-b85c-f2073f01c8f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978440309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3978440309
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1147669931
Short name T293
Test name
Test status
Simulation time 105081951210 ps
CPU time 235.66 seconds
Started Jun 26 07:06:49 PM PDT 24
Finished Jun 26 07:10:46 PM PDT 24
Peak memory 257412 kb
Host smart-b594f689-e700-43e8-aeb1-8d2b29196017
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147669931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1147669931
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.793917856
Short name T689
Test name
Test status
Simulation time 116861036 ps
CPU time 10.89 seconds
Started Jun 26 07:06:49 PM PDT 24
Finished Jun 26 07:07:01 PM PDT 24
Peak memory 257464 kb
Host smart-3c656fd6-0350-4634-ac5f-3163072a1878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79391
7856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.793917856
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1247642032
Short name T492
Test name
Test status
Simulation time 803918175 ps
CPU time 51.9 seconds
Started Jun 26 07:06:44 PM PDT 24
Finished Jun 26 07:07:37 PM PDT 24
Peak memory 249332 kb
Host smart-1e2fff03-bc32-48e9-bb46-9e6fd439465b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
42032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1247642032
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2680368966
Short name T583
Test name
Test status
Simulation time 163591884 ps
CPU time 3.74 seconds
Started Jun 26 07:06:46 PM PDT 24
Finished Jun 26 07:06:51 PM PDT 24
Peak memory 240304 kb
Host smart-ba42666a-4c16-4eb6-ac38-40ef8b8f786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
68966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2680368966
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.504899708
Short name T430
Test name
Test status
Simulation time 284627353 ps
CPU time 8.26 seconds
Started Jun 26 07:06:43 PM PDT 24
Finished Jun 26 07:06:54 PM PDT 24
Peak memory 249320 kb
Host smart-77b0b6fa-8a79-4d61-a35f-dc19137d9141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50489
9708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.504899708
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3182069449
Short name T438
Test name
Test status
Simulation time 7593862418 ps
CPU time 807.46 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 07:20:33 PM PDT 24
Peak memory 273924 kb
Host smart-2be4086a-9cb2-453e-8d62-aa4d1b058baf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182069449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3182069449
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2210162924
Short name T182
Test name
Test status
Simulation time 188507723835 ps
CPU time 5710.38 seconds
Started Jun 26 07:07:04 PM PDT 24
Finished Jun 26 08:42:17 PM PDT 24
Peak memory 370736 kb
Host smart-ffc562c2-2cfb-448d-bd5c-076649b92c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210162924 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2210162924
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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