Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	66367	1			T2	5		T5	13		T6	94
class_i[0x1]	60485	1			T2	5694		T5	20		T9	3
class_i[0x2]	93612	1			T5	3650		T9	2		T18	4576
class_i[0x3]	40065	1			T5	5		T6	10		T10	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61372	1			T2	1232		T5	849		T6	38
alert[0x1]	68918	1			T2	1818		T5	821		T6	24
alert[0x2]	66201	1			T2	1335		T5	1266		T6	31
alert[0x3]	64038	1			T2	1314		T5	752		T6	11

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

260258

1

T2

5699

T5

3688

T6

104

esc_ping_fail

271

1

T9

7

T10

2

T11

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61297	1			T2	1232		T5	849		T6	38
esc_integrity_fail	alert[0x1]	68857	1			T2	1818		T5	821		T6	24
esc_integrity_fail	alert[0x2]	66126	1			T2	1335		T5	1266		T6	31
esc_integrity_fail	alert[0x3]	63978	1			T2	1314		T5	752		T6	11
esc_ping_fail	alert[0x0]	75	1			T9	2		T10	1		T11	2
esc_ping_fail	alert[0x1]	61	1			T9	1		T11	1		T29	2
esc_ping_fail	alert[0x2]	75	1			T9	2		T10	1		T11	2
esc_ping_fail	alert[0x3]	60	1			T9	2		T11	2		T29	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	66307	1			T2	5		T5	13		T6	94
esc_integrity_fail	class_i[0x1]	60440	1			T2	5694		T5	20		T9	2
esc_integrity_fail	class_i[0x2]	93540	1			T5	3650		T18	4576		T30	2121
esc_integrity_fail	class_i[0x3]	39971	1			T5	5		T6	10		T30	3
esc_ping_fail	class_i[0x0]	60	1			T9	4		T29	8		T234	2
esc_ping_fail	class_i[0x1]	45	1			T9	1		T11	6		T63	1
esc_ping_fail	class_i[0x2]	72	1			T9	2		T10	1		T234	3
esc_ping_fail	class_i[0x3]	94	1			T10	1		T11	1		T63	3