Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	617447457	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	617447457	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	617447457	617303461	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	617447457	617303461	0	0
tb.dut.EdnKnownO_A	0	0	617447457	617303461	0	0
tb.dut.EscPKnownO_A	0	0	617447457	617303461	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	617447457	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	617447457	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	617447457	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	617447457	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	617447457	60	0	0
tb.dut.IrqAKnownO_A	0	0	617447457	617303461	0	0
tb.dut.IrqBKnownO_A	0	0	617447457	617303461	0	0
tb.dut.IrqCKnownO_A	0	0	617447457	617303461	0	0
tb.dut.IrqDKnownO_A	0	0	617447457	617303461	0	0
tb.dut.TlAReadyKnownO_A	0	0	617447457	617303461	0	0
tb.dut.TlDValidKnownO_A	0	0	617447457	617303461	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	638101479	2524379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	638101479	6934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	638101479	7171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	638101479	6991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	638101479	6863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	638101479	6771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	638101479	6709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	638101479	6967	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	638101479	6709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	638101479	6596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	638101479	6948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	638101479	6580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	638101479	6873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	638101479	7019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	638101479	6950	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	638101479	6837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	638101479	6870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	638101479	6833	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	638101479	6921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	638101479	6699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	638101479	6890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	638101479	6913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	638101479	6737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	638101479	7058	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	638101479	6837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	638101479	7038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	638101479	7032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	638101479	6724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	638101479	7074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	638101479	7090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	638101479	6889	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	638101479	6855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	638101479	6843	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	638101479	6826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	638101479	6973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	638101479	6836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	638101479	6688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	638101479	7115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	638101479	6955	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	638101479	7011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	638101479	6744	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	638101479	7020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	638101479	6710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	638101479	6953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	638101479	6712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	638101479	6985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	638101479	6777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	638101479	6764	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	638101479	7049	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	638101479	6801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	638101479	6872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	638101479	6766	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	638101479	6893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	638101479	6856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	638101479	6875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	638101479	6915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	638101479	6794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	638101479	6823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	638101479	6816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	638101479	6969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	638101479	6752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	638101479	6736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	638101479	6911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	638101479	6818	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	638101479	6640	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	638101479	6741	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	638101479	7037	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	638101479	6822	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	638101479	6793	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	638101479	6822	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	638101479	13372	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	638101479	6976	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	638101479	6779	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	638101479	6952	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	638101479	6703	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	638101479	7081	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	638101479	6907	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	638101479	6973	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	638101479	7104	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	617447457	2250	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	617447457	189283	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	617447457	320326875	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	617447457	204	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	617447457	813	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	617447457	55	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	617447457	418	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	617321313	228155614	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	617447457	915	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	617447457	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	617447457	865	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	617447457	852	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	617447457	1041	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	617447457	101410	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	617447457	918	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	617447457	67	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	617447457	1008	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	617447457	828	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	617320191	617252920	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	617447457	617303461	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	617447457	3056	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	617447457	177890	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	617447457	329538956	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	617447457	206	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	617447457	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	617447457	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	617447457	290	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	617321313	247940431	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	617447457	622	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	617447457	603	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	617447457	592	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	617447457	580	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	617447457	1040	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	617447457	95213	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	617447457	959	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	617447457	56	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	617447457	1055	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	617447457	875	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	617320191	617252920	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	617447457	617303461	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	617447457	3491	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	617447457	176548	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	617447457	330616997	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	617447457	183	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	617447457	456	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	617447457	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	617447457	204	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	617321313	248336263	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	617447457	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	617447457	521	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	617447457	510	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	617447457	503	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	617447457	693	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	617447457	73840	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	617447457	605	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	617447457	65	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	617447457	1019	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	617447457	839	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	617320191	617252920	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	617447457	617303461	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	617447457	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	617447457	2469	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	617447457	197088	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	617447457	330924763	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	617447457	216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	617447457	483	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	617447457	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	617447457	204	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	617321313	265306610	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	617447457	551	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	617447457	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	617447457	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	617447457	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	617447457	822	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	617447457	78614	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	617447457	751	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	617447457	52	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	617447457	1111	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	617447457	931	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	617320191	617252920	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	617447457	617303461	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	638101479	121522647	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	638101479	637484655	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	638101479	637484655	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	638101479	162101058	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	638101479	637484655	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	638101479	637484655	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	827	827	0	0
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