Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	168	1			T2	1		T5	9		T8	1
index[0x1]	171	1			T2	1		T3	1		T5	6
index[0x2]	161	1			T2	1		T5	1		T6	1
index[0x3]	169	1			T3	1		T20	1		T6	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	218	1			T3	2		T5	10		T15	1
lens_less_than_1000[1]	116	1			T2	1		T5	4		T8	1
lens_less_than_1000[2]	93	1			T20	1		T5	2		T6	2
lens_less_than_1000[3]	63	1			T6	1		T38	1		T30	1
lens_less_than_1000[4]	46	1			T30	1		T28	1		T66	2
lens_less_than_1000[5]	52	1			T21	1		T27	1		T72	2
lens_less_than_1000[6]	33	1			T2	1		T28	2		T307	1
lens_less_than_1000[7]	22	1			T2	1		T15	1		T45	1
lens_less_than_1000[8]	10	1			T115	1		T32	1		T308	1
lens_less_than_1000[9]	7	1			T32	1		T49	1		T82	1
len_2	9	1			T32	1		T94	1		T109	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	53	1			T5	5		T70	1		T46	1
index[0x0]	lens_less_than_1000[1]	28	1			T5	4		T8	1		T82	6
index[0x0]	lens_less_than_1000[2]	18	1			T27	3		T272	1		T67	1
index[0x0]	lens_less_than_1000[3]	17	1			T296	1		T309	1		T198	1
index[0x0]	lens_less_than_1000[4]	16	1			T28	1		T66	2		T48	2
index[0x0]	lens_less_than_1000[5]	13	1			T32	1		T85	1		T110	1
index[0x0]	lens_less_than_1000[6]	11	1			T2	1		T48	2		T310	4
index[0x0]	lens_less_than_1000[7]	5	1			T45	1		T311	1		T312	1
index[0x0]	lens_less_than_1000[8]	2	1			T32	1		T308	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T313	1		-	-		-	-
index[0x0]	len_2	4	1			T94	1		T314	1		T262	1
index[0x1]	lens_less_than_1000[0]	56	1			T3	1		T5	5		T15	1
index[0x1]	lens_less_than_1000[1]	32	1			T64	1		T47	1		T275	1
index[0x1]	lens_less_than_1000[2]	17	1			T5	1		T57	1		T65	1
index[0x1]	lens_less_than_1000[3]	21	1			T38	1		T42	1		T78	1
index[0x1]	lens_less_than_1000[4]	12	1			T30	1		T44	1		T114	1
index[0x1]	lens_less_than_1000[5]	12	1			T94	1		T92	1		T315	1
index[0x1]	lens_less_than_1000[6]	9	1			T75	5		T316	1		T317	1
index[0x1]	lens_less_than_1000[7]	7	1			T2	1		T48	1		T318	1
index[0x1]	lens_less_than_1000[8]	2	1			T115	1		T319	1		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T320	1		-	-		-	-
index[0x1]	len_2	2	1			T321	1		T322	1		-	-
index[0x2]	lens_less_than_1000[0]	54	1			T39	1		T40	1		T27	1
index[0x2]	lens_less_than_1000[1]	35	1			T2	1		T9	1		T28	1
index[0x2]	lens_less_than_1000[2]	34	1			T5	1		T6	1		T65	1
index[0x2]	lens_less_than_1000[3]	11	1			T46	1		T106	1		T323	1
index[0x2]	lens_less_than_1000[4]	3	1			T324	1		T325	1		T26	1
index[0x2]	lens_less_than_1000[5]	5	1			T27	1		T48	1		T326	1
index[0x2]	lens_less_than_1000[6]	6	1			T28	1		T307	1		T327	1
index[0x2]	lens_less_than_1000[7]	5	1			T84	1		T299	1		T328	1
index[0x2]	lens_less_than_1000[8]	3	1			T107	3		-	-		-	-
index[0x2]	lens_less_than_1000[9]	3	1			T32	1		T82	1		T320	1
index[0x2]	len_2	2	1			T32	1		T329	1		-	-
index[0x3]	lens_less_than_1000[0]	55	1			T3	1		T272	1		T42	1
index[0x3]	lens_less_than_1000[1]	21	1			T103	1		T51	1		T330	1
index[0x3]	lens_less_than_1000[2]	24	1			T20	1		T6	1		T65	7
index[0x3]	lens_less_than_1000[3]	14	1			T6	1		T30	1		T45	1
index[0x3]	lens_less_than_1000[4]	15	1			T331	1		T110	1		T332	1
index[0x3]	lens_less_than_1000[5]	22	1			T21	1		T72	2		T32	1
index[0x3]	lens_less_than_1000[6]	7	1			T28	1		T32	1		T55	1
index[0x3]	lens_less_than_1000[7]	5	1			T15	1		T200	1		T328	1
index[0x3]	lens_less_than_1000[8]	3	1			T55	1		T107	2		-	-
index[0x3]	lens_less_than_1000[9]	2	1			T49	1		T313	1		-	-
index[0x3]	len_2	1	1			T109	1		-	-		-	-