Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	8	32	80.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	8	32	80.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	67	1			T18	1		T42	2		T61	1
class_index[0x1]	56	1			T2	1		T27	1		T42	3
class_index[0x2]	65	1			T8	1		T27	5		T28	1
class_index[0x3]	52	1			T20	1		T6	1		T15	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T20	1		T8	1		T15	1
intr_timeout_cnt[1]	62	1			T18	1		T27	1		T42	1
intr_timeout_cnt[2]	14	1			T2	1		T71	1		T75	1
intr_timeout_cnt[3]	13	1			T42	1		T71	1		T253	2
intr_timeout_cnt[4]	16	1			T6	1		T42	1		T94	1
intr_timeout_cnt[5]	17	1			T42	3		T51	1		T254	1
intr_timeout_cnt[6]	10	1			T28	1		T198	1		T94	1
intr_timeout_cnt[7]	8	1			T32	1		T94	1		T82	3
intr_timeout_cnt[8]	4	1			T94	1		T89	1		T255	1
intr_timeout_cnt[9]	3	1			T82	1		T256	2		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	8	32	80.00	8

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	3
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T42	1		T45	2		T72	2
class_index[0x0]	intr_timeout_cnt[1]	14	1			T18	1		T61	1		T70	1
class_index[0x0]	intr_timeout_cnt[2]	2	1			T75	1		T112	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	6	1			T253	2		T89	1		T257	2
class_index[0x0]	intr_timeout_cnt[4]	7	1			T42	1		T258	1		T259	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T92	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T32	1		T94	1		T260	1
class_index[0x0]	intr_timeout_cnt[9]	3	1			T82	1		T256	2		-	-
class_index[0x1]	intr_timeout_cnt[0]	19	1			T42	1		T45	1		T32	1
class_index[0x1]	intr_timeout_cnt[1]	21	1			T27	1		T42	1		T32	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T2	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	4	1			T42	1		T226	1		T261	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T83	1		T262	1		T263	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T254	1		T264	1		T55	2
class_index[0x1]	intr_timeout_cnt[6]	2	1			T226	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T94	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T8	1		T27	5		T28	1
class_index[0x2]	intr_timeout_cnt[1]	18	1			T102	1		T265	1		T266	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T51	1		T253	1		T229	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T71	1		T89	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T94	1		T262	2		T267	1
class_index[0x2]	intr_timeout_cnt[5]	8	1			T51	1		T92	5		T90	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T97	1		T268	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	20	1			T20	1		T15	1		T27	2
class_index[0x3]	intr_timeout_cnt[1]	9	1			T117	3		T46	1		T89	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T71	1		T269	1		T95	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T270	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T6	1		T95	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T42	3		T267	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T28	1		T198	1		T94	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T82	3		T110	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T89	1		T255	1		T271	1