Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336847	1			T1	25		T2	1766		T3	33
all_values[1]	336847	1			T1	25		T2	1766		T3	33
all_values[2]	336847	1			T1	25		T2	1766		T3	33
all_values[3]	336847	1			T1	25		T2	1766		T3	33

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

669896

1

T1

62

T2

3527

T3

62

auto[1]

677492

1

T1

38

T2

3537

T3

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

806950

1

T1

58

T2

3740

T3

70

auto[1]

540438

1

T1

42

T2

3324

T3

62

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97250	1			T1	5		T2	495		T3	9
all_values[0]	auto[0]	auto[1]	69197	1			T1	4		T2	417		T3	8
all_values[0]	auto[1]	auto[0]	100186	1			T1	8		T2	460		T3	8
all_values[0]	auto[1]	auto[1]	70214	1			T1	8		T2	394		T3	8
all_values[1]	auto[0]	auto[0]	99826	1			T1	17		T2	462		T3	5
all_values[1]	auto[0]	auto[1]	68374	1			T1	4		T2	460		T3	5
all_values[1]	auto[1]	auto[0]	100336	1			T1	2		T2	419		T3	14
all_values[1]	auto[1]	auto[1]	68311	1			T1	2		T2	425		T3	9
all_values[2]	auto[0]	auto[0]	101096	1			T1	9		T2	437		T3	9
all_values[2]	auto[0]	auto[1]	66535	1			T1	8		T2	386		T3	8
all_values[2]	auto[1]	auto[0]	102239	1			T1	4		T2	508		T3	8
all_values[2]	auto[1]	auto[1]	66977	1			T1	4		T2	435		T3	8
all_values[3]	auto[0]	auto[0]	102232	1			T1	8		T2	475		T3	9
all_values[3]	auto[0]	auto[1]	65386	1			T1	7		T2	395		T3	9
all_values[3]	auto[1]	auto[0]	103785	1			T1	5		T2	484		T3	8
all_values[3]	auto[1]	auto[1]	65444	1			T1	5		T2	412		T3	7