Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336847	1			T1	25		T2	1766		T3	33
all_pins[1]	336847	1			T1	25		T2	1766		T3	33
all_pins[2]	336847	1			T1	25		T2	1766		T3	33
all_pins[3]	336847	1			T1	25		T2	1766		T3	33

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1076442	1			T1	81		T2	5398		T3	100
values[0x1]	270946	1			T1	19		T2	1666		T3	32
transitions[0x0=>0x1]	180125	1			T1	13		T2	1041		T3	19
transitions[0x1=>0x0]	180374	1			T1	14		T2	1042		T3	19

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266633	1			T1	17		T2	1372		T3	25
all_pins[0]	values[0x1]	70214	1			T1	8		T2	394		T3	8
all_pins[0]	transitions[0x0=>0x1]	69539	1			T1	7		T2	391		T3	8
all_pins[0]	transitions[0x1=>0x0]	65018	1			T1	5		T2	410		T3	7
all_pins[1]	values[0x0]	268536	1			T1	23		T2	1341		T3	24
all_pins[1]	values[0x1]	68311	1			T1	2		T2	425		T3	9
all_pins[1]	transitions[0x0=>0x1]	37828	1			T2	231		T3	3		T4	167
all_pins[1]	transitions[0x1=>0x0]	39731	1			T1	6		T2	200		T3	2
all_pins[2]	values[0x0]	269870	1			T1	21		T2	1331		T3	25
all_pins[2]	values[0x1]	66977	1			T1	4		T2	435		T3	8
all_pins[2]	transitions[0x0=>0x1]	36819	1			T1	3		T2	219		T3	4
all_pins[2]	transitions[0x1=>0x0]	38153	1			T1	1		T2	209		T3	5
all_pins[3]	values[0x0]	271403	1			T1	20		T2	1354		T3	26
all_pins[3]	values[0x1]	65444	1			T1	5		T2	412		T3	7
all_pins[3]	transitions[0x0=>0x1]	35939	1			T1	3		T2	200		T3	4
all_pins[3]	transitions[0x1=>0x0]	37472	1			T1	2		T2	223		T3	5