Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T162	4		T163	4		T236	4
all_values[1]	281	1			T162	4		T163	4		T236	4
all_values[2]	281	1			T162	4		T163	4		T236	4
all_values[3]	281	1			T162	4		T163	4		T236	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627

1

T162

5

T163

11

T236

10

auto[1]

497

1

T162

11

T163

5

T236

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

478

1

T162

8

T163

10

T236

11

auto[1]

646

1

T162

8

T163

6

T236

5

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699

1

T162

11

T163

12

T236

12

auto[1]

425

1

T162

5

T163

4

T236

4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

72

1

T163

2

T236

1

T235

1

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T348

1

T349

1

T350

1

all_values[0]

auto[0]

auto[1]

auto[0]

62

1

T162

2

T163

2

T236

3

all_values[0]

auto[0]

auto[1]

auto[1]

27

1

T235

2

T249

1

T351

2

all_values[0]

auto[1]

auto[0]

auto[1]

53

1

T162

1

T235

2

T351

4

all_values[0]

auto[1]

auto[1]

auto[1]

43

1

T162

1

T235

2

T249

2

all_values[1]

auto[0]

auto[0]

auto[0]

62

1

T162

1

T163

1

T235

2

all_values[1]

auto[0]

auto[0]

auto[1]

39

1

T163

2

T235

2

T249

1

all_values[1]

auto[0]

auto[1]

auto[0]

51

1

T236

1

T235

1

T352

1

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T162

2

T249

2

T353

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T162

1

T163

1

T236

1

all_values[1]

auto[1]

auto[1]

auto[1]

42

1

T236

2

T249

1

T352

2

all_values[2]

auto[0]

auto[0]

auto[0]

79

1

T162

1

T163

2

T236

4

all_values[2]

auto[0]

auto[0]

auto[1]

27

1

T235

1

T249

1

T352

3

all_values[2]

auto[0]

auto[1]

auto[0]

53

1

T162

3

T163

1

T235

3

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T354

1

T355

1

T356

2

all_values[2]

auto[1]

auto[0]

auto[1]

46

1

T163

1

T235

2

T249

1

all_values[2]

auto[1]

auto[1]

auto[1]

51

1

T353

1

T348

3

T357

1

all_values[3]

auto[0]

auto[0]

auto[0]

58

1

T162

1

T163

1

T236

2

all_values[3]

auto[0]

auto[0]

auto[1]

31

1

T236

1

T249

1

T348

1

all_values[3]

auto[0]

auto[1]

auto[0]

41

1

T163

1

T249

1

T352

1

all_values[3]

auto[0]

auto[1]

auto[1]

26

1

T162

1

T235

2

T352

1

all_values[3]

auto[1]

auto[0]

auto[1]

71

1

T163

1

T236

1

T235

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T162

2

T163

1

T249

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal