Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86619	1			T2	1549		T15	323		T18	1020
accum_cnt_1000	233153	1			T2	2175		T4	1005		T5	829
accum_cnt_100	27791	1			T2	121		T3	4		T4	90
accum_cnt_50	75418	1			T2	1411		T3	34		T4	60
accum_cnt_10	181749	1			T1	17		T2	53		T3	33
accum_cnt_0	353338	1			T1	51		T2	23		T3	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	248957	1			T1	17		T2	1333		T3	26
class_index[0x1]	248957	1			T1	17		T2	1333		T3	26
class_index[0x2]	248957	1			T1	17		T2	1333		T3	26
class_index[0x3]	248957	1			T1	17		T2	1333		T3	26

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21475	1			T2	561		T15	259		T18	567
class_index[0x0]	accum_cnt_1000	56973	1			T2	696		T5	38		T6	144
class_index[0x0]	accum_cnt_100	7501	1			T2	32		T3	4		T5	43
class_index[0x0]	accum_cnt_50	17570	1			T2	28		T3	16		T5	45
class_index[0x0]	accum_cnt_10	56516	1			T2	14		T3	4		T7	12
class_index[0x0]	accum_cnt_0	81670	1			T1	17		T2	2		T3	2
class_index[0x1]	accum_cnt_2000	22962	1			T18	453		T19	179		T40	661
class_index[0x1]	accum_cnt_1000	59335	1			T2	1		T4	1005		T6	36
class_index[0x1]	accum_cnt_100	7209	1			T4	90		T5	11		T6	20
class_index[0x1]	accum_cnt_50	14871	1			T2	1318		T4	60		T5	27
class_index[0x1]	accum_cnt_10	44999	1			T2	7		T3	23		T4	31
class_index[0x1]	accum_cnt_0	89725	1			T1	17		T2	7		T3	3
class_index[0x2]	accum_cnt_2000	21221	1			T2	499		T31	40		T66	325
class_index[0x2]	accum_cnt_1000	58099	1			T2	726		T41	1164		T31	502
class_index[0x2]	accum_cnt_100	5692	1			T2	50		T15	6		T41	69
class_index[0x2]	accum_cnt_50	24860	1			T2	35		T5	7		T15	675
class_index[0x2]	accum_cnt_10	37956	1			T1	17		T2	15		T20	1
class_index[0x2]	accum_cnt_0	91582	1			T2	8		T3	26		T7	14
class_index[0x3]	accum_cnt_2000	20961	1			T2	489		T15	64		T40	589
class_index[0x3]	accum_cnt_1000	58746	1			T2	752		T5	791		T6	113
class_index[0x3]	accum_cnt_100	7389	1			T2	39		T5	47		T6	56
class_index[0x3]	accum_cnt_50	18117	1			T2	30		T3	18		T5	31
class_index[0x3]	accum_cnt_10	42278	1			T2	17		T3	6		T20	8
class_index[0x3]	accum_cnt_0	90361	1			T1	17		T2	6		T3	2