Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3164	1			T6	116		T99	1		T32	354
alert[0x1]	5394	1			T19	100		T27	143		T31	40
alert[0x2]	5516	1			T6	22		T29	1		T234	1
alert[0x3]	3687	1			T2	2		T27	2		T29	1
alert[0x4]	5897	1			T2	1		T5	14		T6	1
alert[0x5]	2988	1			T27	267		T31	1		T42	12
alert[0x6]	7457	1			T19	1332		T31	2		T234	1
alert[0x7]	11556	1			T6	9		T31	81		T63	1
alert[0x8]	2834	1			T4	1		T6	1		T29	1
alert[0x9]	2611	1			T30	2		T45	6		T49	71
alert[0xa]	5135	1			T9	1		T11	1		T29	1
alert[0xb]	3232	1			T5	5		T19	272		T234	1
alert[0xc]	8146	1			T5	2		T15	1		T19	43
alert[0xd]	5612	1			T6	1		T19	32		T27	22
alert[0xe]	8116	1			T6	19		T31	13		T234	1
alert[0xf]	5110	1			T19	749		T27	10		T31	790
alert[0x10]	5640	1			T6	71		T9	1		T31	163
alert[0x11]	2750	1			T19	111		T30	3		T67	3
alert[0x12]	6147	1			T5	3		T10	1		T31	118
alert[0x13]	6332	1			T9	1		T31	208		T44	2
alert[0x14]	4345	1			T9	2		T29	1		T67	2
alert[0x15]	13097	1			T5	1		T27	62		T238	2
alert[0x16]	11192	1			T15	13		T19	15		T11	1
alert[0x17]	7632	1			T5	6		T15	80		T31	7
alert[0x18]	7024	1			T5	1		T42	120		T67	4
alert[0x19]	5856	1			T6	8		T19	129		T40	17
alert[0x1a]	11314	1			T6	474		T19	1081		T31	244
alert[0x1b]	6568	1			T6	40		T31	15		T42	49
alert[0x1c]	9237	1			T6	158		T19	129		T10	1
alert[0x1d]	4034	1			T2	19		T6	9		T19	252
alert[0x1e]	3683	1			T234	1		T42	1		T43	2
alert[0x1f]	5970	1			T6	1		T19	8		T80	1
alert[0x20]	9626	1			T6	5		T19	11		T31	71
alert[0x21]	5364	1			T42	68		T32	128		T48	168
alert[0x22]	14726	1			T6	22		T19	357		T31	10
alert[0x23]	5430	1			T5	3		T19	15		T29	1
alert[0x24]	10793	1			T6	28		T29	1		T42	5
alert[0x25]	4222	1			T5	1		T6	33		T31	41
alert[0x26]	3042	1			T9	1		T19	74		T27	1
alert[0x27]	3077	1			T6	44		T9	1		T31	31
alert[0x28]	6461	1			T19	80		T40	1		T27	1
alert[0x29]	3015	1			T6	3		T19	102		T31	136
alert[0x2a]	11772	1			T6	66		T9	1		T31	102
alert[0x2b]	5073	1			T10	1		T27	7		T31	6
alert[0x2c]	5555	1			T6	7		T19	1144		T63	1
alert[0x2d]	10701	1			T42	887		T63	1		T115	21
alert[0x2e]	11524	1			T10	1		T31	9		T42	10
alert[0x2f]	4057	1			T19	78		T40	21		T234	1
alert[0x30]	6915	1			T6	46		T9	1		T19	63
alert[0x31]	6865	1			T5	4		T42	21		T28	3
alert[0x32]	4671	1			T31	15		T99	1		T115	19
alert[0x33]	8520	1			T6	234		T31	8		T29	1
alert[0x34]	8551	1			T27	20		T66	2		T70	1
alert[0x35]	4770	1			T9	1		T19	319		T63	2
alert[0x36]	3535	1			T234	1		T42	85		T63	1
alert[0x37]	14614	1			T5	1		T66	4		T115	16
alert[0x38]	4086	1			T6	9		T19	704		T31	13
alert[0x39]	9581	1			T6	29		T19	118		T27	8
alert[0x3a]	12624	1			T6	3		T29	1		T234	1
alert[0x3b]	3532	1			T5	1		T6	7		T9	1
alert[0x3c]	6767	1			T6	15		T9	4		T19	17
alert[0x3d]	5978	1			T19	53		T234	1		T42	7
alert[0x3e]	4241	1			T6	13		T19	57		T31	557
alert[0x3f]	7278	1			T5	2		T9	1		T19	136
alert[0x40]	2743	1			T31	15		T11	1		T42	31

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	116019	1			T5	5		T6	122		T15	20
class_i[0x1]	119877	1			T4	1		T5	1		T15	38
class_i[0x2]	93284	1			T2	19		T5	38		T6	1372
class_i[0x3]	97805	1			T2	3		T15	7		T9	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

426306

1

T2

22

T5

44

T6

1494

alert_ping_fail

679

1

T4

1

T9

16

T10

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3153	1			T6	116		T32	354		T51	400
alert_integrity_fail	alert[0x1]	5383	1			T19	100		T27	143		T31	40
alert_integrity_fail	alert[0x2]	5505	1			T6	22		T42	416		T48	223
alert_integrity_fail	alert[0x3]	3680	1			T2	2		T27	2		T42	15
alert_integrity_fail	alert[0x4]	5889	1			T2	1		T5	14		T6	1
alert_integrity_fail	alert[0x5]	2969	1			T27	267		T31	1		T42	12
alert_integrity_fail	alert[0x6]	7444	1			T19	1332		T31	2		T32	2
alert_integrity_fail	alert[0x7]	11544	1			T6	9		T31	81		T103	696
alert_integrity_fail	alert[0x8]	2818	1			T6	1		T42	20		T66	6
alert_integrity_fail	alert[0x9]	2600	1			T30	2		T45	6		T49	71
alert_integrity_fail	alert[0xa]	5120	1			T43	33		T103	467		T115	110
alert_integrity_fail	alert[0xb]	3220	1			T5	5		T19	272		T103	165
alert_integrity_fail	alert[0xc]	8134	1			T5	2		T15	1		T19	43
alert_integrity_fail	alert[0xd]	5602	1			T6	1		T19	32		T27	22
alert_integrity_fail	alert[0xe]	8113	1			T6	19		T31	13		T103	44
alert_integrity_fail	alert[0xf]	5100	1			T19	749		T27	10		T31	790
alert_integrity_fail	alert[0x10]	5631	1			T6	71		T31	163		T42	9
alert_integrity_fail	alert[0x11]	2744	1			T19	111		T30	3		T67	3
alert_integrity_fail	alert[0x12]	6141	1			T5	3		T31	118		T42	6
alert_integrity_fail	alert[0x13]	6318	1			T31	208		T44	2		T45	18
alert_integrity_fail	alert[0x14]	4326	1			T67	2		T103	34		T32	182
alert_integrity_fail	alert[0x15]	13089	1			T5	1		T27	62		T42	127
alert_integrity_fail	alert[0x16]	11183	1			T15	13		T19	15		T115	155
alert_integrity_fail	alert[0x17]	7623	1			T5	6		T15	80		T31	7
alert_integrity_fail	alert[0x18]	7013	1			T5	1		T42	120		T67	4
alert_integrity_fail	alert[0x19]	5846	1			T6	8		T19	129		T40	17
alert_integrity_fail	alert[0x1a]	11310	1			T6	474		T19	1081		T31	244
alert_integrity_fail	alert[0x1b]	6561	1			T6	40		T31	15		T42	49
alert_integrity_fail	alert[0x1c]	9228	1			T6	158		T19	129		T31	244
alert_integrity_fail	alert[0x1d]	4026	1			T2	19		T6	9		T19	252
alert_integrity_fail	alert[0x1e]	3670	1			T42	1		T43	2		T44	4
alert_integrity_fail	alert[0x1f]	5947	1			T6	1		T19	8		T27	5
alert_integrity_fail	alert[0x20]	9616	1			T6	5		T19	11		T31	71
alert_integrity_fail	alert[0x21]	5352	1			T42	68		T32	128		T48	168
alert_integrity_fail	alert[0x22]	14714	1			T6	22		T19	357		T31	10
alert_integrity_fail	alert[0x23]	5416	1			T5	3		T19	15		T42	32
alert_integrity_fail	alert[0x24]	10783	1			T6	28		T42	5		T67	6
alert_integrity_fail	alert[0x25]	4214	1			T5	1		T6	33		T31	41
alert_integrity_fail	alert[0x26]	3034	1			T19	74		T27	1		T42	18
alert_integrity_fail	alert[0x27]	3071	1			T6	44		T31	31		T115	921
alert_integrity_fail	alert[0x28]	6449	1			T19	80		T40	1		T27	1
alert_integrity_fail	alert[0x29]	3007	1			T6	3		T19	102		T31	136
alert_integrity_fail	alert[0x2a]	11758	1			T6	66		T31	102		T67	3
alert_integrity_fail	alert[0x2b]	5060	1			T27	7		T31	6		T70	219
alert_integrity_fail	alert[0x2c]	5542	1			T6	7		T19	1144		T78	147
alert_integrity_fail	alert[0x2d]	10687	1			T42	887		T115	21		T279	14
alert_integrity_fail	alert[0x2e]	11504	1			T31	9		T42	10		T70	8
alert_integrity_fail	alert[0x2f]	4050	1			T19	78		T40	21		T42	1
alert_integrity_fail	alert[0x30]	6901	1			T6	46		T19	63		T42	9
alert_integrity_fail	alert[0x31]	6858	1			T5	4		T42	21		T28	3
alert_integrity_fail	alert[0x32]	4660	1			T31	15		T115	19		T72	1
alert_integrity_fail	alert[0x33]	8506	1			T6	234		T31	8		T66	4
alert_integrity_fail	alert[0x34]	8539	1			T27	20		T66	2		T70	1
alert_integrity_fail	alert[0x35]	4763	1			T19	319		T72	1		T47	1
alert_integrity_fail	alert[0x36]	3524	1			T42	85		T70	4		T103	3
alert_integrity_fail	alert[0x37]	14611	1			T5	1		T66	4		T115	16
alert_integrity_fail	alert[0x38]	4079	1			T6	9		T19	704		T31	13
alert_integrity_fail	alert[0x39]	9574	1			T6	29		T19	118		T27	8
alert_integrity_fail	alert[0x3a]	12613	1			T6	3		T42	3		T115	49
alert_integrity_fail	alert[0x3b]	3525	1			T5	1		T6	7		T70	2
alert_integrity_fail	alert[0x3c]	6753	1			T6	15		T19	17		T103	15
alert_integrity_fail	alert[0x3d]	5970	1			T19	53		T42	7		T43	3
alert_integrity_fail	alert[0x3e]	4232	1			T6	13		T19	57		T31	557
alert_integrity_fail	alert[0x3f]	7272	1			T5	2		T19	136		T40	29
alert_integrity_fail	alert[0x40]	2739	1			T31	15		T42	31		T45	5
alert_ping_fail	alert[0x0]	11	1			T99	1		T280	1		T281	1
alert_ping_fail	alert[0x1]	11	1			T29	1		T99	1		T282	1
alert_ping_fail	alert[0x2]	11	1			T29	1		T234	1		T283	1
alert_ping_fail	alert[0x3]	7	1			T29	1		T284	1		T230	1
alert_ping_fail	alert[0x4]	8	1			T234	1		T285	1		T286	1
alert_ping_fail	alert[0x5]	19	1			T287	1		T283	2		T288	1
alert_ping_fail	alert[0x6]	13	1			T234	1		T274	1		T275	1
alert_ping_fail	alert[0x7]	12	1			T63	1		T289	1		T288	1
alert_ping_fail	alert[0x8]	16	1			T4	1		T29	1		T234	1
alert_ping_fail	alert[0x9]	11	1			T284	1		T290	2		T291	2
alert_ping_fail	alert[0xa]	15	1			T9	1		T11	1		T29	1
alert_ping_fail	alert[0xb]	12	1			T234	1		T285	1		T230	1
alert_ping_fail	alert[0xc]	12	1			T99	1		T287	1		T283	2
alert_ping_fail	alert[0xd]	10	1			T11	1		T29	1		T234	1
alert_ping_fail	alert[0xe]	3	1			T234	1		T292	1		T293	1
alert_ping_fail	alert[0xf]	10	1			T282	3		T287	1		T284	1
alert_ping_fail	alert[0x10]	9	1			T9	1		T223	1		T294	1
alert_ping_fail	alert[0x11]	6	1			T99	1		T283	1		T230	1
alert_ping_fail	alert[0x12]	6	1			T10	1		T281	1		T295	1
alert_ping_fail	alert[0x13]	14	1			T9	1		T274	1		T285	1
alert_ping_fail	alert[0x14]	19	1			T9	2		T29	1		T282	2
alert_ping_fail	alert[0x15]	8	1			T238	2		T234	1		T296	1
alert_ping_fail	alert[0x16]	9	1			T11	1		T274	1		T275	2
alert_ping_fail	alert[0x17]	9	1			T29	1		T281	1		T285	1
alert_ping_fail	alert[0x18]	11	1			T280	1		T284	1		T297	1
alert_ping_fail	alert[0x19]	10	1			T63	1		T99	1		T283	1
alert_ping_fail	alert[0x1a]	4	1			T234	1		T288	1		T298	1
alert_ping_fail	alert[0x1b]	7	1			T290	1		T299	1		T300	2
alert_ping_fail	alert[0x1c]	9	1			T10	1		T29	1		T63	1
alert_ping_fail	alert[0x1d]	8	1			T11	2		T296	1		T301	1
alert_ping_fail	alert[0x1e]	13	1			T234	1		T282	1		T296	1
alert_ping_fail	alert[0x1f]	23	1			T80	1		T63	1		T282	1
alert_ping_fail	alert[0x20]	10	1			T29	1		T280	1		T283	1
alert_ping_fail	alert[0x21]	12	1			T281	1		T285	1		T230	1
alert_ping_fail	alert[0x22]	12	1			T11	1		T282	1		T289	1
alert_ping_fail	alert[0x23]	14	1			T29	1		T283	1		T289	2
alert_ping_fail	alert[0x24]	10	1			T29	1		T63	1		T284	1
alert_ping_fail	alert[0x25]	8	1			T285	1		T302	1		T230	1
alert_ping_fail	alert[0x26]	8	1			T9	1		T280	1		T230	1
alert_ping_fail	alert[0x27]	6	1			T9	1		T289	1		T295	1
alert_ping_fail	alert[0x28]	12	1			T272	2		T63	1		T276	1
alert_ping_fail	alert[0x29]	8	1			T284	1		T288	1		T295	1
alert_ping_fail	alert[0x2a]	14	1			T9	1		T234	2		T289	1
alert_ping_fail	alert[0x2b]	13	1			T10	1		T282	1		T296	1
alert_ping_fail	alert[0x2c]	13	1			T63	1		T99	1		T303	1
alert_ping_fail	alert[0x2d]	14	1			T63	1		T283	1		T81	1
alert_ping_fail	alert[0x2e]	20	1			T10	1		T63	1		T99	1
alert_ping_fail	alert[0x2f]	7	1			T234	1		T282	1		T283	1
alert_ping_fail	alert[0x30]	14	1			T9	1		T10	1		T234	1
alert_ping_fail	alert[0x31]	7	1			T283	1		T302	1		T304	2
alert_ping_fail	alert[0x32]	11	1			T99	1		T283	1		T289	1
alert_ping_fail	alert[0x33]	14	1			T29	1		T280	1		T284	1
alert_ping_fail	alert[0x34]	12	1			T283	2		T285	1		T297	1
alert_ping_fail	alert[0x35]	7	1			T9	1		T63	2		T230	1
alert_ping_fail	alert[0x36]	11	1			T234	1		T63	1		T282	1
alert_ping_fail	alert[0x37]	3	1			T302	1		T305	1		T306	1
alert_ping_fail	alert[0x38]	7	1			T234	1		T63	1		T283	1
alert_ping_fail	alert[0x39]	7	1			T29	1		T234	1		T63	1
alert_ping_fail	alert[0x3a]	11	1			T29	1		T234	1		T63	1
alert_ping_fail	alert[0x3b]	7	1			T9	1		T285	1		T295	1
alert_ping_fail	alert[0x3c]	14	1			T9	4		T11	1		T29	1
alert_ping_fail	alert[0x3d]	8	1			T234	1		T296	1		T304	1
alert_ping_fail	alert[0x3e]	9	1			T63	1		T99	1		T284	1
alert_ping_fail	alert[0x3f]	6	1			T9	1		T285	1		T297	1
alert_ping_fail	alert[0x40]	4	1			T11	1		T284	1		T289	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	115881	1			T5	5		T6	122		T15	20
alert_integrity_fail	class_i[0x1]	119669	1			T5	1		T15	38		T19	7606
alert_integrity_fail	class_i[0x2]	93130	1			T2	19		T5	38		T6	1372
alert_integrity_fail	class_i[0x3]	97626	1			T2	3		T15	7		T30	5
alert_ping_fail	class_i[0x0]	138	1			T10	1		T11	2		T63	3
alert_ping_fail	class_i[0x1]	208	1			T4	1		T9	14		T80	1
alert_ping_fail	class_i[0x2]	154	1			T10	2		T272	2		T238	2
alert_ping_fail	class_i[0x3]	179	1			T9	2		T10	2		T234	20