Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.66 100.00 100.00 100.00 99.38 99.44


Total test records in report: 827
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.784002797 Jun 27 06:15:48 PM PDT 24 Jun 27 06:16:01 PM PDT 24 241487373 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1213342567 Jun 27 06:14:47 PM PDT 24 Jun 27 06:14:56 PM PDT 24 428170716 ps
T356 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1099037053 Jun 27 06:15:52 PM PDT 24 Jun 27 06:16:01 PM PDT 24 13443412 ps
T774 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1142175011 Jun 27 06:15:51 PM PDT 24 Jun 27 06:16:13 PM PDT 24 768159252 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3194653421 Jun 27 06:14:38 PM PDT 24 Jun 27 06:16:31 PM PDT 24 6930454506 ps
T144 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2650018245 Jun 27 06:15:16 PM PDT 24 Jun 27 06:16:54 PM PDT 24 819081940 ps
T776 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1886315435 Jun 27 06:15:46 PM PDT 24 Jun 27 06:15:56 PM PDT 24 138774794 ps
T140 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3628042947 Jun 27 06:15:32 PM PDT 24 Jun 27 06:18:19 PM PDT 24 10707315153 ps
T777 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.430230737 Jun 27 06:15:31 PM PDT 24 Jun 27 06:15:45 PM PDT 24 857235803 ps
T778 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3298144772 Jun 27 06:15:29 PM PDT 24 Jun 27 06:15:31 PM PDT 24 22574074 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.802328270 Jun 27 06:15:29 PM PDT 24 Jun 27 06:15:38 PM PDT 24 113787188 ps
T780 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.22645662 Jun 27 06:15:23 PM PDT 24 Jun 27 06:15:29 PM PDT 24 120667021 ps
T781 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2693945803 Jun 27 06:15:42 PM PDT 24 Jun 27 06:15:56 PM PDT 24 358158225 ps
T134 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3847746563 Jun 27 06:15:06 PM PDT 24 Jun 27 06:17:34 PM PDT 24 1985515501 ps
T782 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3149902181 Jun 27 06:15:15 PM PDT 24 Jun 27 06:15:18 PM PDT 24 13451001 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1580168557 Jun 27 06:15:46 PM PDT 24 Jun 27 06:15:50 PM PDT 24 6571078 ps
T784 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2905129617 Jun 27 06:15:52 PM PDT 24 Jun 27 06:16:01 PM PDT 24 13541262 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.232074384 Jun 27 06:15:06 PM PDT 24 Jun 27 06:19:23 PM PDT 24 3482117914 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.126439183 Jun 27 06:15:46 PM PDT 24 Jun 27 06:16:12 PM PDT 24 180097664 ps
T138 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3702939823 Jun 27 06:14:51 PM PDT 24 Jun 27 06:19:53 PM PDT 24 16956226300 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2002948877 Jun 27 06:15:47 PM PDT 24 Jun 27 06:15:51 PM PDT 24 25264500 ps
T176 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.365817122 Jun 27 06:14:42 PM PDT 24 Jun 27 06:15:05 PM PDT 24 156529172 ps
T788 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.836225194 Jun 27 06:15:47 PM PDT 24 Jun 27 06:15:53 PM PDT 24 12138645 ps
T169 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1570938384 Jun 27 06:15:47 PM PDT 24 Jun 27 06:16:28 PM PDT 24 3322274045 ps
T172 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1822934840 Jun 27 06:15:43 PM PDT 24 Jun 27 06:16:05 PM PDT 24 590831665 ps
T789 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2509862485 Jun 27 06:15:32 PM PDT 24 Jun 27 06:15:34 PM PDT 24 6263948 ps
T790 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2116942878 Jun 27 06:15:52 PM PDT 24 Jun 27 06:16:01 PM PDT 24 8750487 ps
T791 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2509486476 Jun 27 06:14:49 PM PDT 24 Jun 27 06:18:36 PM PDT 24 1722946671 ps
T792 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2217195058 Jun 27 06:15:51 PM PDT 24 Jun 27 06:15:59 PM PDT 24 19243123 ps
T793 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2547720747 Jun 27 06:15:49 PM PDT 24 Jun 27 06:16:01 PM PDT 24 77189442 ps
T155 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1233667131 Jun 27 06:15:45 PM PDT 24 Jun 27 06:21:14 PM PDT 24 15279032763 ps
T151 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2643920542 Jun 27 06:15:24 PM PDT 24 Jun 27 06:18:03 PM PDT 24 8243114520 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2048572543 Jun 27 06:15:51 PM PDT 24 Jun 27 06:16:10 PM PDT 24 601215550 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1027071651 Jun 27 06:15:25 PM PDT 24 Jun 27 06:16:09 PM PDT 24 526781063 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.886292911 Jun 27 06:15:31 PM PDT 24 Jun 27 06:15:42 PM PDT 24 144854015 ps
T166 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3009814804 Jun 27 06:15:45 PM PDT 24 Jun 27 06:15:52 PM PDT 24 40839852 ps
T797 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2101831140 Jun 27 06:15:28 PM PDT 24 Jun 27 06:15:31 PM PDT 24 9301358 ps
T798 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.392690301 Jun 27 06:15:47 PM PDT 24 Jun 27 06:15:51 PM PDT 24 7500397 ps
T799 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2074206858 Jun 27 06:15:44 PM PDT 24 Jun 27 06:15:47 PM PDT 24 14670934 ps
T800 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.628182586 Jun 27 06:15:45 PM PDT 24 Jun 27 06:15:48 PM PDT 24 8181086 ps
T801 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2680742521 Jun 27 06:15:30 PM PDT 24 Jun 27 06:15:36 PM PDT 24 117934846 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1730684468 Jun 27 06:14:49 PM PDT 24 Jun 27 06:17:10 PM PDT 24 1145007199 ps
T803 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2037991238 Jun 27 06:15:47 PM PDT 24 Jun 27 06:16:08 PM PDT 24 265933329 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1170561281 Jun 27 06:15:50 PM PDT 24 Jun 27 06:16:07 PM PDT 24 134000338 ps
T805 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2482231907 Jun 27 06:15:51 PM PDT 24 Jun 27 06:15:59 PM PDT 24 9903060 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.35483412 Jun 27 06:15:23 PM PDT 24 Jun 27 06:15:26 PM PDT 24 9678174 ps
T807 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.791572612 Jun 27 06:15:49 PM PDT 24 Jun 27 06:15:56 PM PDT 24 6398808 ps
T808 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2450420155 Jun 27 06:15:22 PM PDT 24 Jun 27 06:15:31 PM PDT 24 368613050 ps
T164 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1539440773 Jun 27 06:15:29 PM PDT 24 Jun 27 06:16:08 PM PDT 24 489045651 ps
T809 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.391046142 Jun 27 06:15:46 PM PDT 24 Jun 27 06:16:13 PM PDT 24 208032640 ps
T152 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.918797775 Jun 27 06:15:27 PM PDT 24 Jun 27 06:18:29 PM PDT 24 3013451792 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2476014648 Jun 27 06:15:30 PM PDT 24 Jun 27 06:15:36 PM PDT 24 63519993 ps
T811 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2287895093 Jun 27 06:15:45 PM PDT 24 Jun 27 06:15:54 PM PDT 24 136389216 ps
T146 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2632580915 Jun 27 06:15:01 PM PDT 24 Jun 27 06:18:09 PM PDT 24 7359327115 ps
T156 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1667491330 Jun 27 06:15:26 PM PDT 24 Jun 27 06:23:13 PM PDT 24 25871007093 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4040103780 Jun 27 06:14:49 PM PDT 24 Jun 27 06:14:52 PM PDT 24 11973312 ps
T170 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.808920152 Jun 27 06:14:56 PM PDT 24 Jun 27 06:14:59 PM PDT 24 123806026 ps
T813 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1834991593 Jun 27 06:15:48 PM PDT 24 Jun 27 06:16:11 PM PDT 24 491734681 ps
T814 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2756283813 Jun 27 06:15:51 PM PDT 24 Jun 27 06:16:10 PM PDT 24 324980065 ps
T815 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2939467781 Jun 27 06:15:44 PM PDT 24 Jun 27 06:15:49 PM PDT 24 59834723 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1931625588 Jun 27 06:14:52 PM PDT 24 Jun 27 06:15:15 PM PDT 24 1210717138 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.101533693 Jun 27 06:15:30 PM PDT 24 Jun 27 06:15:38 PM PDT 24 48472189 ps
T182 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.726992686 Jun 27 06:14:55 PM PDT 24 Jun 27 06:14:59 PM PDT 24 59538980 ps
T157 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3764071212 Jun 27 06:15:31 PM PDT 24 Jun 27 06:24:40 PM PDT 24 34144252312 ps
T818 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.923880992 Jun 27 06:15:32 PM PDT 24 Jun 27 06:15:34 PM PDT 24 15673736 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2866687567 Jun 27 06:15:06 PM PDT 24 Jun 27 06:15:09 PM PDT 24 8465139 ps
T153 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1276347733 Jun 27 06:15:25 PM PDT 24 Jun 27 06:17:39 PM PDT 24 6769542556 ps
T820 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3713499692 Jun 27 06:15:55 PM PDT 24 Jun 27 06:16:03 PM PDT 24 18987833 ps
T821 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3300954992 Jun 27 06:15:25 PM PDT 24 Jun 27 06:15:35 PM PDT 24 416967692 ps
T142 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3369633883 Jun 27 06:15:24 PM PDT 24 Jun 27 06:25:58 PM PDT 24 17286127869 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4068855615 Jun 27 06:14:57 PM PDT 24 Jun 27 06:15:21 PM PDT 24 319614430 ps
T154 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2574847951 Jun 27 06:14:41 PM PDT 24 Jun 27 06:19:45 PM PDT 24 4221178938 ps
T823 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3941518266 Jun 27 06:15:49 PM PDT 24 Jun 27 06:15:58 PM PDT 24 13003080 ps
T824 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.911719647 Jun 27 06:14:52 PM PDT 24 Jun 27 06:14:59 PM PDT 24 40328953 ps
T825 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1358890338 Jun 27 06:15:47 PM PDT 24 Jun 27 06:19:28 PM PDT 24 4212808243 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2050013880 Jun 27 06:15:06 PM PDT 24 Jun 27 06:15:09 PM PDT 24 13964237 ps
T827 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.998937497 Jun 27 06:15:47 PM PDT 24 Jun 27 06:15:52 PM PDT 24 12879400 ps

Test location /workspace/coverage/default/9.alert_handler_stress_all.2960034368
Short name T5
Test name
Test status
Simulation time 118042347659 ps
CPU time 1851.31 seconds
Started Jun 27 05:24:27 PM PDT 24
Finished Jun 27 05:55:19 PM PDT 24
Peak memory 288316 kb
Host smart-6df081b2-fb25-4a24-9290-1c542b5afced
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960034368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2960034368
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1149860194
Short name T42
Test name
Test status
Simulation time 88205505080 ps
CPU time 6128.2 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 07:07:22 PM PDT 24
Peak memory 331284 kb
Host smart-d7f16302-2da6-4860-bf32-1af5628d1311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149860194 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1149860194
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3982433764
Short name T12
Test name
Test status
Simulation time 1807193705 ps
CPU time 26.35 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:23:40 PM PDT 24
Peak memory 279196 kb
Host smart-6ca40e82-cdd1-494c-8d48-3bf598a647c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3982433764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3982433764
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3754037929
Short name T51
Test name
Test status
Simulation time 181569985531 ps
CPU time 2348.45 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 06:03:51 PM PDT 24
Peak memory 290528 kb
Host smart-5bbc36c8-f7e6-489c-9ad4-5a229ca907a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754037929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3754037929
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2570028538
Short name T177
Test name
Test status
Simulation time 33531399556 ps
CPU time 388.41 seconds
Started Jun 27 06:14:56 PM PDT 24
Finished Jun 27 06:21:25 PM PDT 24
Peak memory 237668 kb
Host smart-a3d8075b-6e5c-47ce-b6af-40108dd022e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2570028538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2570028538
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2062685457
Short name T17
Test name
Test status
Simulation time 560018577 ps
CPU time 8.26 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:24:36 PM PDT 24
Peak memory 249064 kb
Host smart-2a70b1d0-e31c-45ae-bed3-2418235c4db7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2062685457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2062685457
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3559546232
Short name T82
Test name
Test status
Simulation time 238825275912 ps
CPU time 3501.23 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 06:22:47 PM PDT 24
Peak memory 290284 kb
Host smart-55b19979-b067-44bc-9865-d8be431a1abf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559546232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3559546232
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2310473407
Short name T123
Test name
Test status
Simulation time 79725706818 ps
CPU time 282.32 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:20:37 PM PDT 24
Peak memory 265484 kb
Host smart-99b8e540-cb27-4b8c-a9f6-c6dcbd8a149f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2310473407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2310473407
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2119097436
Short name T104
Test name
Test status
Simulation time 45341076690 ps
CPU time 514.79 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:32:44 PM PDT 24
Peak memory 257548 kb
Host smart-80410116-448a-4b24-81b0-a03e36e318da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119097436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2119097436
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1628549927
Short name T276
Test name
Test status
Simulation time 58147294048 ps
CPU time 3426.39 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 289508 kb
Host smart-514c85e6-6a92-49c4-8105-bb0ad39a9e8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628549927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1628549927
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3654093064
Short name T124
Test name
Test status
Simulation time 9038126726 ps
CPU time 617.19 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 265476 kb
Host smart-356d18bd-a13e-4c3f-beba-7d5435008f16
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654093064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3654093064
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.389534435
Short name T93
Test name
Test status
Simulation time 699589005004 ps
CPU time 2263.97 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 06:01:34 PM PDT 24
Peak memory 273920 kb
Host smart-abcd7ead-af6b-408e-8c6b-84724645b5c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389534435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.389534435
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2977022876
Short name T29
Test name
Test status
Simulation time 34649786413 ps
CPU time 381.47 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:33:59 PM PDT 24
Peak memory 249420 kb
Host smart-ec99f3b1-c82c-4184-a30f-5361d1097c8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977022876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2977022876
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2984422278
Short name T143
Test name
Test status
Simulation time 12686788110 ps
CPU time 951.13 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:31:49 PM PDT 24
Peak memory 273588 kb
Host smart-7df1943f-f39b-45fc-96fb-0c20e21c344c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984422278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2984422278
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2063549735
Short name T32
Test name
Test status
Simulation time 199149394312 ps
CPU time 3023.8 seconds
Started Jun 27 05:26:11 PM PDT 24
Finished Jun 27 06:16:37 PM PDT 24
Peak memory 298168 kb
Host smart-be5b7f39-a00c-4947-9495-301adeebd479
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063549735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2063549735
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3310405018
Short name T122
Test name
Test status
Simulation time 1519992698 ps
CPU time 97.96 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:17:04 PM PDT 24
Peak memory 265384 kb
Host smart-17d4f445-ef51-45f8-a121-1e5f97d0c3d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310405018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3310405018
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.732468728
Short name T149
Test name
Test status
Simulation time 25752257184 ps
CPU time 1110.8 seconds
Started Jun 27 06:14:47 PM PDT 24
Finished Jun 27 06:33:19 PM PDT 24
Peak memory 272436 kb
Host smart-012d7ed5-1200-4358-83ac-393f5981204e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732468728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.732468728
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1264976736
Short name T6
Test name
Test status
Simulation time 147532092260 ps
CPU time 2287.88 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 06:06:04 PM PDT 24
Peak memory 290292 kb
Host smart-6e43157d-3d75-458d-a3f1-c0a04319c72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264976736 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1264976736
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1186407241
Short name T273
Test name
Test status
Simulation time 39944805965 ps
CPU time 1627.59 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:53:23 PM PDT 24
Peak memory 287556 kb
Host smart-4e0d4bb9-6963-48be-bf10-f510a3ea29e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186407241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1186407241
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3844868114
Short name T249
Test name
Test status
Simulation time 13145287 ps
CPU time 1.52 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:15:58 PM PDT 24
Peak memory 236704 kb
Host smart-2b6480d8-5509-422a-a9e4-3f4b36d71bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3844868114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3844868114
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.924137971
Short name T181
Test name
Test status
Simulation time 940573946 ps
CPU time 34.84 seconds
Started Jun 27 06:15:03 PM PDT 24
Finished Jun 27 06:15:39 PM PDT 24
Peak memory 240540 kb
Host smart-52792885-ad30-4ef4-81bc-cebfde993442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=924137971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.924137971
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.518440307
Short name T125
Test name
Test status
Simulation time 18084103722 ps
CPU time 350.97 seconds
Started Jun 27 06:15:53 PM PDT 24
Finished Jun 27 06:21:51 PM PDT 24
Peak memory 265456 kb
Host smart-c3a131c1-552f-4dac-b312-728ea463e776
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518440307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.518440307
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4248142276
Short name T335
Test name
Test status
Simulation time 46594195204 ps
CPU time 2826.82 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 06:11:35 PM PDT 24
Peak memory 283696 kb
Host smart-87d8c217-1d3a-4522-b156-0047750e9448
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248142276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4248142276
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1260203542
Short name T283
Test name
Test status
Simulation time 61977449109 ps
CPU time 672.07 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:36:53 PM PDT 24
Peak memory 249224 kb
Host smart-efd9a6b8-6eac-4ec6-a009-59f197b093e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260203542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1260203542
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2647863589
Short name T15
Test name
Test status
Simulation time 9188946288 ps
CPU time 1051.5 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:44:01 PM PDT 24
Peak memory 283236 kb
Host smart-26873847-0af9-411e-b6f5-46507bd914bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647863589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2647863589
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2773681416
Short name T333
Test name
Test status
Simulation time 139727888014 ps
CPU time 1472.46 seconds
Started Jun 27 05:28:15 PM PDT 24
Finished Jun 27 05:52:49 PM PDT 24
Peak memory 273200 kb
Host smart-4373fd04-bbea-4bc0-829b-a58aed3e40fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773681416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2773681416
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.831467814
Short name T132
Test name
Test status
Simulation time 8488291672 ps
CPU time 590.75 seconds
Started Jun 27 06:15:03 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 265436 kb
Host smart-895f7ef0-be95-4fb7-a085-87f25e854528
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831467814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.831467814
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1657693521
Short name T295
Test name
Test status
Simulation time 52457048178 ps
CPU time 595.88 seconds
Started Jun 27 05:25:30 PM PDT 24
Finished Jun 27 05:35:27 PM PDT 24
Peak memory 256152 kb
Host smart-ae759ecb-9b10-41dc-b0bb-06794038a3a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657693521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1657693521
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1747085173
Short name T48
Test name
Test status
Simulation time 83211151626 ps
CPU time 2775.34 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 06:10:41 PM PDT 24
Peak memory 290404 kb
Host smart-56aa0b9d-b863-4ddf-adcc-7eefb2959056
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747085173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1747085173
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3245590994
Short name T301
Test name
Test status
Simulation time 42955660640 ps
CPU time 2414.67 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 06:06:46 PM PDT 24
Peak memory 289668 kb
Host smart-3ba3a47a-970b-4ca9-b519-9be9e7811ab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245590994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3245590994
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.918797775
Short name T152
Test name
Test status
Simulation time 3013451792 ps
CPU time 180.78 seconds
Started Jun 27 06:15:27 PM PDT 24
Finished Jun 27 06:18:29 PM PDT 24
Peak memory 265476 kb
Host smart-27b3b0df-cd2e-4e9e-9577-bb89991a4406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=918797775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.918797775
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3740537049
Short name T238
Test name
Test status
Simulation time 230957504189 ps
CPU time 1984.45 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:58:37 PM PDT 24
Peak memory 273884 kb
Host smart-d59ba850-7af6-4e09-815a-37ed381a1428
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740537049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3740537049
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2411684160
Short name T94
Test name
Test status
Simulation time 16107021288 ps
CPU time 1482.44 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:52:18 PM PDT 24
Peak memory 290336 kb
Host smart-be4e3a2d-fcca-4c12-bb7c-6e2014401deb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411684160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2411684160
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3678772860
Short name T359
Test name
Test status
Simulation time 57165342 ps
CPU time 5.61 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:13 PM PDT 24
Peak memory 248712 kb
Host smart-4fbae052-0945-49ff-ad3d-19b692bae019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678772860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3678772860
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1276347733
Short name T153
Test name
Test status
Simulation time 6769542556 ps
CPU time 133.13 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:17:39 PM PDT 24
Peak memory 267476 kb
Host smart-462bb42a-920d-47ee-b55c-9efe570c2ca3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276347733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1276347733
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2863409247
Short name T127
Test name
Test status
Simulation time 27402549608 ps
CPU time 276.95 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:20:26 PM PDT 24
Peak memory 265432 kb
Host smart-6f1c7ea3-b370-4df1-a439-48af071d5d6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2863409247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2863409247
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4189490023
Short name T348
Test name
Test status
Simulation time 11185690 ps
CPU time 1.6 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:15:48 PM PDT 24
Peak memory 236684 kb
Host smart-44a35abf-bbbb-4472-91ab-882b7d0f7f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4189490023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4189490023
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1020060276
Short name T526
Test name
Test status
Simulation time 99143821292 ps
CPU time 477.17 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:31:13 PM PDT 24
Peak memory 249116 kb
Host smart-1b774823-9045-44bc-9a60-3254fddc5faa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020060276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1020060276
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1762045799
Short name T167
Test name
Test status
Simulation time 60555134 ps
CPU time 3.7 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:54 PM PDT 24
Peak memory 237824 kb
Host smart-f4092456-0058-4c20-bbf9-9a2496586b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1762045799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1762045799
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1728801332
Short name T89
Test name
Test status
Simulation time 215648474916 ps
CPU time 5502.49 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 06:56:28 PM PDT 24
Peak memory 367340 kb
Host smart-c5dc4a36-f85b-4435-9db9-33f21fb7e891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728801332 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1728801332
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.4105512824
Short name T336
Test name
Test status
Simulation time 82165393669 ps
CPU time 1460.62 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:49:05 PM PDT 24
Peak memory 273212 kb
Host smart-7639a7cc-c85d-41aa-8b83-6f645b07dbfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105512824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4105512824
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.232376596
Short name T292
Test name
Test status
Simulation time 14278284180 ps
CPU time 522.57 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:33:55 PM PDT 24
Peak memory 255548 kb
Host smart-3ab87510-7c0a-43a6-9856-e15a5f30a9cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232376596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.232376596
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2726799472
Short name T313
Test name
Test status
Simulation time 37353563649 ps
CPU time 3804.37 seconds
Started Jun 27 05:25:53 PM PDT 24
Finished Jun 27 06:29:18 PM PDT 24
Peak memory 322712 kb
Host smart-55c899f3-fc0f-4224-9da8-f001724859f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726799472 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2726799472
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2316432463
Short name T121
Test name
Test status
Simulation time 6450944270 ps
CPU time 500.73 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:24:07 PM PDT 24
Peak memory 265568 kb
Host smart-4dfde698-c4b9-4046-bb8b-bf0d75e257a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316432463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2316432463
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2774907052
Short name T107
Test name
Test status
Simulation time 14102595084 ps
CPU time 1055.03 seconds
Started Jun 27 05:26:43 PM PDT 24
Finished Jun 27 05:44:19 PM PDT 24
Peak memory 273000 kb
Host smart-bd928b5c-524d-4df9-b367-ea479014d61d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774907052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2774907052
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3894773504
Short name T289
Test name
Test status
Simulation time 20267442027 ps
CPU time 459.12 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:34:25 PM PDT 24
Peak memory 256052 kb
Host smart-1d3391f4-519c-4a04-915b-2d4fd64f887e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894773504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3894773504
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4184893584
Short name T130
Test name
Test status
Simulation time 5770063338 ps
CPU time 352.37 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:21:19 PM PDT 24
Peak memory 271952 kb
Host smart-392e965b-c441-4c77-b17b-21b5ba4bb20d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4184893584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4184893584
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2483332484
Short name T202
Test name
Test status
Simulation time 53047431 ps
CPU time 3.74 seconds
Started Jun 27 05:23:15 PM PDT 24
Finished Jun 27 05:23:21 PM PDT 24
Peak memory 249532 kb
Host smart-2f3b0631-b1ca-409b-aff2-457edfd9799e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483332484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2483332484
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1574583895
Short name T35
Test name
Test status
Simulation time 17956678 ps
CPU time 2.6 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:23:17 PM PDT 24
Peak memory 249432 kb
Host smart-6d631b0e-9efb-4e70-9b94-e359b79fa7d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1574583895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1574583895
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3656261291
Short name T208
Test name
Test status
Simulation time 173289834 ps
CPU time 3.79 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 05:24:29 PM PDT 24
Peak memory 249512 kb
Host smart-fa02e394-1590-40f9-91a8-9ce5d3dc3855
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3656261291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3656261291
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3101171312
Short name T206
Test name
Test status
Simulation time 172383730 ps
CPU time 4.19 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:24:28 PM PDT 24
Peak memory 249552 kb
Host smart-f3551afb-c0a6-41ca-adac-2d6a5cfabbe3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3101171312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3101171312
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2802212661
Short name T354
Test name
Test status
Simulation time 13988514 ps
CPU time 1.49 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:15:57 PM PDT 24
Peak memory 236684 kb
Host smart-712b506c-419a-4a91-9517-bbb4c2b60787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802212661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2802212661
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2648200636
Short name T567
Test name
Test status
Simulation time 1536965625 ps
CPU time 26.46 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:23:41 PM PDT 24
Peak memory 249224 kb
Host smart-0df0f4ad-e09a-460f-a0ac-4f8dd0bb3181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26482
00636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2648200636
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3957369140
Short name T325
Test name
Test status
Simulation time 41501769154 ps
CPU time 2251.93 seconds
Started Jun 27 05:23:16 PM PDT 24
Finished Jun 27 06:00:50 PM PDT 24
Peak memory 290164 kb
Host smart-1a1480f4-aefb-42fb-9fc1-0dfd80726a56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957369140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3957369140
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2122383920
Short name T338
Test name
Test status
Simulation time 93708836900 ps
CPU time 1864.58 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:56:38 PM PDT 24
Peak memory 273888 kb
Host smart-1b8e800d-6460-42d9-a77d-9eee33d41c94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122383920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2122383920
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1501686275
Short name T9
Test name
Test status
Simulation time 14351985487 ps
CPU time 537.84 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:36:01 PM PDT 24
Peak memory 249300 kb
Host smart-70d74dbb-6d82-4d53-8fd1-3b73696a0d53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501686275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1501686275
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1171248349
Short name T75
Test name
Test status
Simulation time 3047375614 ps
CPU time 50.91 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:27:54 PM PDT 24
Peak memory 256876 kb
Host smart-67a00059-a153-43ea-90c3-d40f7e115d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11712
48349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1171248349
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3628042947
Short name T140
Test name
Test status
Simulation time 10707315153 ps
CPU time 165.97 seconds
Started Jun 27 06:15:32 PM PDT 24
Finished Jun 27 06:18:19 PM PDT 24
Peak memory 265332 kb
Host smart-2c075982-c2dd-458b-8217-f615f987e26d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3628042947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3628042947
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3764071212
Short name T157
Test name
Test status
Simulation time 34144252312 ps
CPU time 548.35 seconds
Started Jun 27 06:15:31 PM PDT 24
Finished Jun 27 06:24:40 PM PDT 24
Peak memory 265316 kb
Host smart-44d911c5-2c61-465b-9661-410de837bb1d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764071212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3764071212
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3746202102
Short name T334
Test name
Test status
Simulation time 93469621068 ps
CPU time 2621.8 seconds
Started Jun 27 05:23:20 PM PDT 24
Finished Jun 27 06:07:03 PM PDT 24
Peak memory 287564 kb
Host smart-5ec79dec-c1b4-4a1a-97ff-bf9c0a1dec8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746202102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3746202102
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4095279576
Short name T53
Test name
Test status
Simulation time 29627902656 ps
CPU time 1285.05 seconds
Started Jun 27 05:24:21 PM PDT 24
Finished Jun 27 05:45:47 PM PDT 24
Peak memory 273028 kb
Host smart-27d8b36a-0dd0-469a-a6b3-2ef9b08dc434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095279576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4095279576
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3725664750
Short name T302
Test name
Test status
Simulation time 9063980484 ps
CPU time 344.03 seconds
Started Jun 27 05:24:30 PM PDT 24
Finished Jun 27 05:30:15 PM PDT 24
Peak memory 249212 kb
Host smart-ab654a76-6af3-44ff-9445-508bc2cd1a66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725664750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3725664750
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3667040937
Short name T109
Test name
Test status
Simulation time 143204828009 ps
CPU time 2202 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 06:01:26 PM PDT 24
Peak memory 281684 kb
Host smart-0def9363-a304-4a10-93a7-6bc403a02b32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667040937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3667040937
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1457490827
Short name T268
Test name
Test status
Simulation time 768867077 ps
CPU time 46.5 seconds
Started Jun 27 05:24:47 PM PDT 24
Finished Jun 27 05:25:35 PM PDT 24
Peak memory 256852 kb
Host smart-4d006fa1-7fcb-4b18-b3aa-55a0339f67db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14574
90827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1457490827
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1308584696
Short name T322
Test name
Test status
Simulation time 97752426885 ps
CPU time 1612.32 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:51:37 PM PDT 24
Peak memory 290420 kb
Host smart-64f0b21e-d6a7-4a1d-bdae-1d5a3400a3b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308584696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1308584696
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.181694570
Short name T270
Test name
Test status
Simulation time 514116727 ps
CPU time 27.74 seconds
Started Jun 27 05:24:47 PM PDT 24
Finished Jun 27 05:25:16 PM PDT 24
Peak memory 256772 kb
Host smart-4355148f-6701-4a9d-8da9-eea8fc054e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
4570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.181694570
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3071349503
Short name T83
Test name
Test status
Simulation time 241837380 ps
CPU time 28.55 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:25:14 PM PDT 24
Peak memory 250208 kb
Host smart-5a556562-0bce-4cbb-8c6a-c8a1ba10f5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30713
49503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3071349503
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2079704506
Short name T71
Test name
Test status
Simulation time 13015278380 ps
CPU time 1390.21 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 05:48:44 PM PDT 24
Peak memory 285096 kb
Host smart-c96b740d-0ff8-4956-85cb-a9c6bf9c1116
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079704506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2079704506
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2937824915
Short name T344
Test name
Test status
Simulation time 14938903630 ps
CPU time 1426.24 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 05:49:21 PM PDT 24
Peak memory 289416 kb
Host smart-6d4acdb8-6318-4b0a-be1b-f8abf36e8313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937824915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2937824915
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1510443822
Short name T115
Test name
Test status
Simulation time 19984892096 ps
CPU time 716.49 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:37:38 PM PDT 24
Peak memory 273368 kb
Host smart-a2ce235a-b339-4e6b-b7ca-72319505c1bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510443822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1510443822
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2956021753
Short name T328
Test name
Test status
Simulation time 20797956444 ps
CPU time 1124.58 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:44:35 PM PDT 24
Peak memory 274012 kb
Host smart-948ad8de-cc53-41ac-985c-eb196a7c6ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956021753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2956021753
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.584109579
Short name T226
Test name
Test status
Simulation time 1740834179 ps
CPU time 31.96 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:26:47 PM PDT 24
Peak memory 256252 kb
Host smart-a0bff9f2-a2fd-4cd8-9946-4a1992b499a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58410
9579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.584109579
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.40435909
Short name T264
Test name
Test status
Simulation time 168991528 ps
CPU time 4.01 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:26:19 PM PDT 24
Peak memory 241072 kb
Host smart-7722cb80-2b7b-42d9-b046-f8d7da725898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.40435909
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3830234537
Short name T345
Test name
Test status
Simulation time 82510131392 ps
CPU time 1547.61 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:52:36 PM PDT 24
Peak memory 289680 kb
Host smart-a5727e30-8dc3-4b2a-b905-a43a5e88f436
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830234537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3830234537
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1294484503
Short name T92
Test name
Test status
Simulation time 14011623066 ps
CPU time 743.46 seconds
Started Jun 27 05:26:42 PM PDT 24
Finished Jun 27 05:39:06 PM PDT 24
Peak memory 265800 kb
Host smart-3471d9a0-b910-438a-877c-ef5ee2d4427b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294484503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1294484503
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1470280058
Short name T2
Test name
Test status
Simulation time 15689389560 ps
CPU time 1239.81 seconds
Started Jun 27 05:28:29 PM PDT 24
Finished Jun 27 05:49:10 PM PDT 24
Peak memory 289716 kb
Host smart-cbfed2ff-de91-40d0-8c66-10d15ce5a4a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470280058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1470280058
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.4126154681
Short name T320
Test name
Test status
Simulation time 26323438956 ps
CPU time 2508.75 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 06:06:00 PM PDT 24
Peak memory 290476 kb
Host smart-b1ebecbe-503b-4c02-8e3a-90efd1585deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126154681 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.4126154681
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3009814804
Short name T166
Test name
Test status
Simulation time 40839852 ps
CPU time 3.85 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 237724 kb
Host smart-e4c2499f-4671-4ee7-a6cf-99b38f018c11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3009814804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3009814804
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3476301208
Short name T147
Test name
Test status
Simulation time 3034056446 ps
CPU time 202.47 seconds
Started Jun 27 06:14:53 PM PDT 24
Finished Jun 27 06:18:17 PM PDT 24
Peak memory 265548 kb
Host smart-22ff9097-e0fc-4ffd-88ed-47e404fc613a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3476301208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3476301208
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1539440773
Short name T164
Test name
Test status
Simulation time 489045651 ps
CPU time 37.58 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:16:08 PM PDT 24
Peak memory 240572 kb
Host smart-7003e955-27d8-4f30-bd34-3c113dc10d39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1539440773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1539440773
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.177479852
Short name T165
Test name
Test status
Simulation time 2143911647 ps
CPU time 40.01 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:16:36 PM PDT 24
Peak memory 240580 kb
Host smart-81aaa455-8e12-4976-a046-d74df094b2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=177479852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.177479852
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1570938384
Short name T169
Test name
Test status
Simulation time 3322274045 ps
CPU time 38.26 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:16:28 PM PDT 24
Peak memory 240568 kb
Host smart-648edcb5-1be7-4379-b820-f17fd4676f83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1570938384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1570938384
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.808920152
Short name T170
Test name
Test status
Simulation time 123806026 ps
CPU time 2.42 seconds
Started Jun 27 06:14:56 PM PDT 24
Finished Jun 27 06:14:59 PM PDT 24
Peak memory 237800 kb
Host smart-c22025d4-033d-447c-a9cd-340a324884eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=808920152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.808920152
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1070541705
Short name T141
Test name
Test status
Simulation time 24560761582 ps
CPU time 495.04 seconds
Started Jun 27 06:14:40 PM PDT 24
Finished Jun 27 06:22:55 PM PDT 24
Peak memory 268228 kb
Host smart-7910b460-007d-462d-a6f8-1d6177594199
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070541705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1070541705
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2574847951
Short name T154
Test name
Test status
Simulation time 4221178938 ps
CPU time 302.83 seconds
Started Jun 27 06:14:41 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 265500 kb
Host smart-711549fe-0f36-4e10-a0a9-15272c2d2764
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2574847951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2574847951
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1553876379
Short name T160
Test name
Test status
Simulation time 64655926 ps
CPU time 3.35 seconds
Started Jun 27 06:15:24 PM PDT 24
Finished Jun 27 06:15:29 PM PDT 24
Peak memory 237608 kb
Host smart-a2b61a3e-4acc-4e7a-8402-6ebbe8bdd7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1553876379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1553876379
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2819528576
Short name T175
Test name
Test status
Simulation time 162419309 ps
CPU time 8.01 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:16:00 PM PDT 24
Peak memory 238648 kb
Host smart-8452cc31-d644-409b-a3e0-92c7117e213a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2819528576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2819528576
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2324604011
Short name T119
Test name
Test status
Simulation time 1192956543 ps
CPU time 108.39 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:17:34 PM PDT 24
Peak memory 257236 kb
Host smart-4611b3d8-c266-4faf-ad14-64cd199bc859
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2324604011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2324604011
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1822934840
Short name T172
Test name
Test status
Simulation time 590831665 ps
CPU time 20 seconds
Started Jun 27 06:15:43 PM PDT 24
Finished Jun 27 06:16:05 PM PDT 24
Peak memory 240504 kb
Host smart-5ed980be-0a95-41b3-bc97-afa6226efea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1822934840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1822934840
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3847746563
Short name T134
Test name
Test status
Simulation time 1985515501 ps
CPU time 145.98 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:17:34 PM PDT 24
Peak memory 265528 kb
Host smart-8cccd381-2a2f-47a7-b890-e5ee6c5e7fef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3847746563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3847746563
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3960965666
Short name T173
Test name
Test status
Simulation time 4491483916 ps
CPU time 76.39 seconds
Started Jun 27 06:14:56 PM PDT 24
Finished Jun 27 06:16:14 PM PDT 24
Peak memory 240620 kb
Host smart-7bc8fa60-c2be-4119-b9fd-d931d874ad12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3960965666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3960965666
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.726992686
Short name T182
Test name
Test status
Simulation time 59538980 ps
CPU time 2.78 seconds
Started Jun 27 06:14:55 PM PDT 24
Finished Jun 27 06:14:59 PM PDT 24
Peak memory 236648 kb
Host smart-af42a45d-94db-4bdd-839c-ceaf9914b150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=726992686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.726992686
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1095483946
Short name T171
Test name
Test status
Simulation time 299028438 ps
CPU time 22.83 seconds
Started Jun 27 06:15:27 PM PDT 24
Finished Jun 27 06:15:51 PM PDT 24
Peak memory 248740 kb
Host smart-ae46539f-4c35-4e6c-97b2-1d69279abb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1095483946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1095483946
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2890070146
Short name T179
Test name
Test status
Simulation time 35577509 ps
CPU time 3.26 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 237624 kb
Host smart-2a08f9ea-daa6-4d8e-9cbd-790f414e5033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2890070146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2890070146
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2762645146
Short name T159
Test name
Test status
Simulation time 56039331 ps
CPU time 4.27 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:12 PM PDT 24
Peak memory 237596 kb
Host smart-fd6a678b-5e23-4ebd-80b8-fee501cd9990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2762645146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2762645146
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.463046684
Short name T174
Test name
Test status
Simulation time 2448131421 ps
CPU time 83.74 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:16:41 PM PDT 24
Peak memory 240636 kb
Host smart-de73b9dd-fb66-48f9-93f2-dfeaa838c5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=463046684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.463046684
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.640391601
Short name T183
Test name
Test status
Simulation time 180684290 ps
CPU time 24.6 seconds
Started Jun 27 06:15:32 PM PDT 24
Finished Jun 27 06:15:57 PM PDT 24
Peak memory 240548 kb
Host smart-7c6a83ed-e042-48ff-8361-132cc2008f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=640391601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.640391601
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2861779413
Short name T168
Test name
Test status
Simulation time 38953696 ps
CPU time 3.74 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:15:30 PM PDT 24
Peak memory 237616 kb
Host smart-18127dc9-6b90-4cf6-8bf9-7b6ae6a70507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2861779413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2861779413
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.682359528
Short name T158
Test name
Test status
Simulation time 195673120 ps
CPU time 3.93 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:15:31 PM PDT 24
Peak memory 238100 kb
Host smart-3697778b-83b0-4e73-902d-eebf303832bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=682359528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.682359528
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.497880387
Short name T26
Test name
Test status
Simulation time 145480349230 ps
CPU time 2204.34 seconds
Started Jun 27 05:23:48 PM PDT 24
Finished Jun 27 06:00:36 PM PDT 24
Peak memory 306872 kb
Host smart-909b85d7-9ac7-4bad-8ac2-bbf6a23859b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497880387 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.497880387
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3194653421
Short name T775
Test name
Test status
Simulation time 6930454506 ps
CPU time 112.71 seconds
Started Jun 27 06:14:38 PM PDT 24
Finished Jun 27 06:16:31 PM PDT 24
Peak memory 237760 kb
Host smart-18380cdd-d649-4937-934f-ec42b24a0d81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3194653421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3194653421
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.127909091
Short name T749
Test name
Test status
Simulation time 5716617510 ps
CPU time 371.33 seconds
Started Jun 27 06:14:58 PM PDT 24
Finished Jun 27 06:21:10 PM PDT 24
Peak memory 237684 kb
Host smart-804b9a08-b79e-48bb-94b3-ec09f07d6885
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=127909091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.127909091
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.911719647
Short name T824
Test name
Test status
Simulation time 40328953 ps
CPU time 6.08 seconds
Started Jun 27 06:14:52 PM PDT 24
Finished Jun 27 06:14:59 PM PDT 24
Peak memory 249128 kb
Host smart-f5af2a12-8b45-496a-9c93-eb463b6c9043
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=911719647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.911719647
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1577939540
Short name T201
Test name
Test status
Simulation time 121739339 ps
CPU time 8.93 seconds
Started Jun 27 06:14:48 PM PDT 24
Finished Jun 27 06:14:58 PM PDT 24
Peak memory 257000 kb
Host smart-9a16fce9-295e-42bf-8f2d-b269f6b7fec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577939540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1577939540
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3647052139
Short name T769
Test name
Test status
Simulation time 114407048 ps
CPU time 8.5 seconds
Started Jun 27 06:14:48 PM PDT 24
Finished Jun 27 06:14:58 PM PDT 24
Peak memory 240568 kb
Host smart-49a24ff2-9eb7-40cd-b071-275999c69cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3647052139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3647052139
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1134212133
Short name T236
Test name
Test status
Simulation time 6483262 ps
CPU time 1.41 seconds
Started Jun 27 06:14:51 PM PDT 24
Finished Jun 27 06:14:53 PM PDT 24
Peak memory 235696 kb
Host smart-8b3e5d43-9357-424d-89a3-01e351c8cf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134212133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1134212133
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1931625588
Short name T816
Test name
Test status
Simulation time 1210717138 ps
CPU time 21.36 seconds
Started Jun 27 06:14:52 PM PDT 24
Finished Jun 27 06:15:15 PM PDT 24
Peak memory 244888 kb
Host smart-5d4a90ed-bdf4-4a31-b200-06c1f6c295c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1931625588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1931625588
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4068855615
Short name T822
Test name
Test status
Simulation time 319614430 ps
CPU time 22.84 seconds
Started Jun 27 06:14:57 PM PDT 24
Finished Jun 27 06:15:21 PM PDT 24
Peak memory 248308 kb
Host smart-4b29addb-5eab-4255-adf2-6f61d96d182f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4068855615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4068855615
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1414733154
Short name T737
Test name
Test status
Simulation time 6625008803 ps
CPU time 243.52 seconds
Started Jun 27 06:14:50 PM PDT 24
Finished Jun 27 06:18:55 PM PDT 24
Peak memory 240636 kb
Host smart-fc0d3807-4509-40f1-be95-4c222dbce009
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1414733154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1414733154
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2509486476
Short name T791
Test name
Test status
Simulation time 1722946671 ps
CPU time 226.25 seconds
Started Jun 27 06:14:49 PM PDT 24
Finished Jun 27 06:18:36 PM PDT 24
Peak memory 240544 kb
Host smart-8bf52f44-88a0-4356-8535-4aac04c65389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2509486476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2509486476
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.355403163
Short name T161
Test name
Test status
Simulation time 36509416 ps
CPU time 4.68 seconds
Started Jun 27 06:14:41 PM PDT 24
Finished Jun 27 06:14:47 PM PDT 24
Peak memory 248200 kb
Host smart-c14c8f5f-975d-4b58-a4e2-66f0caff03f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=355403163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.355403163
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1672465457
Short name T730
Test name
Test status
Simulation time 186854383 ps
CPU time 5.28 seconds
Started Jun 27 06:14:41 PM PDT 24
Finished Jun 27 06:14:47 PM PDT 24
Peak memory 237204 kb
Host smart-021fcb31-5869-4e7d-8330-39d3fb20e824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1672465457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1672465457
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4040103780
Short name T812
Test name
Test status
Simulation time 11973312 ps
CPU time 1.44 seconds
Started Jun 27 06:14:49 PM PDT 24
Finished Jun 27 06:14:52 PM PDT 24
Peak memory 236688 kb
Host smart-d7ea36da-4b3e-47ca-b18e-44e8eda82a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4040103780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4040103780
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.100163925
Short name T728
Test name
Test status
Simulation time 1297976452 ps
CPU time 21.26 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:29 PM PDT 24
Peak memory 244820 kb
Host smart-a1f33ed5-d554-49de-afbf-7118bde7814c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=100163925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.100163925
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1726530457
Short name T129
Test name
Test status
Simulation time 12193071578 ps
CPU time 433.43 seconds
Started Jun 27 06:14:41 PM PDT 24
Finished Jun 27 06:21:56 PM PDT 24
Peak memory 265440 kb
Host smart-44ce726d-21a4-474f-ae49-b7d9d18cfc5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726530457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1726530457
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3188690978
Short name T247
Test name
Test status
Simulation time 325304164 ps
CPU time 20.56 seconds
Started Jun 27 06:14:45 PM PDT 24
Finished Jun 27 06:15:06 PM PDT 24
Peak memory 255712 kb
Host smart-7af32a2d-09ce-4ecd-87f6-ab39b1aab5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188690978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3188690978
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.365817122
Short name T176
Test name
Test status
Simulation time 156529172 ps
CPU time 21.82 seconds
Started Jun 27 06:14:42 PM PDT 24
Finished Jun 27 06:15:05 PM PDT 24
Peak memory 237888 kb
Host smart-5e421ee9-7c3e-4d78-8014-f252c7e70f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=365817122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.365817122
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.430230737
Short name T777
Test name
Test status
Simulation time 857235803 ps
CPU time 13.18 seconds
Started Jun 27 06:15:31 PM PDT 24
Finished Jun 27 06:15:45 PM PDT 24
Peak memory 250824 kb
Host smart-795028a5-0689-4a1d-abd4-3a50892e46e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430230737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.430230737
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.802328270
Short name T779
Test name
Test status
Simulation time 113787188 ps
CPU time 7.44 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:15:38 PM PDT 24
Peak memory 240580 kb
Host smart-048224b6-b0ce-4331-b09e-dc2e35477660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=802328270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.802328270
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1695700394
Short name T751
Test name
Test status
Simulation time 7628453 ps
CPU time 1.46 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:15:29 PM PDT 24
Peak memory 235588 kb
Host smart-70cf6dfc-1ecc-4129-b657-ca737165cf72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1695700394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1695700394
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2146183629
Short name T187
Test name
Test status
Simulation time 348218813 ps
CPU time 25.53 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:15:53 PM PDT 24
Peak memory 245804 kb
Host smart-6c36083e-0a80-411b-bff3-fb2f6c4265e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2146183629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2146183629
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.22645662
Short name T780
Test name
Test status
Simulation time 120667021 ps
CPU time 5.09 seconds
Started Jun 27 06:15:23 PM PDT 24
Finished Jun 27 06:15:29 PM PDT 24
Peak memory 248836 kb
Host smart-7de7e97f-b937-43e1-9847-575eb4a7bf0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=22645662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.22645662
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2826174081
Short name T764
Test name
Test status
Simulation time 35920401 ps
CPU time 6.22 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:15:36 PM PDT 24
Peak memory 243296 kb
Host smart-5a4d4828-cf5f-43bd-a6fe-9abc02302913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826174081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2826174081
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2112425920
Short name T244
Test name
Test status
Simulation time 214739029 ps
CPU time 4.85 seconds
Started Jun 27 06:15:22 PM PDT 24
Finished Jun 27 06:15:28 PM PDT 24
Peak memory 236580 kb
Host smart-7d315cea-4f69-4d99-9680-9b664314513f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2112425920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2112425920
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2101831140
Short name T797
Test name
Test status
Simulation time 9301358 ps
CPU time 1.53 seconds
Started Jun 27 06:15:28 PM PDT 24
Finished Jun 27 06:15:31 PM PDT 24
Peak memory 237640 kb
Host smart-fb0a9f5f-d30b-4e96-a6a6-db511871aabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2101831140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2101831140
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1475778727
Short name T770
Test name
Test status
Simulation time 376110463 ps
CPU time 25.25 seconds
Started Jun 27 06:15:22 PM PDT 24
Finished Jun 27 06:15:48 PM PDT 24
Peak memory 245804 kb
Host smart-d8cd13d1-31a7-40ec-b0d5-bf82add548c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1475778727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1475778727
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2643920542
Short name T151
Test name
Test status
Simulation time 8243114520 ps
CPU time 158.03 seconds
Started Jun 27 06:15:24 PM PDT 24
Finished Jun 27 06:18:03 PM PDT 24
Peak memory 265588 kb
Host smart-976ae248-b0ae-4b09-8119-7b038cb42162
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2643920542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2643920542
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1667491330
Short name T156
Test name
Test status
Simulation time 25871007093 ps
CPU time 465.55 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:23:13 PM PDT 24
Peak memory 265404 kb
Host smart-8c677b58-2a06-482d-b5f0-3d05573b85c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667491330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1667491330
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.101533693
Short name T817
Test name
Test status
Simulation time 48472189 ps
CPU time 6.97 seconds
Started Jun 27 06:15:30 PM PDT 24
Finished Jun 27 06:15:38 PM PDT 24
Peak memory 254648 kb
Host smart-739c482c-4283-4a38-9c30-18518bd7cf63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=101533693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.101533693
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.113113972
Short name T743
Test name
Test status
Simulation time 294862895 ps
CPU time 11.93 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:16:04 PM PDT 24
Peak memory 251184 kb
Host smart-fc9bbbb3-d639-41e9-907d-523668eb0149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113113972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.113113972
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1745016246
Short name T250
Test name
Test status
Simulation time 221876515 ps
CPU time 5.02 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 236644 kb
Host smart-c7e529d8-4c5a-4f63-a54b-379cd2766774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1745016246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1745016246
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2509862485
Short name T789
Test name
Test status
Simulation time 6263948 ps
CPU time 1.43 seconds
Started Jun 27 06:15:32 PM PDT 24
Finished Jun 27 06:15:34 PM PDT 24
Peak memory 237520 kb
Host smart-a239f868-2b41-4348-850e-297a571e9cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2509862485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2509862485
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.126439183
Short name T786
Test name
Test status
Simulation time 180097664 ps
CPU time 22.9 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:16:12 PM PDT 24
Peak memory 244872 kb
Host smart-333567ee-f76a-410f-8a76-6498b94e3765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=126439183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.126439183
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.5672651
Short name T131
Test name
Test status
Simulation time 18685955819 ps
CPU time 470.17 seconds
Started Jun 27 06:15:27 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 265328 kb
Host smart-ec0a9629-d1cd-406f-8051-7a07e35ce8da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5672651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_shadow_reg_errors_with_csr_rw.5672651
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3036496511
Short name T248
Test name
Test status
Simulation time 334688730 ps
CPU time 9.72 seconds
Started Jun 27 06:15:28 PM PDT 24
Finished Jun 27 06:15:39 PM PDT 24
Peak memory 249044 kb
Host smart-05b1cfd8-1d55-48a4-b0e1-63ec38346313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3036496511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3036496511
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2693945803
Short name T781
Test name
Test status
Simulation time 358158225 ps
CPU time 12.98 seconds
Started Jun 27 06:15:42 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 249840 kb
Host smart-1fd79d5f-29ec-4ced-ad20-54632af1aaa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693945803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2693945803
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3630092675
Short name T242
Test name
Test status
Simulation time 67078317 ps
CPU time 5.73 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 237588 kb
Host smart-44d8a18a-4cf0-4fb9-81e0-d3f9ae122a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3630092675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3630092675
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1580168557
Short name T783
Test name
Test status
Simulation time 6571078 ps
CPU time 1.58 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:15:50 PM PDT 24
Peak memory 235620 kb
Host smart-401f49fd-f4d6-4b48-8767-1f532c265c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580168557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1580168557
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.391046142
Short name T809
Test name
Test status
Simulation time 208032640 ps
CPU time 24.54 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:16:13 PM PDT 24
Peak memory 248760 kb
Host smart-0c63c2d8-6564-44b3-8888-6face6d9a720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=391046142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.391046142
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1170561281
Short name T804
Test name
Test status
Simulation time 134000338 ps
CPU time 10.35 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:16:07 PM PDT 24
Peak memory 248816 kb
Host smart-1510976a-a881-4b92-ac86-6ee80c201926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1170561281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1170561281
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2547720747
Short name T793
Test name
Test status
Simulation time 77189442 ps
CPU time 6.16 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 239852 kb
Host smart-9fdc5783-4050-4192-8881-fdfca54f7763
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547720747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2547720747
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.753311956
Short name T752
Test name
Test status
Simulation time 483746712 ps
CPU time 5.05 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:55 PM PDT 24
Peak memory 240528 kb
Host smart-99720ec6-2d2e-4ecb-ae63-a8cb17ecb54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=753311956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.753311956
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3941518266
Short name T823
Test name
Test status
Simulation time 13003080 ps
CPU time 1.81 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:15:58 PM PDT 24
Peak memory 236692 kb
Host smart-5b9aff1e-cb62-41ca-b3fb-68cb8daf97ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3941518266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3941518266
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3849355934
Short name T184
Test name
Test status
Simulation time 1223279528 ps
CPU time 35.3 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:16:30 PM PDT 24
Peak memory 244856 kb
Host smart-186cb0ea-f4fc-47c5-8bcd-84883b895a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3849355934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3849355934
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2859969180
Short name T245
Test name
Test status
Simulation time 1320784007 ps
CPU time 24.22 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:16:14 PM PDT 24
Peak memory 248472 kb
Host smart-c02bb267-384c-4135-a5c1-33ad1e8271b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2859969180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2859969180
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2048572543
Short name T794
Test name
Test status
Simulation time 601215550 ps
CPU time 12.38 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:10 PM PDT 24
Peak memory 255656 kb
Host smart-e2d50a2c-992d-49a3-badd-713449d65cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048572543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2048572543
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2939467781
Short name T815
Test name
Test status
Simulation time 59834723 ps
CPU time 3.64 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:15:49 PM PDT 24
Peak memory 240572 kb
Host smart-a925bbb6-303d-41d2-be63-573a55aeb481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2939467781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2939467781
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2998661596
Short name T767
Test name
Test status
Simulation time 1040826826 ps
CPU time 18.07 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:16:04 PM PDT 24
Peak memory 240564 kb
Host smart-1325cb36-5bd8-4858-b076-10d821f62f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2998661596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2998661596
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3159186935
Short name T128
Test name
Test status
Simulation time 7650147847 ps
CPU time 279.21 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:20:34 PM PDT 24
Peak memory 272132 kb
Host smart-a8d459a1-472d-438a-94a3-54ea270fcc7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3159186935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3159186935
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.978187849
Short name T120
Test name
Test status
Simulation time 2511337004 ps
CPU time 340.84 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:21:37 PM PDT 24
Peak memory 265416 kb
Host smart-44e4ca36-4f21-4bf7-b160-216e361d3a99
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978187849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.978187849
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1834991593
Short name T813
Test name
Test status
Simulation time 491734681 ps
CPU time 17.6 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:16:11 PM PDT 24
Peak memory 249104 kb
Host smart-b951a2e7-d8b4-4385-8c29-2224eabc7441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834991593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1834991593
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3880339240
Short name T746
Test name
Test status
Simulation time 204428372 ps
CPU time 15.49 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:16:04 PM PDT 24
Peak memory 243688 kb
Host smart-11dcc013-b994-4916-b037-652202994cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880339240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3880339240
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1886315435
Short name T776
Test name
Test status
Simulation time 138774794 ps
CPU time 7.62 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 237612 kb
Host smart-001e6eb5-0295-4f23-86ef-c747c290377b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1886315435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1886315435
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.746256848
Short name T755
Test name
Test status
Simulation time 6312551 ps
CPU time 1.35 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 237596 kb
Host smart-fd0c6eac-fb67-4d02-af2d-5f1aafcb8c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746256848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.746256848
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2037991238
Short name T803
Test name
Test status
Simulation time 265933329 ps
CPU time 18.87 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:16:08 PM PDT 24
Peak memory 248732 kb
Host smart-482dadb5-1aec-4b31-a2af-ea3de13ab93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2037991238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2037991238
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3200052859
Short name T150
Test name
Test status
Simulation time 5844248751 ps
CPU time 450.28 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:23:26 PM PDT 24
Peak memory 265432 kb
Host smart-18e96615-028a-44f3-aa4e-a092a73a0356
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200052859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3200052859
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2745134936
Short name T738
Test name
Test status
Simulation time 173831346 ps
CPU time 5.73 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:15:51 PM PDT 24
Peak memory 252288 kb
Host smart-4e6c264f-6ed7-4631-b427-2d4fc75ba17e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745134936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2745134936
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1032677415
Short name T757
Test name
Test status
Simulation time 462092943 ps
CPU time 6.95 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 241092 kb
Host smart-a2fa3e2f-bf9d-4fa1-bb2d-0a8f84e7526c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032677415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1032677415
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1800351186
Short name T762
Test name
Test status
Simulation time 72059022 ps
CPU time 3.54 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:03 PM PDT 24
Peak memory 237612 kb
Host smart-342327c1-1275-4fa1-9856-92b2067decf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1800351186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1800351186
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1335799336
Short name T745
Test name
Test status
Simulation time 11735956 ps
CPU time 1.76 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:15:48 PM PDT 24
Peak memory 237732 kb
Host smart-902b41bf-68ea-4329-952d-8a6d996abc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1335799336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1335799336
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3426881975
Short name T768
Test name
Test status
Simulation time 513455093 ps
CPU time 35.25 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:33 PM PDT 24
Peak memory 245788 kb
Host smart-3faeb7d5-8d3e-4ab8-87ad-176c5602ea34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3426881975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3426881975
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1233667131
Short name T155
Test name
Test status
Simulation time 15279032763 ps
CPU time 326.4 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:21:14 PM PDT 24
Peak memory 265412 kb
Host smart-38398da5-43c9-4d30-894a-c54fa3b7afcc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233667131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1233667131
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2287895093
Short name T811
Test name
Test status
Simulation time 136389216 ps
CPU time 7.62 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:15:54 PM PDT 24
Peak memory 249584 kb
Host smart-a2c13232-db4e-4b9a-b13b-91e16c4e5e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2287895093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2287895093
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1142175011
Short name T774
Test name
Test status
Simulation time 768159252 ps
CPU time 14.03 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:13 PM PDT 24
Peak memory 251888 kb
Host smart-5b0ad45e-a645-4897-92f7-9fd86adb65a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142175011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1142175011
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2768315293
Short name T759
Test name
Test status
Simulation time 19508154 ps
CPU time 3.71 seconds
Started Jun 27 06:15:46 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 237624 kb
Host smart-0d249224-fa02-4be5-9292-12e3f2a6c4f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2768315293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2768315293
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.791572612
Short name T807
Test name
Test status
Simulation time 6398808 ps
CPU time 1.43 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 237636 kb
Host smart-259f2fe5-2193-4228-a2f6-75a898e99b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=791572612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.791572612
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2613693321
Short name T186
Test name
Test status
Simulation time 501313517 ps
CPU time 18.54 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:16:11 PM PDT 24
Peak memory 245824 kb
Host smart-2fea363a-b20e-40b4-b6f5-e7f2fde9b5d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2613693321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2613693321
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1271554468
Short name T137
Test name
Test status
Simulation time 4765926919 ps
CPU time 95.54 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:17:33 PM PDT 24
Peak memory 265488 kb
Host smart-c8a27f2d-0bfd-4716-b9a8-c541de550bf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1271554468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1271554468
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.480892438
Short name T750
Test name
Test status
Simulation time 412876159 ps
CPU time 13.43 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:11 PM PDT 24
Peak memory 256932 kb
Host smart-aa685368-13b0-4dcb-876d-539c40ca62fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=480892438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.480892438
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3950299524
Short name T765
Test name
Test status
Simulation time 1113162894 ps
CPU time 10.84 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:16:06 PM PDT 24
Peak memory 240616 kb
Host smart-c30004ad-29bc-43e6-bab1-3e91e6d8f9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950299524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3950299524
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1239239973
Short name T185
Test name
Test status
Simulation time 124270909 ps
CPU time 6.08 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:16:02 PM PDT 24
Peak memory 240544 kb
Host smart-31517864-cffb-4a98-ad37-e6406d4fb15e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1239239973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1239239973
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2002948877
Short name T787
Test name
Test status
Simulation time 25264500 ps
CPU time 1.5 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:51 PM PDT 24
Peak memory 237628 kb
Host smart-8b8692d5-cb5d-4da8-932b-3376a37a0a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2002948877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2002948877
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2756283813
Short name T814
Test name
Test status
Simulation time 324980065 ps
CPU time 12.96 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:10 PM PDT 24
Peak memory 245764 kb
Host smart-f0cd5653-c0d7-4e91-9a3d-7a9d9d1b8a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2756283813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2756283813
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1358890338
Short name T825
Test name
Test status
Simulation time 4212808243 ps
CPU time 217.17 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 265608 kb
Host smart-fd0ebff9-aa10-4d41-a18e-bcc4c997ed73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1358890338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1358890338
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3331896826
Short name T135
Test name
Test status
Simulation time 2177490429 ps
CPU time 316.86 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:21:13 PM PDT 24
Peak memory 265412 kb
Host smart-da92ae53-3482-40ec-8567-5913187ddfb2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331896826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3331896826
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.784002797
Short name T772
Test name
Test status
Simulation time 241487373 ps
CPU time 9.3 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 248496 kb
Host smart-88aaed4d-965c-43da-a26d-179ce8e39cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=784002797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.784002797
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.232074384
Short name T785
Test name
Test status
Simulation time 3482117914 ps
CPU time 255.83 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 241016 kb
Host smart-556beaac-e997-4b81-bc46-f91f6eddd175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=232074384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.232074384
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.157634583
Short name T754
Test name
Test status
Simulation time 17069292508 ps
CPU time 242.49 seconds
Started Jun 27 06:14:53 PM PDT 24
Finished Jun 27 06:18:56 PM PDT 24
Peak memory 237668 kb
Host smart-9a0689dd-88a9-41b3-af4e-9da26422c8b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=157634583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.157634583
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2682245569
Short name T237
Test name
Test status
Simulation time 81613114 ps
CPU time 4.28 seconds
Started Jun 27 06:14:57 PM PDT 24
Finished Jun 27 06:15:03 PM PDT 24
Peak memory 248716 kb
Host smart-e2cbfe18-269c-4372-a900-e135ca7982c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2682245569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2682245569
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.176128962
Short name T358
Test name
Test status
Simulation time 44726807 ps
CPU time 6.69 seconds
Started Jun 27 06:14:57 PM PDT 24
Finished Jun 27 06:15:05 PM PDT 24
Peak memory 240568 kb
Host smart-f5d86e5c-2f20-48bd-85b4-ec1c7710f16f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176128962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.176128962
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2956415075
Short name T189
Test name
Test status
Simulation time 36655441 ps
CPU time 4.48 seconds
Started Jun 27 06:14:57 PM PDT 24
Finished Jun 27 06:15:03 PM PDT 24
Peak memory 240564 kb
Host smart-da08ec3b-2434-44fb-ba4c-a21f43edb4a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2956415075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2956415075
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2050013880
Short name T826
Test name
Test status
Simulation time 13964237 ps
CPU time 1.3 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:09 PM PDT 24
Peak memory 236536 kb
Host smart-6cf1df39-75f7-4908-a946-83b82b8fdc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2050013880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2050013880
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1515006343
Short name T191
Test name
Test status
Simulation time 510092792 ps
CPU time 32.98 seconds
Started Jun 27 06:14:52 PM PDT 24
Finished Jun 27 06:15:26 PM PDT 24
Peak memory 244884 kb
Host smart-d2a2cade-d062-43a2-b157-e112414f250b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1515006343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1515006343
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3702939823
Short name T138
Test name
Test status
Simulation time 16956226300 ps
CPU time 300.29 seconds
Started Jun 27 06:14:51 PM PDT 24
Finished Jun 27 06:19:53 PM PDT 24
Peak memory 265500 kb
Host smart-7bf1ce34-264f-4991-97e9-08d5a02d8dd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3702939823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3702939823
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2972303941
Short name T126
Test name
Test status
Simulation time 8449329702 ps
CPU time 335.86 seconds
Started Jun 27 06:14:55 PM PDT 24
Finished Jun 27 06:20:32 PM PDT 24
Peak memory 265576 kb
Host smart-7d739c82-0a60-4028-bc4c-0b8f122b810d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972303941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2972303941
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1325311174
Short name T729
Test name
Test status
Simulation time 78123959 ps
CPU time 9.41 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:17 PM PDT 24
Peak memory 256304 kb
Host smart-ead62e2a-2036-4bfa-a5cb-5f127f042427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1325311174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1325311174
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2213867994
Short name T760
Test name
Test status
Simulation time 6298688 ps
CPU time 1.39 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 237588 kb
Host smart-85199a40-ecb9-47e1-a2aa-f9d7714117e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2213867994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2213867994
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2482231907
Short name T805
Test name
Test status
Simulation time 9903060 ps
CPU time 1.6 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 236556 kb
Host smart-1caa55f0-2ef6-40fa-a726-9e001035811f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2482231907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2482231907
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1099037053
Short name T356
Test name
Test status
Simulation time 13443412 ps
CPU time 1.35 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 237628 kb
Host smart-5ae0de79-6743-4dc2-a343-df1660f90f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1099037053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1099037053
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2905129617
Short name T784
Test name
Test status
Simulation time 13541262 ps
CPU time 1.37 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 236664 kb
Host smart-3c2cf551-b2ff-4709-b94d-d7534f77565b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2905129617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2905129617
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3503110226
Short name T162
Test name
Test status
Simulation time 17365926 ps
CPU time 1.36 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 235664 kb
Host smart-99f1321d-4fb8-485e-838d-703c8dbe9171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3503110226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3503110226
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2217195058
Short name T792
Test name
Test status
Simulation time 19243123 ps
CPU time 1.27 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 237596 kb
Host smart-6b9b610d-604b-4bf3-9c5f-055eb1c099c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217195058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2217195058
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3227748950
Short name T349
Test name
Test status
Simulation time 13046482 ps
CPU time 1.6 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 236664 kb
Host smart-9abc7ed5-ad18-459e-9357-8519abd893c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3227748950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3227748950
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4069841742
Short name T235
Test name
Test status
Simulation time 6788897 ps
CPU time 1.4 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 236720 kb
Host smart-8740af84-5b23-419b-8162-b679124bf893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4069841742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4069841742
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3586751047
Short name T744
Test name
Test status
Simulation time 17041549 ps
CPU time 1.39 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 236728 kb
Host smart-83a8e9f3-b7a0-4043-aa93-318464ca9e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3586751047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3586751047
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1730684468
Short name T802
Test name
Test status
Simulation time 1145007199 ps
CPU time 139.88 seconds
Started Jun 27 06:14:49 PM PDT 24
Finished Jun 27 06:17:10 PM PDT 24
Peak memory 241004 kb
Host smart-8654e120-65d2-4168-8334-3a0a8b5f6f4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1730684468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1730684468
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1816562585
Short name T735
Test name
Test status
Simulation time 124024795 ps
CPU time 9.75 seconds
Started Jun 27 06:14:47 PM PDT 24
Finished Jun 27 06:14:58 PM PDT 24
Peak memory 248776 kb
Host smart-537e3f5c-03d7-4b67-bb99-6b5136bb27b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1816562585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1816562585
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2767729053
Short name T360
Test name
Test status
Simulation time 459011199 ps
CPU time 11.79 seconds
Started Jun 27 06:14:56 PM PDT 24
Finished Jun 27 06:15:09 PM PDT 24
Peak memory 251872 kb
Host smart-4c96c8a5-7db5-4a50-8bf4-5bc643423d81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767729053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2767729053
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2969204472
Short name T363
Test name
Test status
Simulation time 93939741 ps
CPU time 8.4 seconds
Started Jun 27 06:14:50 PM PDT 24
Finished Jun 27 06:15:00 PM PDT 24
Peak memory 237620 kb
Host smart-e1e84d97-342a-42e7-8068-f1d35ac75adf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2969204472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2969204472
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2866687567
Short name T819
Test name
Test status
Simulation time 8465139 ps
CPU time 1.4 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:09 PM PDT 24
Peak memory 237604 kb
Host smart-00c7bd2b-19d5-436c-8ff0-b06274c3ba29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2866687567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2866687567
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4081500910
Short name T733
Test name
Test status
Simulation time 92078597 ps
CPU time 11.71 seconds
Started Jun 27 06:14:50 PM PDT 24
Finished Jun 27 06:15:03 PM PDT 24
Peak memory 240544 kb
Host smart-aeae6952-025c-4d39-9d3a-348a21199559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4081500910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4081500910
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.927892284
Short name T756
Test name
Test status
Simulation time 69767466 ps
CPU time 8.81 seconds
Started Jun 27 06:14:51 PM PDT 24
Finished Jun 27 06:15:01 PM PDT 24
Peak memory 254600 kb
Host smart-be7b7118-5505-480c-b8c3-9799139c9453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=927892284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.927892284
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2116942878
Short name T790
Test name
Test status
Simulation time 8750487 ps
CPU time 1.4 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 237632 kb
Host smart-4ddc2bf3-6ad1-4f62-8b3b-2dbfd8f4df1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116942878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2116942878
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2360087043
Short name T350
Test name
Test status
Simulation time 12518077 ps
CPU time 1.52 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 237612 kb
Host smart-fc2029f9-49b1-47ad-8117-082f99e984d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2360087043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2360087043
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3343613532
Short name T742
Test name
Test status
Simulation time 7258476 ps
CPU time 1.49 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:00 PM PDT 24
Peak memory 237600 kb
Host smart-430dcdaf-0da1-4eaa-b768-c335099a3d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343613532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3343613532
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2596770803
Short name T353
Test name
Test status
Simulation time 7357470 ps
CPU time 1.32 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 237628 kb
Host smart-566a8f2d-06d1-4d96-a7f3-af613fc6bbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2596770803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2596770803
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2074206858
Short name T799
Test name
Test status
Simulation time 14670934 ps
CPU time 1.42 seconds
Started Jun 27 06:15:44 PM PDT 24
Finished Jun 27 06:15:47 PM PDT 24
Peak memory 236840 kb
Host smart-2d925af9-6e3b-4176-b485-40ec4e56c358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074206858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2074206858
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.836225194
Short name T788
Test name
Test status
Simulation time 12138645 ps
CPU time 1.44 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:53 PM PDT 24
Peak memory 237628 kb
Host smart-e36d9e3e-8897-4288-94b8-f65e9ca5563b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=836225194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.836225194
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3690253391
Short name T771
Test name
Test status
Simulation time 25739033 ps
CPU time 1.48 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 236688 kb
Host smart-56bf9672-6739-4dd8-b48e-7ff5b6221d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3690253391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3690253391
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4173997669
Short name T740
Test name
Test status
Simulation time 21390969 ps
CPU time 1.38 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:16:00 PM PDT 24
Peak memory 237600 kb
Host smart-79e707bf-6f88-45c9-ab1a-df57bde46036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4173997669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4173997669
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.231577248
Short name T355
Test name
Test status
Simulation time 13484316 ps
CPU time 1.54 seconds
Started Jun 27 06:15:51 PM PDT 24
Finished Jun 27 06:15:59 PM PDT 24
Peak memory 237608 kb
Host smart-6e2c30a4-8f30-4ba6-8ce2-b4a4f0f8f151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=231577248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.231577248
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3948643757
Short name T734
Test name
Test status
Simulation time 2145512786 ps
CPU time 62.96 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:16:20 PM PDT 24
Peak memory 240568 kb
Host smart-0d4a3b17-2198-4f87-8b7e-acd0a130b5f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3948643757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3948643757
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3014286516
Short name T758
Test name
Test status
Simulation time 3406485275 ps
CPU time 113.61 seconds
Started Jun 27 06:15:02 PM PDT 24
Finished Jun 27 06:16:57 PM PDT 24
Peak memory 237644 kb
Host smart-61800682-ef2f-438b-98eb-45bf6a0cde6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3014286516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3014286516
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.776278125
Short name T731
Test name
Test status
Simulation time 53251270 ps
CPU time 5.52 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:15:13 PM PDT 24
Peak memory 248432 kb
Host smart-1d45f509-a585-450f-a4cf-db9ba59d86d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=776278125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.776278125
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3727270767
Short name T748
Test name
Test status
Simulation time 727982592 ps
CPU time 14.48 seconds
Started Jun 27 06:15:01 PM PDT 24
Finished Jun 27 06:15:17 PM PDT 24
Peak memory 256924 kb
Host smart-af773655-6cee-4609-abae-a2ca4a651523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727270767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3727270767
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3890115022
Short name T362
Test name
Test status
Simulation time 96775614 ps
CPU time 7.33 seconds
Started Jun 27 06:15:02 PM PDT 24
Finished Jun 27 06:15:11 PM PDT 24
Peak memory 240572 kb
Host smart-62b0b9a6-6c68-44df-85d2-92b07260946c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3890115022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3890115022
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1381060461
Short name T163
Test name
Test status
Simulation time 10374779 ps
CPU time 1.56 seconds
Started Jun 27 06:14:50 PM PDT 24
Finished Jun 27 06:14:53 PM PDT 24
Peak memory 236624 kb
Host smart-d56957a8-c5f6-4e24-8e5e-fc691f8e4152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1381060461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1381060461
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3557991673
Short name T188
Test name
Test status
Simulation time 179192729 ps
CPU time 24.4 seconds
Started Jun 27 06:15:01 PM PDT 24
Finished Jun 27 06:15:26 PM PDT 24
Peak memory 248744 kb
Host smart-21dd7ce9-de96-4af1-acc3-e37eed53ed78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3557991673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3557991673
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4161975027
Short name T145
Test name
Test status
Simulation time 11077692065 ps
CPU time 189.52 seconds
Started Jun 27 06:15:06 PM PDT 24
Finished Jun 27 06:18:17 PM PDT 24
Peak memory 265364 kb
Host smart-671433e0-2a46-4549-9f88-ee9055a37b9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4161975027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.4161975027
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.373606375
Short name T148
Test name
Test status
Simulation time 28566378158 ps
CPU time 328.85 seconds
Started Jun 27 06:14:55 PM PDT 24
Finished Jun 27 06:20:25 PM PDT 24
Peak memory 265432 kb
Host smart-017e289c-38fd-4928-bb09-3dd285d448c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373606375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.373606375
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1213342567
Short name T773
Test name
Test status
Simulation time 428170716 ps
CPU time 7.38 seconds
Started Jun 27 06:14:47 PM PDT 24
Finished Jun 27 06:14:56 PM PDT 24
Peak memory 248840 kb
Host smart-28f3f79b-a37e-4464-b0f7-48f8435d86b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1213342567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1213342567
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4070428550
Short name T352
Test name
Test status
Simulation time 68019362 ps
CPU time 1.38 seconds
Started Jun 27 06:15:50 PM PDT 24
Finished Jun 27 06:15:58 PM PDT 24
Peak memory 236692 kb
Host smart-eda7afba-2ee4-434f-8e95-680c439c7ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4070428550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4070428550
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3344651813
Short name T357
Test name
Test status
Simulation time 9461897 ps
CPU time 1.3 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:15:49 PM PDT 24
Peak memory 235680 kb
Host smart-0db861d8-bba3-4be8-aabf-a8f32ee262f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3344651813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3344651813
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.392690301
Short name T798
Test name
Test status
Simulation time 7500397 ps
CPU time 1.26 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:51 PM PDT 24
Peak memory 237620 kb
Host smart-37f65864-f6a6-41cd-bfed-fd3fd2f4de63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=392690301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.392690301
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1215213937
Short name T763
Test name
Test status
Simulation time 13247648 ps
CPU time 1.41 seconds
Started Jun 27 06:15:52 PM PDT 24
Finished Jun 27 06:16:01 PM PDT 24
Peak memory 236676 kb
Host smart-78e69eb4-8c38-41b9-8b0c-0a8433dc4bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215213937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1215213937
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.998937497
Short name T827
Test name
Test status
Simulation time 12879400 ps
CPU time 1.24 seconds
Started Jun 27 06:15:47 PM PDT 24
Finished Jun 27 06:15:52 PM PDT 24
Peak memory 237612 kb
Host smart-1373425e-3c6f-4ade-8749-c2363971a65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=998937497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.998937497
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3713499692
Short name T820
Test name
Test status
Simulation time 18987833 ps
CPU time 1.43 seconds
Started Jun 27 06:15:55 PM PDT 24
Finished Jun 27 06:16:03 PM PDT 24
Peak memory 236604 kb
Host smart-bd020e91-2397-4ceb-9a0f-2b538a3a38c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3713499692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3713499692
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2278989866
Short name T766
Test name
Test status
Simulation time 8586362 ps
CPU time 1.46 seconds
Started Jun 27 06:15:55 PM PDT 24
Finished Jun 27 06:16:03 PM PDT 24
Peak memory 236636 kb
Host smart-9942e966-56f9-4016-b8f9-0b7f5f4dddc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2278989866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2278989866
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.628182586
Short name T800
Test name
Test status
Simulation time 8181086 ps
CPU time 1.44 seconds
Started Jun 27 06:15:45 PM PDT 24
Finished Jun 27 06:15:48 PM PDT 24
Peak memory 236700 kb
Host smart-2512e81c-dabc-497d-8439-47ccb3a33d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628182586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.628182586
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3742123135
Short name T753
Test name
Test status
Simulation time 20084759 ps
CPU time 1.52 seconds
Started Jun 27 06:15:49 PM PDT 24
Finished Jun 27 06:15:56 PM PDT 24
Peak memory 237616 kb
Host smart-5b2958ca-44e9-4720-bb49-c09ecb6384db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3742123135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3742123135
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2140023367
Short name T351
Test name
Test status
Simulation time 21547961 ps
CPU time 1.49 seconds
Started Jun 27 06:15:48 PM PDT 24
Finished Jun 27 06:15:55 PM PDT 24
Peak memory 236664 kb
Host smart-fb2ac458-5d82-4917-b78e-4af799bb9988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2140023367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2140023367
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1979039708
Short name T180
Test name
Test status
Simulation time 191095604 ps
CPU time 4.34 seconds
Started Jun 27 06:15:09 PM PDT 24
Finished Jun 27 06:15:14 PM PDT 24
Peak memory 240536 kb
Host smart-013043a1-a17a-405b-ad53-6c4ea4f87ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979039708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1979039708
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.101665565
Short name T178
Test name
Test status
Simulation time 103383764 ps
CPU time 6.85 seconds
Started Jun 27 06:15:02 PM PDT 24
Finished Jun 27 06:15:10 PM PDT 24
Peak memory 237736 kb
Host smart-8c938254-0468-42f4-abe5-6ce72343c69a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=101665565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.101665565
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3149902181
Short name T782
Test name
Test status
Simulation time 13451001 ps
CPU time 1.42 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:15:18 PM PDT 24
Peak memory 236684 kb
Host smart-27574f4a-15f8-45b2-9534-0ee7316e8bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149902181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3149902181
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3683123927
Short name T727
Test name
Test status
Simulation time 2026020964 ps
CPU time 35.34 seconds
Started Jun 27 06:15:02 PM PDT 24
Finished Jun 27 06:15:39 PM PDT 24
Peak memory 248780 kb
Host smart-1296dddd-629f-4592-a8ea-57d7c7163f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3683123927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3683123927
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2632580915
Short name T146
Test name
Test status
Simulation time 7359327115 ps
CPU time 187.24 seconds
Started Jun 27 06:15:01 PM PDT 24
Finished Jun 27 06:18:09 PM PDT 24
Peak memory 273356 kb
Host smart-b1f329bd-ed68-4559-8240-d966890f80ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2632580915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2632580915
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1216691051
Short name T747
Test name
Test status
Simulation time 109367829 ps
CPU time 9.01 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:15:26 PM PDT 24
Peak memory 247444 kb
Host smart-5c959894-2141-44aa-a466-ab34c38766ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1216691051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1216691051
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2680742521
Short name T801
Test name
Test status
Simulation time 117934846 ps
CPU time 4.83 seconds
Started Jun 27 06:15:30 PM PDT 24
Finished Jun 27 06:15:36 PM PDT 24
Peak memory 240580 kb
Host smart-196af9ac-59bf-4d0a-b394-c2eb465ca71b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680742521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2680742521
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1735523377
Short name T361
Test name
Test status
Simulation time 56411192 ps
CPU time 5.27 seconds
Started Jun 27 06:15:28 PM PDT 24
Finished Jun 27 06:15:34 PM PDT 24
Peak memory 236668 kb
Host smart-299e1af1-42dc-4db5-8fa5-59b74a6e8a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1735523377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1735523377
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3879167481
Short name T741
Test name
Test status
Simulation time 13430635 ps
CPU time 1.44 seconds
Started Jun 27 06:15:22 PM PDT 24
Finished Jun 27 06:15:24 PM PDT 24
Peak memory 237636 kb
Host smart-ac6db75e-feb3-4a3f-b21c-3909a3474961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3879167481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3879167481
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1027071651
Short name T795
Test name
Test status
Simulation time 526781063 ps
CPU time 41.75 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:16:09 PM PDT 24
Peak memory 245824 kb
Host smart-04c66198-e319-45fd-a38f-fa7d3413726f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1027071651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1027071651
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2650018245
Short name T144
Test name
Test status
Simulation time 819081940 ps
CPU time 96.64 seconds
Started Jun 27 06:15:16 PM PDT 24
Finished Jun 27 06:16:54 PM PDT 24
Peak memory 265424 kb
Host smart-5abeb5b7-6ccd-411f-b1cd-710be5ace27c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2650018245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2650018245
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3909083078
Short name T136
Test name
Test status
Simulation time 31225403102 ps
CPU time 554.96 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 265620 kb
Host smart-c1a026f2-182c-48b1-a679-091ba82d438b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909083078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3909083078
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2728678366
Short name T725
Test name
Test status
Simulation time 686728537 ps
CPU time 14.16 seconds
Started Jun 27 06:15:15 PM PDT 24
Finished Jun 27 06:15:31 PM PDT 24
Peak memory 248832 kb
Host smart-d4de9092-30f8-45ef-a4a6-cf9088c3d47b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728678366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2728678366
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3544681524
Short name T761
Test name
Test status
Simulation time 152853534 ps
CPU time 11.6 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:15:39 PM PDT 24
Peak memory 251912 kb
Host smart-5565a803-83c3-40ae-bfcb-c8bd7bf0ad4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544681524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3544681524
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1009056371
Short name T739
Test name
Test status
Simulation time 110190387 ps
CPU time 8.48 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:15:35 PM PDT 24
Peak memory 237600 kb
Host smart-31139385-e847-4628-85d2-9495303c9ed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1009056371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1009056371
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.35483412
Short name T806
Test name
Test status
Simulation time 9678174 ps
CPU time 1.65 seconds
Started Jun 27 06:15:23 PM PDT 24
Finished Jun 27 06:15:26 PM PDT 24
Peak memory 236644 kb
Host smart-d980358a-99af-48cf-bf2a-763efbd2ff13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=35483412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.35483412
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2586987345
Short name T243
Test name
Test status
Simulation time 1331872768 ps
CPU time 19.78 seconds
Started Jun 27 06:15:21 PM PDT 24
Finished Jun 27 06:15:42 PM PDT 24
Peak memory 244860 kb
Host smart-cba07a5e-8b5e-4692-af60-f90013208097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2586987345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2586987345
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3233303620
Short name T139
Test name
Test status
Simulation time 23385542786 ps
CPU time 488.74 seconds
Started Jun 27 06:15:26 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 266456 kb
Host smart-1fe0c201-48f4-4e88-a780-e8da10141867
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233303620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3233303620
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.943526182
Short name T726
Test name
Test status
Simulation time 193796365 ps
CPU time 14.45 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:15:45 PM PDT 24
Peak memory 253388 kb
Host smart-d8978bc6-bbe4-44a1-8a9f-5187fdd222b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=943526182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.943526182
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.886292911
Short name T796
Test name
Test status
Simulation time 144854015 ps
CPU time 10.49 seconds
Started Jun 27 06:15:31 PM PDT 24
Finished Jun 27 06:15:42 PM PDT 24
Peak memory 238148 kb
Host smart-e16c16e7-efc5-4b50-bf64-e4cd19d400f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886292911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.886292911
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2306110076
Short name T736
Test name
Test status
Simulation time 41185875 ps
CPU time 4.78 seconds
Started Jun 27 06:15:21 PM PDT 24
Finished Jun 27 06:15:26 PM PDT 24
Peak memory 236640 kb
Host smart-e7f49e07-48b8-4347-9dda-c3ec7fb4cfd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2306110076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2306110076
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.923880992
Short name T818
Test name
Test status
Simulation time 15673736 ps
CPU time 1.46 seconds
Started Jun 27 06:15:32 PM PDT 24
Finished Jun 27 06:15:34 PM PDT 24
Peak memory 237628 kb
Host smart-dc31bd41-b9f4-447c-98b4-9947fc36a4bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=923880992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.923880992
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2635677979
Short name T190
Test name
Test status
Simulation time 729724711 ps
CPU time 20.49 seconds
Started Jun 27 06:15:23 PM PDT 24
Finished Jun 27 06:15:45 PM PDT 24
Peak memory 244880 kb
Host smart-e0aeca89-e47d-4014-8fb3-2f742178c1e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2635677979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2635677979
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3369633883
Short name T142
Test name
Test status
Simulation time 17286127869 ps
CPU time 633.23 seconds
Started Jun 27 06:15:24 PM PDT 24
Finished Jun 27 06:25:58 PM PDT 24
Peak memory 273632 kb
Host smart-0cce4a03-a036-49a8-8150-e931be92b257
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369633883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3369633883
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2450420155
Short name T808
Test name
Test status
Simulation time 368613050 ps
CPU time 8.05 seconds
Started Jun 27 06:15:22 PM PDT 24
Finished Jun 27 06:15:31 PM PDT 24
Peak memory 248684 kb
Host smart-2691f96a-7e32-4e00-b928-a9ebf3025036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2450420155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2450420155
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2409203311
Short name T246
Test name
Test status
Simulation time 277281739 ps
CPU time 5.65 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:15:32 PM PDT 24
Peak memory 239572 kb
Host smart-105057fe-8344-4738-ac56-8c4db96a2f0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409203311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2409203311
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2476014648
Short name T810
Test name
Test status
Simulation time 63519993 ps
CPU time 5.18 seconds
Started Jun 27 06:15:30 PM PDT 24
Finished Jun 27 06:15:36 PM PDT 24
Peak memory 237576 kb
Host smart-d45b2266-dc06-440b-b873-fb5b8305c4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2476014648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2476014648
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3298144772
Short name T778
Test name
Test status
Simulation time 22574074 ps
CPU time 1.36 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:15:31 PM PDT 24
Peak memory 237504 kb
Host smart-9a229fe7-6bbd-48bb-b47e-842cdbb7c31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3298144772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3298144772
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1207796725
Short name T732
Test name
Test status
Simulation time 404523808 ps
CPU time 13.42 seconds
Started Jun 27 06:15:29 PM PDT 24
Finished Jun 27 06:15:44 PM PDT 24
Peak memory 245800 kb
Host smart-de29c546-1c74-44c2-ac0a-e28a958e5d8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1207796725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1207796725
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3333077049
Short name T133
Test name
Test status
Simulation time 2402505437 ps
CPU time 307.89 seconds
Started Jun 27 06:15:21 PM PDT 24
Finished Jun 27 06:20:30 PM PDT 24
Peak memory 267252 kb
Host smart-ca8c298e-dc15-4b71-8ab4-2010b179bff7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333077049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3333077049
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3300954992
Short name T821
Test name
Test status
Simulation time 416967692 ps
CPU time 8.52 seconds
Started Jun 27 06:15:25 PM PDT 24
Finished Jun 27 06:15:35 PM PDT 24
Peak memory 249852 kb
Host smart-ef994b90-7525-42c0-b690-7feb8ece710d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300954992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3300954992
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2823774391
Short name T54
Test name
Test status
Simulation time 35750103235 ps
CPU time 2253.74 seconds
Started Jun 27 05:23:16 PM PDT 24
Finished Jun 27 06:00:52 PM PDT 24
Peak memory 290012 kb
Host smart-6bc34f17-a4e5-46b1-ae61-4b8acc7e57e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823774391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2823774391
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3286608466
Short name T498
Test name
Test status
Simulation time 773368316 ps
CPU time 11.91 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:23:35 PM PDT 24
Peak memory 249292 kb
Host smart-51385c99-6404-4675-a2a6-c6439e373659
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3286608466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3286608466
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1051504672
Short name T451
Test name
Test status
Simulation time 12232303599 ps
CPU time 132.09 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:25:26 PM PDT 24
Peak memory 257168 kb
Host smart-8305f8d8-2ac9-4346-b9e6-227a96f78491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
04672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1051504672
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3641294958
Short name T680
Test name
Test status
Simulation time 1099969918 ps
CPU time 19.34 seconds
Started Jun 27 05:23:17 PM PDT 24
Finished Jun 27 05:23:37 PM PDT 24
Peak memory 249240 kb
Host smart-603a6485-5cfc-4fb6-949b-1a854c0ca024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
94958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3641294958
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2871759376
Short name T521
Test name
Test status
Simulation time 11927622717 ps
CPU time 1002.17 seconds
Started Jun 27 05:23:20 PM PDT 24
Finished Jun 27 05:40:04 PM PDT 24
Peak memory 287284 kb
Host smart-c11841de-ea70-4d0c-9674-9afacd229517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871759376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2871759376
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1619664684
Short name T684
Test name
Test status
Simulation time 6800367833 ps
CPU time 261.47 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:27:38 PM PDT 24
Peak memory 249312 kb
Host smart-19b85bae-8083-4f78-9258-dd09b4cacc69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619664684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1619664684
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.299838893
Short name T309
Test name
Test status
Simulation time 4119533468 ps
CPU time 34.14 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:23:50 PM PDT 24
Peak memory 257112 kb
Host smart-20196c56-e64d-4a11-a3ab-ac72b2c04d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
8893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.299838893
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3084957032
Short name T666
Test name
Test status
Simulation time 1282646739 ps
CPU time 32.88 seconds
Started Jun 27 05:23:11 PM PDT 24
Finished Jun 27 05:23:46 PM PDT 24
Peak memory 249232 kb
Host smart-a46ba920-c48a-479b-a43e-936655319594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
57032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3084957032
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1442192641
Short name T437
Test name
Test status
Simulation time 752313701 ps
CPU time 19.4 seconds
Started Jun 27 05:23:22 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 249788 kb
Host smart-35b57c4c-9ae1-4ac2-8ca8-ef61a4becbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
92641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1442192641
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3533893238
Short name T519
Test name
Test status
Simulation time 138815737132 ps
CPU time 2286.92 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 06:01:23 PM PDT 24
Peak memory 289920 kb
Host smart-aac7c076-edb4-471c-9ce9-3ecec8e782c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533893238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3533893238
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1739450380
Short name T639
Test name
Test status
Simulation time 186434091901 ps
CPU time 1418.55 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:46:55 PM PDT 24
Peak memory 273820 kb
Host smart-2a6e0e6d-f8ba-41e6-8bdc-8a2b5b986cbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739450380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1739450380
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.401527126
Short name T551
Test name
Test status
Simulation time 1522055010 ps
CPU time 19.42 seconds
Started Jun 27 05:23:16 PM PDT 24
Finished Jun 27 05:23:37 PM PDT 24
Peak memory 249292 kb
Host smart-a8e171bb-9429-4aeb-9f3b-a8fe8e819f02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=401527126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.401527126
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.940024832
Short name T595
Test name
Test status
Simulation time 3112031040 ps
CPU time 63.81 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:24:18 PM PDT 24
Peak memory 257532 kb
Host smart-d35bc3a9-723f-4a64-8d8a-e51a02c2a651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94002
4832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.940024832
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.613339401
Short name T548
Test name
Test status
Simulation time 5021212235 ps
CPU time 29.93 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:23:53 PM PDT 24
Peak memory 249328 kb
Host smart-c754dc4b-f58c-4232-a2ce-c9d00fc24ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61333
9401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.613339401
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3117440712
Short name T4
Test name
Test status
Simulation time 78143531985 ps
CPU time 1582.48 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:49:45 PM PDT 24
Peak memory 287000 kb
Host smart-d58c0726-73f7-41d1-a818-022c2a40ef19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117440712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3117440712
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.418624101
Short name T697
Test name
Test status
Simulation time 83102176637 ps
CPU time 2304.45 seconds
Started Jun 27 05:23:20 PM PDT 24
Finished Jun 27 06:01:46 PM PDT 24
Peak memory 283992 kb
Host smart-6e431589-8918-4e72-bbbc-6a248742b78b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418624101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.418624101
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.57687376
Short name T505
Test name
Test status
Simulation time 806559984 ps
CPU time 20.91 seconds
Started Jun 27 05:23:16 PM PDT 24
Finished Jun 27 05:23:39 PM PDT 24
Peak memory 256508 kb
Host smart-a746d462-6135-43f1-a548-eedd23746b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57687
376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.57687376
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1816268289
Short name T457
Test name
Test status
Simulation time 225576130 ps
CPU time 12.51 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:23:28 PM PDT 24
Peak memory 248764 kb
Host smart-da5ce8ab-37cf-4b30-be06-581b6afe7325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
68289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1816268289
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1179163827
Short name T14
Test name
Test status
Simulation time 476143360 ps
CPU time 14.67 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:23:38 PM PDT 24
Peak memory 271084 kb
Host smart-0f6d5377-3fc1-433d-9c8f-9fb5acedb91d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1179163827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1179163827
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2947821382
Short name T72
Test name
Test status
Simulation time 438308148 ps
CPU time 13.59 seconds
Started Jun 27 05:23:20 PM PDT 24
Finished Jun 27 05:23:35 PM PDT 24
Peak memory 256456 kb
Host smart-08efe5d8-d9a5-40b1-9d8e-8fb99c792385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
21382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2947821382
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.793167342
Short name T401
Test name
Test status
Simulation time 3169504164 ps
CPU time 48.81 seconds
Started Jun 27 05:23:16 PM PDT 24
Finished Jun 27 05:24:06 PM PDT 24
Peak memory 257592 kb
Host smart-845e5720-1889-4b64-ac91-9d8b480a1684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79316
7342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.793167342
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1825407790
Short name T220
Test name
Test status
Simulation time 103966496533 ps
CPU time 4288.65 seconds
Started Jun 27 05:23:18 PM PDT 24
Finished Jun 27 06:34:48 PM PDT 24
Peak memory 298348 kb
Host smart-294844d4-6bdc-4cc1-a3c3-e1ac8f935482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825407790 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1825407790
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2632177526
Short name T698
Test name
Test status
Simulation time 71892976507 ps
CPU time 1191.3 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 05:44:17 PM PDT 24
Peak memory 272704 kb
Host smart-b4c1f100-8364-4986-a431-335dcb6cec91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632177526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2632177526
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3927793826
Short name T589
Test name
Test status
Simulation time 3886314772 ps
CPU time 248.6 seconds
Started Jun 27 05:24:30 PM PDT 24
Finished Jun 27 05:28:39 PM PDT 24
Peak memory 257380 kb
Host smart-9d7e1032-e659-4a3c-8b7e-c43160d4436c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39277
93826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3927793826
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3036039544
Short name T261
Test name
Test status
Simulation time 3027034794 ps
CPU time 28.93 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:24:53 PM PDT 24
Peak memory 249356 kb
Host smart-5a7efec3-f7c6-48fc-92a0-67040b86f88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30360
39544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3036039544
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2374287710
Short name T421
Test name
Test status
Simulation time 87724849632 ps
CPU time 1312.07 seconds
Started Jun 27 05:24:25 PM PDT 24
Finished Jun 27 05:46:18 PM PDT 24
Peak memory 287380 kb
Host smart-b9dfc38e-0612-4d4d-a03f-4be19693c03b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374287710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2374287710
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2852372320
Short name T674
Test name
Test status
Simulation time 42238453645 ps
CPU time 149.51 seconds
Started Jun 27 05:24:25 PM PDT 24
Finished Jun 27 05:26:56 PM PDT 24
Peak memory 249356 kb
Host smart-00a58dde-1f42-4000-88d1-a957cafc479a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852372320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2852372320
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.242530745
Short name T367
Test name
Test status
Simulation time 72619279 ps
CPU time 6.86 seconds
Started Jun 27 05:24:25 PM PDT 24
Finished Jun 27 05:24:33 PM PDT 24
Peak memory 249300 kb
Host smart-c6a1bd57-963d-4438-b540-c59aebd9548e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
0745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.242530745
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1359619816
Short name T265
Test name
Test status
Simulation time 1723987370 ps
CPU time 14.01 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:24:38 PM PDT 24
Peak memory 248656 kb
Host smart-d9a16f13-be37-4fed-be52-31c28f7c42da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13596
19816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1359619816
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.21101768
Short name T257
Test name
Test status
Simulation time 1226334618 ps
CPU time 80.81 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:25:44 PM PDT 24
Peak memory 250208 kb
Host smart-751b4b6d-f554-49d3-9d2d-e20eaa4d392c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21101
768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.21101768
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.648696934
Short name T452
Test name
Test status
Simulation time 1289797073 ps
CPU time 19.81 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:24:43 PM PDT 24
Peak memory 255852 kb
Host smart-799588b0-2e3b-4c07-8342-621a3e8a6657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64869
6934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.648696934
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3389274445
Short name T52
Test name
Test status
Simulation time 20359803117 ps
CPU time 1431.2 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:48:16 PM PDT 24
Peak memory 273704 kb
Host smart-a396fcd0-b632-41fb-a75b-a6eae48f3895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389274445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3389274445
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2781453012
Short name T557
Test name
Test status
Simulation time 134697209 ps
CPU time 9.57 seconds
Started Jun 27 05:24:22 PM PDT 24
Finished Jun 27 05:24:33 PM PDT 24
Peak memory 249212 kb
Host smart-8e96126e-f05d-46a1-b02a-ed42d06de847
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2781453012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2781453012
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1851433341
Short name T721
Test name
Test status
Simulation time 17724564892 ps
CPU time 243.42 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 05:28:28 PM PDT 24
Peak memory 257600 kb
Host smart-336a042f-4c7f-459f-82fc-288248379ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18514
33341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1851433341
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1169662001
Short name T525
Test name
Test status
Simulation time 607909709 ps
CPU time 13.25 seconds
Started Jun 27 05:24:25 PM PDT 24
Finished Jun 27 05:24:40 PM PDT 24
Peak memory 248528 kb
Host smart-849c25dc-210a-42af-bcfd-f3e45a8822c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11696
62001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1169662001
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1544896589
Short name T347
Test name
Test status
Simulation time 41166199732 ps
CPU time 2148.61 seconds
Started Jun 27 05:24:25 PM PDT 24
Finished Jun 27 06:00:15 PM PDT 24
Peak memory 287244 kb
Host smart-d380eb16-a123-4daa-8992-2c5e9d012619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544896589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1544896589
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.620826208
Short name T559
Test name
Test status
Simulation time 204012967932 ps
CPU time 2040.06 seconds
Started Jun 27 05:24:28 PM PDT 24
Finished Jun 27 05:58:29 PM PDT 24
Peak memory 289000 kb
Host smart-ce1ad92f-60f4-4ef7-a4f8-bf9dafb31e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620826208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.620826208
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.857239706
Short name T396
Test name
Test status
Simulation time 2438829484 ps
CPU time 70.36 seconds
Started Jun 27 05:24:28 PM PDT 24
Finished Jun 27 05:25:39 PM PDT 24
Peak memory 257116 kb
Host smart-1ff39549-0df4-42e5-986c-eb6fa8c4f4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85723
9706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.857239706
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2139649880
Short name T630
Test name
Test status
Simulation time 277014094 ps
CPU time 29.27 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:24:57 PM PDT 24
Peak memory 248852 kb
Host smart-a3302374-056e-4d08-847b-87501654738b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
49880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2139649880
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2752686591
Short name T691
Test name
Test status
Simulation time 3405982522 ps
CPU time 42.67 seconds
Started Jun 27 05:24:24 PM PDT 24
Finished Jun 27 05:25:08 PM PDT 24
Peak memory 257412 kb
Host smart-f5710a02-4844-42e1-b87b-b95871e7ca23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526
86591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2752686591
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2139518354
Short name T692
Test name
Test status
Simulation time 308652874 ps
CPU time 29.2 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:24:57 PM PDT 24
Peak memory 257452 kb
Host smart-6bed84fb-42c7-465e-9abd-71560de9a1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
18354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2139518354
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1896785554
Short name T204
Test name
Test status
Simulation time 137194061 ps
CPU time 2.19 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:24:45 PM PDT 24
Peak memory 249556 kb
Host smart-e0feca19-0b1d-43af-be4c-32897301264f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1896785554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1896785554
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4023345941
Short name T508
Test name
Test status
Simulation time 5972390810 ps
CPU time 23.1 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 249596 kb
Host smart-eed4ae09-5621-46e1-bac3-3b36cf9ce1cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4023345941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4023345941
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1431219444
Short name T576
Test name
Test status
Simulation time 2360793128 ps
CPU time 97.68 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:26:21 PM PDT 24
Peak memory 256968 kb
Host smart-1c2beaa8-9f73-4df6-99d4-3ca495627320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
19444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1431219444
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.204300719
Short name T627
Test name
Test status
Simulation time 467984252 ps
CPU time 24.11 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:25:08 PM PDT 24
Peak memory 248996 kb
Host smart-80cc5d73-179a-4e38-a707-eca1d37d5590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20430
0719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.204300719
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2087155598
Short name T64
Test name
Test status
Simulation time 74825477656 ps
CPU time 1341.09 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:47:04 PM PDT 24
Peak memory 273812 kb
Host smart-b99565d4-fff6-4423-9acb-59a25d560932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087155598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2087155598
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2583277003
Short name T291
Test name
Test status
Simulation time 24557194818 ps
CPU time 458.36 seconds
Started Jun 27 05:24:41 PM PDT 24
Finished Jun 27 05:32:21 PM PDT 24
Peak memory 249324 kb
Host smart-7d2d36bb-0d6a-4954-9f0d-e6c730d9e003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583277003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2583277003
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.832129262
Short name T193
Test name
Test status
Simulation time 337652616 ps
CPU time 8.97 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:24:52 PM PDT 24
Peak memory 253884 kb
Host smart-016088a7-a8fe-43e8-bdbd-1549d06b20ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83212
9262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.832129262
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1904121101
Short name T675
Test name
Test status
Simulation time 341578724 ps
CPU time 28.35 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:25:14 PM PDT 24
Peak memory 257456 kb
Host smart-64ca430b-6aa6-4904-810d-418464d22b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
21101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1904121101
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3055563519
Short name T436
Test name
Test status
Simulation time 957717812 ps
CPU time 61.67 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:25:45 PM PDT 24
Peak memory 249208 kb
Host smart-efdafbef-bf6a-44d8-9ae1-851f137866bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30555
63519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3055563519
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3886571003
Short name T207
Test name
Test status
Simulation time 65070700 ps
CPU time 3.03 seconds
Started Jun 27 05:24:46 PM PDT 24
Finished Jun 27 05:24:50 PM PDT 24
Peak memory 249544 kb
Host smart-d4749b51-6e73-45f3-843f-43bd8f2c4542
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3886571003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3886571003
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.532731636
Short name T66
Test name
Test status
Simulation time 7710942074 ps
CPU time 880.48 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:39:26 PM PDT 24
Peak memory 273916 kb
Host smart-4f4118f9-2e9c-4172-aeb8-407444b72e70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532731636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.532731636
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3780532757
Short name T651
Test name
Test status
Simulation time 274929227 ps
CPU time 13.9 seconds
Started Jun 27 05:24:45 PM PDT 24
Finished Jun 27 05:25:00 PM PDT 24
Peak memory 249296 kb
Host smart-d172f947-953a-4a5a-ad9d-916dd28c3ecc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3780532757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3780532757
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1976211314
Short name T620
Test name
Test status
Simulation time 4442835721 ps
CPU time 70.33 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:25:54 PM PDT 24
Peak memory 256884 kb
Host smart-0ee292c7-e887-4f1d-8429-68f260c33085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19762
11314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1976211314
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2765894853
Short name T79
Test name
Test status
Simulation time 3657859163 ps
CPU time 54.17 seconds
Started Jun 27 05:24:46 PM PDT 24
Finished Jun 27 05:25:42 PM PDT 24
Peak memory 249436 kb
Host smart-598b6149-e9de-4c21-b8fc-b29b15dd4a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
94853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2765894853
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3239817786
Short name T339
Test name
Test status
Simulation time 953753217977 ps
CPU time 2825.9 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 06:11:49 PM PDT 24
Peak memory 289392 kb
Host smart-ea754595-4cb8-41c6-bc9c-54d098255f39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239817786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3239817786
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.329503411
Short name T687
Test name
Test status
Simulation time 12216024463 ps
CPU time 1431.78 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:48:36 PM PDT 24
Peak memory 289644 kb
Host smart-4d2ae264-0284-49f0-b582-f4c1f7c3bb56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329503411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.329503411
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1720160381
Short name T306
Test name
Test status
Simulation time 16879336004 ps
CPU time 171.95 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:27:37 PM PDT 24
Peak memory 249244 kb
Host smart-9c8a8492-da4d-4730-84bb-92aa8c85b157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720160381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1720160381
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3429182943
Short name T386
Test name
Test status
Simulation time 791351074 ps
CPU time 15.13 seconds
Started Jun 27 05:24:45 PM PDT 24
Finished Jun 27 05:25:02 PM PDT 24
Peak memory 256512 kb
Host smart-ff80a24e-4d07-4c63-ae53-9d3dacf61925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
82943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3429182943
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3251691228
Short name T599
Test name
Test status
Simulation time 1701802933 ps
CPU time 77.96 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:26:03 PM PDT 24
Peak memory 257076 kb
Host smart-8e3d245e-d297-47a6-94ff-8e28d9189037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32516
91228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3251691228
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.506379175
Short name T118
Test name
Test status
Simulation time 1521388351 ps
CPU time 20.97 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 257424 kb
Host smart-36807b59-ded2-42e0-89c5-8edb69d0fe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50637
9175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.506379175
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.296954131
Short name T585
Test name
Test status
Simulation time 51735386299 ps
CPU time 992.09 seconds
Started Jun 27 05:24:45 PM PDT 24
Finished Jun 27 05:41:18 PM PDT 24
Peak memory 287328 kb
Host smart-c6a719c4-70dd-4d9b-a163-8866ab14c27a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296954131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.296954131
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1637893692
Short name T212
Test name
Test status
Simulation time 101052714 ps
CPU time 2.47 seconds
Started Jun 27 05:25:09 PM PDT 24
Finished Jun 27 05:25:12 PM PDT 24
Peak memory 249592 kb
Host smart-86c9503b-5cd4-451e-a8d6-4235f461b8c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1637893692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1637893692
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2547110135
Short name T382
Test name
Test status
Simulation time 34047453279 ps
CPU time 1288.04 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:46:12 PM PDT 24
Peak memory 289704 kb
Host smart-bf9934d1-c328-4ef4-bd72-6bb56500626f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547110135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2547110135
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1180975254
Short name T388
Test name
Test status
Simulation time 429119070 ps
CPU time 13.9 seconds
Started Jun 27 05:25:13 PM PDT 24
Finished Jun 27 05:25:29 PM PDT 24
Peak memory 249324 kb
Host smart-a3e968af-2b43-4952-b1fb-dd8a07597b87
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180975254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1180975254
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2860332990
Short name T642
Test name
Test status
Simulation time 8973167927 ps
CPU time 74.76 seconds
Started Jun 27 05:24:42 PM PDT 24
Finished Jun 27 05:25:58 PM PDT 24
Peak memory 256844 kb
Host smart-63c32bd0-2cb5-4bf4-9646-c28e0633c7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
32990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2860332990
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1014490463
Short name T373
Test name
Test status
Simulation time 5677880306 ps
CPU time 57.07 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:25:43 PM PDT 24
Peak memory 256600 kb
Host smart-1f70788b-c5bb-4a94-a517-6f9734e2cd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
90463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1014490463
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1296591762
Short name T278
Test name
Test status
Simulation time 45704874384 ps
CPU time 1369.42 seconds
Started Jun 27 05:24:47 PM PDT 24
Finished Jun 27 05:47:38 PM PDT 24
Peak memory 282136 kb
Host smart-f348f93b-573c-4810-a77a-cc58ab147589
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296591762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1296591762
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2083825868
Short name T625
Test name
Test status
Simulation time 12146910374 ps
CPU time 1179.45 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:44:54 PM PDT 24
Peak memory 290372 kb
Host smart-dd82e931-1398-41b7-b381-29ce57d32889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083825868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2083825868
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1352913933
Short name T230
Test name
Test status
Simulation time 88491688136 ps
CPU time 709.06 seconds
Started Jun 27 05:24:43 PM PDT 24
Finished Jun 27 05:36:33 PM PDT 24
Peak memory 249408 kb
Host smart-0c6aa1d9-cfe3-400c-86f1-b521254584ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352913933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1352913933
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.709660938
Short name T444
Test name
Test status
Simulation time 42379364 ps
CPU time 5.15 seconds
Started Jun 27 05:24:47 PM PDT 24
Finished Jun 27 05:24:53 PM PDT 24
Peak memory 249236 kb
Host smart-0601800b-90dc-49ac-9914-7637748cc3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70966
0938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.709660938
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4027125717
Short name T665
Test name
Test status
Simulation time 359610686 ps
CPU time 25.84 seconds
Started Jun 27 05:24:47 PM PDT 24
Finished Jun 27 05:25:14 PM PDT 24
Peak memory 249312 kb
Host smart-2523c9b2-aa0e-409e-a2e9-22322fea1e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
25717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4027125717
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.757042836
Short name T626
Test name
Test status
Simulation time 154331397 ps
CPU time 17 seconds
Started Jun 27 05:24:44 PM PDT 24
Finished Jun 27 05:25:03 PM PDT 24
Peak memory 257400 kb
Host smart-f6130812-dc79-4f98-be84-5628854a5ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75704
2836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.757042836
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3679970544
Short name T515
Test name
Test status
Simulation time 262573462 ps
CPU time 8.02 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:25:18 PM PDT 24
Peak memory 254268 kb
Host smart-5b6bb5f8-6c65-4800-8a7b-c3fb7bc8f486
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679970544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3679970544
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2069537054
Short name T199
Test name
Test status
Simulation time 138635585 ps
CPU time 3.57 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:17 PM PDT 24
Peak memory 249564 kb
Host smart-0e5a6a76-379b-44f0-9685-b6301be1aedb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2069537054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2069537054
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1257251914
Short name T644
Test name
Test status
Simulation time 183521946040 ps
CPU time 2587.41 seconds
Started Jun 27 05:25:09 PM PDT 24
Finished Jun 27 06:08:18 PM PDT 24
Peak memory 290404 kb
Host smart-ab82c2a6-cba7-45dd-a060-66a1e39588cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257251914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1257251914
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1602992522
Short name T441
Test name
Test status
Simulation time 885486621 ps
CPU time 40.84 seconds
Started Jun 27 05:25:14 PM PDT 24
Finished Jun 27 05:25:56 PM PDT 24
Peak memory 249160 kb
Host smart-6afb4171-fb87-45f1-8be6-c6b143b304c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1602992522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1602992522
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2117925184
Short name T370
Test name
Test status
Simulation time 4498240830 ps
CPU time 146.73 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:27:38 PM PDT 24
Peak memory 256748 kb
Host smart-eb1602d6-321e-4137-89c3-4f7ccd93924c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
25184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2117925184
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.584507534
Short name T61
Test name
Test status
Simulation time 632299030 ps
CPU time 19.84 seconds
Started Jun 27 05:25:09 PM PDT 24
Finished Jun 27 05:25:30 PM PDT 24
Peak memory 256864 kb
Host smart-fd039461-fe8f-425f-ad6e-31fff086db4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58450
7534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.584507534
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.817587878
Short name T41
Test name
Test status
Simulation time 16948517379 ps
CPU time 1446.92 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:49:22 PM PDT 24
Peak memory 289716 kb
Host smart-e47964aa-5234-4921-9663-d4d78e5598d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817587878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.817587878
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3595831529
Short name T499
Test name
Test status
Simulation time 67604035424 ps
CPU time 2051.4 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:59:26 PM PDT 24
Peak memory 273912 kb
Host smart-2278df65-e996-4ba8-aea0-7defba7759f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595831529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3595831529
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.556111323
Short name T605
Test name
Test status
Simulation time 906445546 ps
CPU time 47.38 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:25:59 PM PDT 24
Peak memory 249304 kb
Host smart-a3b359ca-88c4-46db-af92-1fd0785474c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55611
1323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.556111323
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1174429047
Short name T722
Test name
Test status
Simulation time 271243422 ps
CPU time 20.56 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:25:35 PM PDT 24
Peak memory 249004 kb
Host smart-5b7dc49f-175b-4c2f-a5fe-8c81e243b31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11744
29047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1174429047
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3789504751
Short name T579
Test name
Test status
Simulation time 934012242 ps
CPU time 16.54 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:25:28 PM PDT 24
Peak memory 257076 kb
Host smart-9e925f45-56cd-4161-b7f1-24bfaaeb1f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
04751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3789504751
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2402582857
Short name T412
Test name
Test status
Simulation time 1851922988 ps
CPU time 25.38 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:40 PM PDT 24
Peak memory 256156 kb
Host smart-fed27e34-9469-42b1-8c64-be719d08caf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
82857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2402582857
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3241573379
Short name T258
Test name
Test status
Simulation time 52404070358 ps
CPU time 2951.87 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 06:14:24 PM PDT 24
Peak memory 289716 kb
Host smart-8dabb981-62e5-48ab-85e6-c6434fda7532
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241573379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3241573379
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2033070882
Short name T78
Test name
Test status
Simulation time 42356908600 ps
CPU time 4649.86 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 339136 kb
Host smart-7151d938-62e1-4f7f-b620-c4e307afbeb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033070882 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2033070882
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4064256865
Short name T213
Test name
Test status
Simulation time 14335193 ps
CPU time 2.45 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:25:13 PM PDT 24
Peak memory 249528 kb
Host smart-5544ed55-0d8e-48f1-b08e-38b52b4a1820
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4064256865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4064256865
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1761978892
Short name T466
Test name
Test status
Simulation time 5400986682 ps
CPU time 596.44 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:35:12 PM PDT 24
Peak memory 266860 kb
Host smart-c7b93bdc-cc81-497a-b484-af237beb2afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761978892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1761978892
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.835083128
Short name T478
Test name
Test status
Simulation time 1246042404 ps
CPU time 28.02 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:25:43 PM PDT 24
Peak memory 249204 kb
Host smart-48be45fb-1e1f-406b-9b87-1525433ec321
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=835083128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.835083128
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1177636659
Short name T252
Test name
Test status
Simulation time 3796858884 ps
CPU time 101.87 seconds
Started Jun 27 05:25:13 PM PDT 24
Finished Jun 27 05:26:57 PM PDT 24
Peak memory 250444 kb
Host smart-6a5a907f-a411-4441-9aea-4a87a2e8fc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
36659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1177636659
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2973444658
Short name T420
Test name
Test status
Simulation time 1043891814 ps
CPU time 25.9 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:25:38 PM PDT 24
Peak memory 249292 kb
Host smart-71091daa-3f76-44b8-9099-767d54bfca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29734
44658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2973444658
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3153176114
Short name T330
Test name
Test status
Simulation time 21963513310 ps
CPU time 1190.32 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:45:04 PM PDT 24
Peak memory 273936 kb
Host smart-1a44ad1c-84ac-44f0-812f-2eb727d11c67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153176114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3153176114
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2922535860
Short name T535
Test name
Test status
Simulation time 68475869510 ps
CPU time 1291.06 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:46:45 PM PDT 24
Peak memory 289972 kb
Host smart-7c333011-12f0-4f63-b31e-d18ebca4b0c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922535860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2922535860
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3307597588
Short name T285
Test name
Test status
Simulation time 8887764080 ps
CPU time 370.3 seconds
Started Jun 27 05:25:10 PM PDT 24
Finished Jun 27 05:31:22 PM PDT 24
Peak memory 248256 kb
Host smart-597c1b11-6608-463f-9657-19819c6f1cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307597588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3307597588
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3587305448
Short name T58
Test name
Test status
Simulation time 3532045650 ps
CPU time 48.37 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:26:03 PM PDT 24
Peak memory 256816 kb
Host smart-c45a9790-61e1-4938-a34b-6decebb6f9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
05448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3587305448
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3079674635
Short name T423
Test name
Test status
Simulation time 1963557282 ps
CPU time 44.91 seconds
Started Jun 27 05:25:14 PM PDT 24
Finished Jun 27 05:26:01 PM PDT 24
Peak memory 257388 kb
Host smart-188ef069-34ea-4651-8f87-a72201e448fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
74635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3079674635
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3782678437
Short name T406
Test name
Test status
Simulation time 142122567 ps
CPU time 12.74 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:27 PM PDT 24
Peak memory 248752 kb
Host smart-8a6ee2fd-37da-42ec-aa45-569c44f52a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
78437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3782678437
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3492935070
Short name T473
Test name
Test status
Simulation time 557584677 ps
CPU time 23.01 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:37 PM PDT 24
Peak memory 257428 kb
Host smart-aaf1f071-0b9c-43e1-9497-51f121f3e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
35070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3492935070
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.17155231
Short name T24
Test name
Test status
Simulation time 437593498 ps
CPU time 38.44 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:53 PM PDT 24
Peak memory 257436 kb
Host smart-5c283067-4948-49eb-af89-591cdd3cc3ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17155231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_hand
ler_stress_all.17155231
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3766383503
Short name T215
Test name
Test status
Simulation time 167478398 ps
CPU time 3.98 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:25:37 PM PDT 24
Peak memory 249536 kb
Host smart-a18e4cac-0014-45c8-a61b-03d884d25e1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3766383503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3766383503
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2188803352
Short name T723
Test name
Test status
Simulation time 348136056956 ps
CPU time 2000.21 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:58:35 PM PDT 24
Peak memory 282204 kb
Host smart-9157fe08-7c8b-4216-9d02-4e064c3c71c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188803352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2188803352
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2200276209
Short name T597
Test name
Test status
Simulation time 1075346388 ps
CPU time 48.9 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:26:21 PM PDT 24
Peak memory 249192 kb
Host smart-f5a622a6-81c6-4be6-aa66-f638129dafdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2200276209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2200276209
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1477741607
Short name T492
Test name
Test status
Simulation time 2421604513 ps
CPU time 112.33 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:27:07 PM PDT 24
Peak memory 257004 kb
Host smart-e9496aaf-a651-46f2-8a2f-6f48f9006874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
41607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1477741607
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.869270230
Short name T711
Test name
Test status
Simulation time 4965993382 ps
CPU time 32.8 seconds
Started Jun 27 05:25:11 PM PDT 24
Finished Jun 27 05:25:47 PM PDT 24
Peak memory 249356 kb
Host smart-429f0c4b-ed26-41fc-a89b-189c1983d3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86927
0230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.869270230
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3157712833
Short name T453
Test name
Test status
Simulation time 55691834913 ps
CPU time 2932.41 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 06:14:27 PM PDT 24
Peak memory 290132 kb
Host smart-695d90e7-e28c-490c-abb8-41ae969cf85f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157712833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3157712833
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2788743861
Short name T538
Test name
Test status
Simulation time 17087715213 ps
CPU time 172.52 seconds
Started Jun 27 05:25:33 PM PDT 24
Finished Jun 27 05:28:27 PM PDT 24
Peak memory 248368 kb
Host smart-09f97ae8-763d-46b4-b1a4-eff738d92d33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788743861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2788743861
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2440063707
Short name T400
Test name
Test status
Simulation time 1549831036 ps
CPU time 28.36 seconds
Started Jun 27 05:25:13 PM PDT 24
Finished Jun 27 05:25:44 PM PDT 24
Peak memory 256708 kb
Host smart-df507934-0a51-4b3c-9197-ffa8a5bbdac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24400
63707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2440063707
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2389322488
Short name T1
Test name
Test status
Simulation time 1014292240 ps
CPU time 23.1 seconds
Started Jun 27 05:25:14 PM PDT 24
Finished Jun 27 05:25:39 PM PDT 24
Peak memory 249296 kb
Host smart-c8bb7913-96bd-48c6-a5a4-475b90ef948d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23893
22488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2389322488
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.475963379
Short name T554
Test name
Test status
Simulation time 3315495019 ps
CPU time 52.9 seconds
Started Jun 27 05:25:12 PM PDT 24
Finished Jun 27 05:26:08 PM PDT 24
Peak memory 249208 kb
Host smart-640da667-1dd5-4071-be49-b50e1229a0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47596
3379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.475963379
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3865294798
Short name T448
Test name
Test status
Simulation time 1817350251 ps
CPU time 64.74 seconds
Started Jun 27 05:25:13 PM PDT 24
Finished Jun 27 05:26:20 PM PDT 24
Peak memory 249480 kb
Host smart-d41c52f5-2f38-4a0a-8b91-e66d65552c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38652
94798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3865294798
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.265297667
Short name T267
Test name
Test status
Simulation time 650330430352 ps
CPU time 8155.85 seconds
Started Jun 27 05:25:29 PM PDT 24
Finished Jun 27 07:41:28 PM PDT 24
Peak memory 330948 kb
Host smart-a698ff5e-28f7-4a3b-a222-0aa73e96aeb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265297667 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.265297667
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4093868469
Short name T203
Test name
Test status
Simulation time 139525236 ps
CPU time 3.84 seconds
Started Jun 27 05:25:33 PM PDT 24
Finished Jun 27 05:25:39 PM PDT 24
Peak memory 249552 kb
Host smart-5df1582d-338d-4c70-a793-395deb5b4d9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4093868469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4093868469
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2930623730
Short name T19
Test name
Test status
Simulation time 10871045158 ps
CPU time 915.33 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:40:48 PM PDT 24
Peak memory 290116 kb
Host smart-97a4e00a-d762-4c58-b712-95ad09c13fa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930623730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2930623730
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1208138757
Short name T440
Test name
Test status
Simulation time 749889513 ps
CPU time 6.17 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:25:44 PM PDT 24
Peak memory 249244 kb
Host smart-4b5e4787-b793-4c78-a266-46da2396cd84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1208138757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1208138757
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2264857347
Short name T414
Test name
Test status
Simulation time 1791558015 ps
CPU time 160.02 seconds
Started Jun 27 05:25:29 PM PDT 24
Finished Jun 27 05:28:11 PM PDT 24
Peak memory 256552 kb
Host smart-1f2195c6-5c7f-44e7-a656-57f74590b60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
57347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2264857347
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4024850217
Short name T454
Test name
Test status
Simulation time 33998191 ps
CPU time 4.4 seconds
Started Jun 27 05:25:27 PM PDT 24
Finished Jun 27 05:25:33 PM PDT 24
Peak memory 249216 kb
Host smart-4428841f-e252-44db-be2a-65a96a30712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
50217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4024850217
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3698361618
Short name T482
Test name
Test status
Simulation time 39176217427 ps
CPU time 1022.29 seconds
Started Jun 27 05:25:29 PM PDT 24
Finished Jun 27 05:42:32 PM PDT 24
Peak memory 282108 kb
Host smart-49e55940-6ddf-4626-bc64-0f1c2b139235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698361618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3698361618
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.928105969
Short name T11
Test name
Test status
Simulation time 20071451686 ps
CPU time 216.19 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:29:14 PM PDT 24
Peak memory 256016 kb
Host smart-fb7119e2-3faa-4e64-9e9f-347481c27460
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928105969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.928105969
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.398143757
Short name T428
Test name
Test status
Simulation time 2802643696 ps
CPU time 25.14 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:26:03 PM PDT 24
Peak memory 255948 kb
Host smart-7a72f5d3-e555-4229-bd1b-1c79f8735951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39814
3757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.398143757
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2061416995
Short name T560
Test name
Test status
Simulation time 574335458 ps
CPU time 28.91 seconds
Started Jun 27 05:25:29 PM PDT 24
Finished Jun 27 05:25:59 PM PDT 24
Peak memory 256556 kb
Host smart-b109ae88-0302-4b66-a94a-6fafba267913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
16995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2061416995
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2772352958
Short name T271
Test name
Test status
Simulation time 66004645 ps
CPU time 8.56 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 05:25:43 PM PDT 24
Peak memory 248848 kb
Host smart-4c3114d6-4d6e-4d35-bbb7-99b9a13c586a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27723
52958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2772352958
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.623043374
Short name T475
Test name
Test status
Simulation time 135144735 ps
CPU time 6.04 seconds
Started Jun 27 05:25:37 PM PDT 24
Finished Jun 27 05:25:44 PM PDT 24
Peak memory 249260 kb
Host smart-b70437a8-229f-45c9-8714-b54322d48cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62304
3374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.623043374
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1282997786
Short name T253
Test name
Test status
Simulation time 75776679197 ps
CPU time 2176.44 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 06:01:51 PM PDT 24
Peak memory 286660 kb
Host smart-aca2d86a-bb94-4862-8907-7eb287bfe388
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282997786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1282997786
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3742985813
Short name T210
Test name
Test status
Simulation time 50195065 ps
CPU time 2.57 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:25:36 PM PDT 24
Peak memory 249592 kb
Host smart-65e2313b-ee65-4dda-811a-835b4e0b5cd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3742985813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3742985813
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3079137398
Short name T402
Test name
Test status
Simulation time 310329078939 ps
CPU time 2333.56 seconds
Started Jun 27 05:25:33 PM PDT 24
Finished Jun 27 06:04:29 PM PDT 24
Peak memory 290020 kb
Host smart-c65213d2-0329-4a52-ac57-20a8f3810964
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079137398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3079137398
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1579732587
Short name T16
Test name
Test status
Simulation time 527837031 ps
CPU time 8.02 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:25:41 PM PDT 24
Peak memory 249240 kb
Host smart-1659db21-8e8b-44e7-8d3f-c08334c957e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1579732587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1579732587
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3227148133
Short name T443
Test name
Test status
Simulation time 2785317152 ps
CPU time 102.92 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:27:16 PM PDT 24
Peak memory 257576 kb
Host smart-a346c76c-fb96-4d0b-aae6-97a57776a4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
48133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3227148133
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3303958605
Short name T69
Test name
Test status
Simulation time 227018541 ps
CPU time 11.69 seconds
Started Jun 27 05:25:29 PM PDT 24
Finished Jun 27 05:25:43 PM PDT 24
Peak memory 249020 kb
Host smart-10e4c672-5410-498e-984e-d786bc432b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33039
58605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3303958605
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.439206708
Short name T527
Test name
Test status
Simulation time 30895201453 ps
CPU time 1866.94 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:56:48 PM PDT 24
Peak memory 273332 kb
Host smart-2749d0b9-1c84-4704-bc26-224829fa88dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439206708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.439206708
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4018521881
Short name T413
Test name
Test status
Simulation time 654196906996 ps
CPU time 2098.27 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 06:00:32 PM PDT 24
Peak memory 289016 kb
Host smart-2133e0e0-10b0-4f1b-9296-6d826119e21b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018521881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4018521881
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2602999494
Short name T496
Test name
Test status
Simulation time 24888020389 ps
CPU time 126.84 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 05:27:40 PM PDT 24
Peak memory 249360 kb
Host smart-11fc63be-d8b8-4ccc-9ef7-367b2804fe91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602999494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2602999494
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2533056462
Short name T60
Test name
Test status
Simulation time 742835957 ps
CPU time 51.43 seconds
Started Jun 27 05:25:30 PM PDT 24
Finished Jun 27 05:26:23 PM PDT 24
Peak memory 257328 kb
Host smart-c648bcfd-016c-498d-8819-404ce72a1954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330
56462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2533056462
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2685520438
Short name T74
Test name
Test status
Simulation time 1516724018 ps
CPU time 25.46 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:26:03 PM PDT 24
Peak memory 249192 kb
Host smart-4d4fc6dd-c25c-4c86-bcda-12aeb8a0c7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
20438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2685520438
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2279498280
Short name T696
Test name
Test status
Simulation time 1089791799 ps
CPU time 64.41 seconds
Started Jun 27 05:25:30 PM PDT 24
Finished Jun 27 05:26:36 PM PDT 24
Peak memory 248824 kb
Host smart-78c695dc-293a-429c-afe8-3ddb4d41439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794
98280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2279498280
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.634367412
Short name T483
Test name
Test status
Simulation time 3135441584 ps
CPU time 52.26 seconds
Started Jun 27 05:25:27 PM PDT 24
Finished Jun 27 05:26:21 PM PDT 24
Peak memory 257368 kb
Host smart-72a84a7d-ffd6-47a9-a3b5-5b2f1a509e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63436
7412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.634367412
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2081862972
Short name T570
Test name
Test status
Simulation time 200328403208 ps
CPU time 1966.51 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:58:23 PM PDT 24
Peak memory 290168 kb
Host smart-0aa25b57-d7fc-4489-83bc-6379806a42e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081862972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2081862972
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2327648928
Short name T209
Test name
Test status
Simulation time 27681662 ps
CPU time 2.38 seconds
Started Jun 27 05:23:28 PM PDT 24
Finished Jun 27 05:23:33 PM PDT 24
Peak memory 249580 kb
Host smart-fcbb1b4b-a906-48e8-a747-b335cac5ef58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2327648928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2327648928
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2556856343
Short name T18
Test name
Test status
Simulation time 165440661150 ps
CPU time 3063.61 seconds
Started Jun 27 05:23:29 PM PDT 24
Finished Jun 27 06:14:35 PM PDT 24
Peak memory 289308 kb
Host smart-fa5fcca2-8bbe-4ecd-8bfc-2d65e05767cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556856343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2556856343
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.623286920
Short name T708
Test name
Test status
Simulation time 1070128888 ps
CPU time 15.28 seconds
Started Jun 27 05:23:28 PM PDT 24
Finished Jun 27 05:23:46 PM PDT 24
Peak memory 249312 kb
Host smart-fe38fd14-ab31-48d3-aa16-04cb2203039b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=623286920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.623286920
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.117403098
Short name T455
Test name
Test status
Simulation time 447949310 ps
CPU time 27.97 seconds
Started Jun 27 05:23:30 PM PDT 24
Finished Jun 27 05:24:00 PM PDT 24
Peak memory 256996 kb
Host smart-2c24f4e6-47a3-4f52-acb9-9af772a799bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11740
3098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.117403098
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3814647121
Short name T672
Test name
Test status
Simulation time 2416457025 ps
CPU time 39.59 seconds
Started Jun 27 05:23:29 PM PDT 24
Finished Jun 27 05:24:11 PM PDT 24
Peak memory 248928 kb
Host smart-68c55b81-8c2b-4445-a147-5dd1a05c444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146
47121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3814647121
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2815026710
Short name T275
Test name
Test status
Simulation time 33226904406 ps
CPU time 2048.99 seconds
Started Jun 27 05:23:29 PM PDT 24
Finished Jun 27 05:57:40 PM PDT 24
Peak memory 282140 kb
Host smart-d55f5596-02a3-4306-b142-c009714ac07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815026710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2815026710
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4006901020
Short name T196
Test name
Test status
Simulation time 56283863178 ps
CPU time 1100.86 seconds
Started Jun 27 05:23:30 PM PDT 24
Finished Jun 27 05:41:53 PM PDT 24
Peak memory 273956 kb
Host smart-069ee6a9-ef52-45bc-84a2-b9758a829d8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006901020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4006901020
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1509548645
Short name T296
Test name
Test status
Simulation time 3640079030 ps
CPU time 148.88 seconds
Started Jun 27 05:23:27 PM PDT 24
Finished Jun 27 05:25:58 PM PDT 24
Peak memory 249360 kb
Host smart-634d9239-1c07-4862-9bfb-5d1c77521423
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509548645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1509548645
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3169401323
Short name T476
Test name
Test status
Simulation time 789567010 ps
CPU time 18.81 seconds
Started Jun 27 05:23:33 PM PDT 24
Finished Jun 27 05:23:54 PM PDT 24
Peak memory 249272 kb
Host smart-2dc3f4f0-d1cf-470a-a7a9-7e97e0f8da67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
01323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3169401323
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.106065991
Short name T669
Test name
Test status
Simulation time 2472206123 ps
CPU time 36.02 seconds
Started Jun 27 05:23:30 PM PDT 24
Finished Jun 27 05:24:08 PM PDT 24
Peak memory 249428 kb
Host smart-878cef80-6d4b-4366-8496-52f0304fc131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606
5991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.106065991
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.607285319
Short name T13
Test name
Test status
Simulation time 873731362 ps
CPU time 12.66 seconds
Started Jun 27 05:23:28 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 274668 kb
Host smart-940a9fe7-037f-4137-9401-f1df60261c17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=607285319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.607285319
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1947704568
Short name T707
Test name
Test status
Simulation time 235082890 ps
CPU time 4.94 seconds
Started Jun 27 05:23:28 PM PDT 24
Finished Jun 27 05:23:35 PM PDT 24
Peak memory 241064 kb
Host smart-0c9af606-6670-4e9c-bc1d-1141637b9179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19477
04568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1947704568
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4128255823
Short name T602
Test name
Test status
Simulation time 183872701 ps
CPU time 10.24 seconds
Started Jun 27 05:23:18 PM PDT 24
Finished Jun 27 05:23:29 PM PDT 24
Peak memory 257100 kb
Host smart-69912ad1-14cf-4c89-bc1b-630bfebc40ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41282
55823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4128255823
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1026866453
Short name T65
Test name
Test status
Simulation time 2307105992 ps
CPU time 140.27 seconds
Started Jun 27 05:23:29 PM PDT 24
Finished Jun 27 05:25:51 PM PDT 24
Peak memory 257592 kb
Host smart-5fa6a7e1-5143-48a9-b759-20fb4d087342
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026866453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1026866453
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1995576182
Short name T701
Test name
Test status
Simulation time 56738082602 ps
CPU time 1808.7 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:55:45 PM PDT 24
Peak memory 273796 kb
Host smart-b4467ec5-6073-48f4-b8a2-5e72d7840b09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995576182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1995576182
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1076352399
Short name T38
Test name
Test status
Simulation time 3265374650 ps
CPU time 72.95 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:26:46 PM PDT 24
Peak memory 257124 kb
Host smart-dd3fcdef-f3f9-4938-b80f-f4c1b3f34fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10763
52399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1076352399
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4093765850
Short name T445
Test name
Test status
Simulation time 3093295378 ps
CPU time 55.07 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:26:32 PM PDT 24
Peak memory 249372 kb
Host smart-1ea9cd36-e222-4374-9bfa-fde513cb0740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
65850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4093765850
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2709766041
Short name T447
Test name
Test status
Simulation time 8240910777 ps
CPU time 591.45 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:35:28 PM PDT 24
Peak memory 267888 kb
Host smart-227ee932-75a9-455c-a988-fd3ce060a688
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709766041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2709766041
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.757571383
Short name T660
Test name
Test status
Simulation time 278022197 ps
CPU time 13.08 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:25:45 PM PDT 24
Peak memory 249304 kb
Host smart-1ad5be31-25fc-4a2e-a7cb-33f3a2bc365e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75757
1383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.757571383
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.141937033
Short name T308
Test name
Test status
Simulation time 2954766028 ps
CPU time 44.28 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:26:20 PM PDT 24
Peak memory 256920 kb
Host smart-d03b4c56-7ad4-4307-887f-fb47bfc9d51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14193
7033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.141937033
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2520479685
Short name T198
Test name
Test status
Simulation time 2749126061 ps
CPU time 42.77 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:26:20 PM PDT 24
Peak memory 249392 kb
Host smart-b3c24f6d-6936-4166-b797-16c97fa78e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25204
79685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2520479685
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3453911653
Short name T480
Test name
Test status
Simulation time 175431796 ps
CPU time 19.85 seconds
Started Jun 27 05:25:33 PM PDT 24
Finished Jun 27 05:25:54 PM PDT 24
Peak memory 256704 kb
Host smart-63782a8c-6ac1-4528-b62f-30846ff86e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539
11653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3453911653
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1022267656
Short name T522
Test name
Test status
Simulation time 45687420017 ps
CPU time 1071.5 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:43:33 PM PDT 24
Peak memory 289284 kb
Host smart-cd1785a6-de31-45e9-b69a-e449cf364640
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022267656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1022267656
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2225715342
Short name T479
Test name
Test status
Simulation time 1790854509 ps
CPU time 83.36 seconds
Started Jun 27 05:25:32 PM PDT 24
Finished Jun 27 05:26:57 PM PDT 24
Peak memory 250312 kb
Host smart-f35cac93-4cb9-454e-9855-a912dcdc1af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
15342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2225715342
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3826481406
Short name T565
Test name
Test status
Simulation time 475032711 ps
CPU time 35.69 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:26:12 PM PDT 24
Peak memory 256996 kb
Host smart-1c5d6462-3dec-4ac3-9722-096be1975d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
81406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3826481406
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3836218369
Short name T593
Test name
Test status
Simulation time 327945512243 ps
CPU time 2276.88 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 06:03:34 PM PDT 24
Peak memory 286036 kb
Host smart-e23585f3-412c-4c8e-97c7-8d66b015879d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836218369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3836218369
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3821788959
Short name T327
Test name
Test status
Simulation time 39997946297 ps
CPU time 1583.7 seconds
Started Jun 27 05:25:37 PM PDT 24
Finished Jun 27 05:52:02 PM PDT 24
Peak memory 290100 kb
Host smart-9981a4c8-f802-4210-87ea-81191a77128f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821788959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3821788959
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1074758786
Short name T374
Test name
Test status
Simulation time 636140563 ps
CPU time 23.75 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:26:01 PM PDT 24
Peak memory 256948 kb
Host smart-a0830dce-d3d7-4bb1-a7f8-841e7583a357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
58786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1074758786
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2483473497
Short name T682
Test name
Test status
Simulation time 3736768048 ps
CPU time 51.41 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:26:33 PM PDT 24
Peak memory 257044 kb
Host smart-09076040-b5f8-41d9-8110-38d300da2ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24834
73497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2483473497
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.909584915
Short name T511
Test name
Test status
Simulation time 833522042 ps
CPU time 50.25 seconds
Started Jun 27 05:25:40 PM PDT 24
Finished Jun 27 05:26:31 PM PDT 24
Peak memory 256856 kb
Host smart-61dc90ce-1c4a-41ad-b42c-019b30cb3f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90958
4915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.909584915
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.151120646
Short name T404
Test name
Test status
Simulation time 338763399 ps
CPU time 21.88 seconds
Started Jun 27 05:25:31 PM PDT 24
Finished Jun 27 05:25:54 PM PDT 24
Peak memory 249212 kb
Host smart-e91d1c81-6781-4344-a0a6-30b436c00c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
0646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.151120646
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.197285283
Short name T394
Test name
Test status
Simulation time 53561738334 ps
CPU time 1194 seconds
Started Jun 27 05:25:36 PM PDT 24
Finished Jun 27 05:45:32 PM PDT 24
Peak memory 285872 kb
Host smart-70ab7147-0f49-4f0f-89dc-b4fe5a4cef94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197285283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.197285283
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3651046612
Short name T702
Test name
Test status
Simulation time 15794728974 ps
CPU time 1619.36 seconds
Started Jun 27 05:25:35 PM PDT 24
Finished Jun 27 05:52:36 PM PDT 24
Peak memory 298724 kb
Host smart-964c15ef-d94b-4ce3-8553-4a5e06ca2cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651046612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3651046612
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4190844232
Short name T67
Test name
Test status
Simulation time 6551085514 ps
CPU time 624.73 seconds
Started Jun 27 05:25:48 PM PDT 24
Finished Jun 27 05:36:14 PM PDT 24
Peak memory 266796 kb
Host smart-d8015968-2ff3-4486-b698-012ccd29745a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190844232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4190844232
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2345629841
Short name T598
Test name
Test status
Simulation time 456786780 ps
CPU time 33.11 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:26:23 PM PDT 24
Peak memory 257028 kb
Host smart-3a665ba7-b39e-47f0-a222-cb6948ff9922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23456
29841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2345629841
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.968173799
Short name T415
Test name
Test status
Simulation time 1660255162 ps
CPU time 44.53 seconds
Started Jun 27 05:25:48 PM PDT 24
Finished Jun 27 05:26:33 PM PDT 24
Peak memory 249212 kb
Host smart-335dbd9f-d549-422c-9c89-76950a8fb1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96817
3799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.968173799
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3955995590
Short name T633
Test name
Test status
Simulation time 134816799581 ps
CPU time 1996.29 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:59:07 PM PDT 24
Peak memory 282084 kb
Host smart-3a6a34ca-d5ab-438e-9302-57ff5be9cb58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955995590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3955995590
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.945218233
Short name T588
Test name
Test status
Simulation time 104542848510 ps
CPU time 798.55 seconds
Started Jun 27 05:25:53 PM PDT 24
Finished Jun 27 05:39:12 PM PDT 24
Peak memory 273440 kb
Host smart-3cb23346-9c76-4ad2-82d4-ff8b38785f18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945218233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.945218233
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.384496620
Short name T540
Test name
Test status
Simulation time 35255904243 ps
CPU time 366.52 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:31:58 PM PDT 24
Peak memory 249320 kb
Host smart-839388eb-5b63-4be9-901f-d96cdcce929e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384496620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.384496620
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1236050110
Short name T497
Test name
Test status
Simulation time 323627367 ps
CPU time 13.9 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:26:05 PM PDT 24
Peak memory 256804 kb
Host smart-bd88fd6a-9bae-478e-a185-25082a3bb372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
50110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1236050110
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2573819648
Short name T3
Test name
Test status
Simulation time 1260906557 ps
CPU time 47.1 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:26:37 PM PDT 24
Peak memory 249312 kb
Host smart-556d38af-2304-48fe-9fdc-47848ae5d7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25738
19648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2573819648
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.218685073
Short name T326
Test name
Test status
Simulation time 572458084 ps
CPU time 36.75 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:26:28 PM PDT 24
Peak memory 249624 kb
Host smart-20ef4e52-340f-4c22-a366-11000076b3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21868
5073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.218685073
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.92987623
Short name T377
Test name
Test status
Simulation time 86556137 ps
CPU time 3.16 seconds
Started Jun 27 05:25:51 PM PDT 24
Finished Jun 27 05:25:55 PM PDT 24
Peak memory 251324 kb
Host smart-9f980e2d-456d-47b4-aa2e-374f3b73ae18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92987
623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.92987623
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3884569653
Short name T45
Test name
Test status
Simulation time 4124240411 ps
CPU time 358.95 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:31:50 PM PDT 24
Peak memory 257540 kb
Host smart-8c22381a-a665-4a40-a703-eb3d3bbfef3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884569653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3884569653
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1547335254
Short name T446
Test name
Test status
Simulation time 7050606384 ps
CPU time 355.14 seconds
Started Jun 27 05:25:47 PM PDT 24
Finished Jun 27 05:31:43 PM PDT 24
Peak memory 256948 kb
Host smart-c9b730f6-7255-4384-93a2-c000695a4522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15473
35254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1547335254
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3296075943
Short name T438
Test name
Test status
Simulation time 672686289 ps
CPU time 38.28 seconds
Started Jun 27 05:25:48 PM PDT 24
Finished Jun 27 05:26:27 PM PDT 24
Peak memory 249220 kb
Host smart-2507e491-8ea3-4f77-9887-83b1ac4a1eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32960
75943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3296075943
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3843938037
Short name T493
Test name
Test status
Simulation time 173005213043 ps
CPU time 1509.08 seconds
Started Jun 27 05:25:51 PM PDT 24
Finished Jun 27 05:51:01 PM PDT 24
Peak memory 288528 kb
Host smart-f1f3f004-4ae5-4a2b-abce-3b2b3641a4f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843938037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3843938037
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3066186635
Short name T590
Test name
Test status
Simulation time 140226054620 ps
CPU time 2808.84 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 06:12:39 PM PDT 24
Peak memory 287212 kb
Host smart-1d76f57a-acaf-4d73-b96c-5971e7630cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066186635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3066186635
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3893785470
Short name T63
Test name
Test status
Simulation time 24845620780 ps
CPU time 529.85 seconds
Started Jun 27 05:25:47 PM PDT 24
Finished Jun 27 05:34:38 PM PDT 24
Peak memory 249240 kb
Host smart-01a39d1f-7a1b-481c-a82a-2290830925e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893785470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3893785470
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.850301540
Short name T57
Test name
Test status
Simulation time 417562520 ps
CPU time 38.3 seconds
Started Jun 27 05:25:51 PM PDT 24
Finished Jun 27 05:26:31 PM PDT 24
Peak memory 256596 kb
Host smart-5c59b755-82c3-43ff-a893-cffae0711648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85030
1540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.850301540
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1115806142
Short name T435
Test name
Test status
Simulation time 1077124840 ps
CPU time 58.47 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:26:48 PM PDT 24
Peak memory 257040 kb
Host smart-50c36e22-a4d1-473e-90f4-9d8100476650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11158
06142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1115806142
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4023802572
Short name T484
Test name
Test status
Simulation time 1501001280 ps
CPU time 19.38 seconds
Started Jun 27 05:25:52 PM PDT 24
Finished Jun 27 05:26:13 PM PDT 24
Peak memory 248812 kb
Host smart-4f8f3c2a-bcd3-4cd1-a13e-49edf9971573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40238
02572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4023802572
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3242769158
Short name T670
Test name
Test status
Simulation time 397540347 ps
CPU time 25.11 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:26:16 PM PDT 24
Peak memory 257416 kb
Host smart-3fcb96cf-1583-4213-95e0-da1aaf9c96bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32427
69158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3242769158
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3525854795
Short name T704
Test name
Test status
Simulation time 2976072678 ps
CPU time 167.2 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:28:37 PM PDT 24
Peak memory 257604 kb
Host smart-11c14c30-0083-4a6c-b01f-9490141dc19e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525854795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3525854795
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1523169390
Short name T225
Test name
Test status
Simulation time 13908313647 ps
CPU time 1077.48 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:43:48 PM PDT 24
Peak memory 273724 kb
Host smart-3d2ba0c3-a081-4739-9617-558cb30fad30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523169390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1523169390
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1366387453
Short name T624
Test name
Test status
Simulation time 1977287819 ps
CPU time 84.26 seconds
Started Jun 27 05:25:51 PM PDT 24
Finished Jun 27 05:27:16 PM PDT 24
Peak memory 257384 kb
Host smart-0e07b8ec-cd3a-4c71-8e55-822291970559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
87453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1366387453
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2910947622
Short name T596
Test name
Test status
Simulation time 490042113 ps
CPU time 25.64 seconds
Started Jun 27 05:25:52 PM PDT 24
Finished Jun 27 05:26:19 PM PDT 24
Peak memory 249240 kb
Host smart-fbcaae3b-ad7c-4932-a6d8-97a5ad27c7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29109
47622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2910947622
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1060095706
Short name T566
Test name
Test status
Simulation time 58914328490 ps
CPU time 753.2 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:38:24 PM PDT 24
Peak memory 273884 kb
Host smart-8540230b-ad1b-4531-894c-ec274bbef92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060095706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1060095706
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.511771395
Short name T485
Test name
Test status
Simulation time 15119559302 ps
CPU time 1672.14 seconds
Started Jun 27 05:25:52 PM PDT 24
Finished Jun 27 05:53:45 PM PDT 24
Peak memory 290332 kb
Host smart-c1cbd6d5-f175-4698-a1a5-343f0d39da27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511771395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.511771395
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1603306060
Short name T223
Test name
Test status
Simulation time 5985759761 ps
CPU time 62.78 seconds
Started Jun 27 05:25:50 PM PDT 24
Finished Jun 27 05:26:54 PM PDT 24
Peak memory 249408 kb
Host smart-c5fc0917-8d84-4a84-bb28-1f8947350aab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603306060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1603306060
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4282978805
Short name T22
Test name
Test status
Simulation time 353838794 ps
CPU time 20.79 seconds
Started Jun 27 05:25:53 PM PDT 24
Finished Jun 27 05:26:14 PM PDT 24
Peak memory 255740 kb
Host smart-335ebad7-d73d-4177-8a18-582a4589181e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42829
78805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4282978805
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.346905446
Short name T113
Test name
Test status
Simulation time 656558769 ps
CPU time 37.37 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:26:27 PM PDT 24
Peak memory 249204 kb
Host smart-ecab6908-c460-4960-a611-7e1d8cab2a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
5446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.346905446
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.8954154
Short name T461
Test name
Test status
Simulation time 2754770713 ps
CPU time 28.81 seconds
Started Jun 27 05:25:49 PM PDT 24
Finished Jun 27 05:26:19 PM PDT 24
Peak memory 249072 kb
Host smart-b12ddd5e-a116-47e8-90c1-93f10799af7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89541
54 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.8954154
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2892585170
Short name T536
Test name
Test status
Simulation time 318420662 ps
CPU time 13.2 seconds
Started Jun 27 05:25:51 PM PDT 24
Finished Jun 27 05:26:05 PM PDT 24
Peak memory 255588 kb
Host smart-07e9984b-2d6b-450e-b9e1-39f1f15ac2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28925
85170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2892585170
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.885458397
Short name T111
Test name
Test status
Simulation time 85664410255 ps
CPU time 2661.88 seconds
Started Jun 27 05:26:17 PM PDT 24
Finished Jun 27 06:10:40 PM PDT 24
Peak memory 287048 kb
Host smart-4112934e-ff3a-4075-aa8f-cb7388bd405e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885458397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.885458397
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2975493148
Short name T618
Test name
Test status
Simulation time 361475820 ps
CPU time 41.12 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 05:26:58 PM PDT 24
Peak memory 256504 kb
Host smart-77d09502-1b31-4321-a4a2-faaeb277021f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29754
93148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2975493148
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2354897256
Short name T647
Test name
Test status
Simulation time 511890562 ps
CPU time 8.4 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:26:20 PM PDT 24
Peak memory 254160 kb
Host smart-03caf855-579f-4653-8ee2-35f073a08873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548
97256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2354897256
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.988297337
Short name T303
Test name
Test status
Simulation time 31456774740 ps
CPU time 1223.28 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:46:33 PM PDT 24
Peak memory 285308 kb
Host smart-fe3e1f5e-5909-41d3-b35e-820bbc0c9495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988297337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.988297337
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4219739224
Short name T399
Test name
Test status
Simulation time 53695123079 ps
CPU time 1355.33 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:48:48 PM PDT 24
Peak memory 289444 kb
Host smart-06a7e04f-5944-4c61-b81a-f2fe040f1d3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219739224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4219739224
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2794685786
Short name T294
Test name
Test status
Simulation time 8369529820 ps
CPU time 316.09 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 05:31:33 PM PDT 24
Peak memory 249208 kb
Host smart-073163ad-9d22-42a9-916c-d8057e76d4bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794685786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2794685786
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.699244175
Short name T528
Test name
Test status
Simulation time 3309857646 ps
CPU time 11.33 seconds
Started Jun 27 05:26:08 PM PDT 24
Finished Jun 27 05:26:20 PM PDT 24
Peak memory 257572 kb
Host smart-e37b7996-7bc2-4544-8d2d-9f2d4d2149e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69924
4175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.699244175
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3950037436
Short name T490
Test name
Test status
Simulation time 697739250 ps
CPU time 23.13 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:33 PM PDT 24
Peak memory 248332 kb
Host smart-433bc94d-be38-4cfb-a45e-d0925cddf3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
37436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3950037436
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3435883932
Short name T397
Test name
Test status
Simulation time 795940201 ps
CPU time 17 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:28 PM PDT 24
Peak memory 256860 kb
Host smart-32e0bd4c-b0c4-4f7e-a1c3-ae294c9550c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34358
83932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3435883932
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1459690111
Short name T720
Test name
Test status
Simulation time 374181094 ps
CPU time 30.41 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:40 PM PDT 24
Peak memory 257420 kb
Host smart-670454e0-7485-4926-905b-b48a045dd372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14596
90111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1459690111
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.623507106
Short name T263
Test name
Test status
Simulation time 79178106561 ps
CPU time 1689.52 seconds
Started Jun 27 05:26:07 PM PDT 24
Finished Jun 27 05:54:18 PM PDT 24
Peak memory 290276 kb
Host smart-baaa1d45-57af-4fd3-a26f-7aefc141849d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623507106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.623507106
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3847079714
Short name T269
Test name
Test status
Simulation time 49272940409 ps
CPU time 1491.98 seconds
Started Jun 27 05:26:11 PM PDT 24
Finished Jun 27 05:51:05 PM PDT 24
Peak memory 290248 kb
Host smart-fbcff0b6-c894-4308-91ce-b0ad3caa05fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847079714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3847079714
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2327156084
Short name T503
Test name
Test status
Simulation time 21635279319 ps
CPU time 987.51 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 05:42:44 PM PDT 24
Peak memory 287988 kb
Host smart-41f761b7-46e1-425e-a3ee-218399b208e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327156084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2327156084
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.53206432
Short name T462
Test name
Test status
Simulation time 2812913213 ps
CPU time 121.31 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:28:12 PM PDT 24
Peak memory 257632 kb
Host smart-dfda3e54-69de-45f7-8aba-7c46bb6d0de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53206
432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.53206432
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4048629975
Short name T460
Test name
Test status
Simulation time 341730021 ps
CPU time 4.29 seconds
Started Jun 27 05:26:08 PM PDT 24
Finished Jun 27 05:26:13 PM PDT 24
Peak memory 240456 kb
Host smart-0fe87890-ea28-4400-8a95-8590a1214de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
29975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4048629975
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3604912416
Short name T81
Test name
Test status
Simulation time 80255586934 ps
CPU time 2616.5 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 06:09:49 PM PDT 24
Peak memory 290040 kb
Host smart-55c14a7b-52aa-42ab-a491-07db03b04171
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604912416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3604912416
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1780627477
Short name T705
Test name
Test status
Simulation time 25740594966 ps
CPU time 1527.1 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:51:39 PM PDT 24
Peak memory 265784 kb
Host smart-b8991d31-424e-4189-a55a-4fde456d71dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780627477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1780627477
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1346720029
Short name T287
Test name
Test status
Simulation time 8160956568 ps
CPU time 84.79 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 05:27:41 PM PDT 24
Peak memory 249352 kb
Host smart-0abf45b0-b8a6-4351-929a-3ce8a594bdd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346720029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1346720029
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3501345555
Short name T611
Test name
Test status
Simulation time 3674420855 ps
CPU time 52.82 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:27:09 PM PDT 24
Peak memory 257300 kb
Host smart-923da32b-aa51-4f53-82e6-602119f32f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
45555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3501345555
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1793796253
Short name T676
Test name
Test status
Simulation time 784103463 ps
CPU time 44.39 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:27:00 PM PDT 24
Peak memory 248788 kb
Host smart-b44d0dd8-2776-4171-90d5-1b9a555e69fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
96253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1793796253
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2431819397
Short name T450
Test name
Test status
Simulation time 469814274 ps
CPU time 12.98 seconds
Started Jun 27 05:26:17 PM PDT 24
Finished Jun 27 05:26:31 PM PDT 24
Peak memory 257392 kb
Host smart-642fce33-e7c3-4a44-9f19-437ada4f8bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24318
19397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2431819397
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2205781784
Short name T251
Test name
Test status
Simulation time 18488664866 ps
CPU time 1510.87 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:51:22 PM PDT 24
Peak memory 290384 kb
Host smart-a5062b77-c540-4405-92c2-59f88d59f992
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205781784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2205781784
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2208828060
Short name T49
Test name
Test status
Simulation time 595079962568 ps
CPU time 9261.07 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 08:00:38 PM PDT 24
Peak memory 404576 kb
Host smart-5e4b3f81-4077-4b59-aed2-ba85e3dc57a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208828060 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2208828060
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1928960158
Short name T718
Test name
Test status
Simulation time 101802131929 ps
CPU time 1669.61 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:53:59 PM PDT 24
Peak memory 273964 kb
Host smart-68aff21b-4dd4-4f37-985b-dff7b67ecf67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928960158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1928960158
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.703254791
Short name T458
Test name
Test status
Simulation time 1293864430 ps
CPU time 50.24 seconds
Started Jun 27 05:26:16 PM PDT 24
Finished Jun 27 05:27:08 PM PDT 24
Peak memory 250276 kb
Host smart-73ac36bb-a36d-4a20-9f69-6cc5db5366b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70325
4791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.703254791
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.4265998487
Short name T673
Test name
Test status
Simulation time 1891314995 ps
CPU time 55.01 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:27:07 PM PDT 24
Peak memory 257364 kb
Host smart-ffcddda7-1818-4380-bff2-6dcb426a6965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
98487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4265998487
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3941432088
Short name T274
Test name
Test status
Simulation time 98310430768 ps
CPU time 1485.44 seconds
Started Jun 27 05:26:08 PM PDT 24
Finished Jun 27 05:50:54 PM PDT 24
Peak memory 273140 kb
Host smart-29620430-2de1-4e35-99fc-0b7e026f8924
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941432088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3941432088
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2442571781
Short name T619
Test name
Test status
Simulation time 83316516388 ps
CPU time 2522.69 seconds
Started Jun 27 05:26:17 PM PDT 24
Finished Jun 27 06:08:21 PM PDT 24
Peak memory 289772 kb
Host smart-ee09d460-5956-4315-9b59-827b7e1091b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442571781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2442571781
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3278129593
Short name T286
Test name
Test status
Simulation time 11193534419 ps
CPU time 238.39 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:30:10 PM PDT 24
Peak memory 249400 kb
Host smart-4ea2d304-897c-4c22-a55c-c02b13876e00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278129593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3278129593
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.324612601
Short name T636
Test name
Test status
Simulation time 1488890653 ps
CPU time 53.95 seconds
Started Jun 27 05:26:08 PM PDT 24
Finished Jun 27 05:27:02 PM PDT 24
Peak memory 257356 kb
Host smart-f46a5a91-ac05-4095-87e8-e5eff8832757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32461
2601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.324612601
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2475344900
Short name T105
Test name
Test status
Simulation time 1380158405 ps
CPU time 50.83 seconds
Started Jun 27 05:26:11 PM PDT 24
Finished Jun 27 05:27:04 PM PDT 24
Peak memory 256940 kb
Host smart-aa986a2a-9b24-45f1-b334-fe16ab7bdc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24753
44900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2475344900
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3724003007
Short name T542
Test name
Test status
Simulation time 377008601 ps
CPU time 5.7 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:16 PM PDT 24
Peak memory 240580 kb
Host smart-6b55e04d-b6d1-47ee-bb39-10faf320737e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240
03007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3724003007
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1612516984
Short name T364
Test name
Test status
Simulation time 450329146 ps
CPU time 12.72 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 05:26:29 PM PDT 24
Peak memory 257432 kb
Host smart-d2aee9d4-487d-450b-ba30-59fd0b42a6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
16984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1612516984
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.378243473
Short name T369
Test name
Test status
Simulation time 7883132413 ps
CPU time 185.13 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:29:15 PM PDT 24
Peak memory 257608 kb
Host smart-a3ee5edd-6e0d-49f6-a9e1-32595da56520
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378243473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.378243473
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.663248221
Short name T85
Test name
Test status
Simulation time 74813865449 ps
CPU time 5548.23 seconds
Started Jun 27 05:26:15 PM PDT 24
Finished Jun 27 06:58:45 PM PDT 24
Peak memory 371672 kb
Host smart-fc25b5f6-400e-4fb5-a7ed-3c61f09d53f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663248221 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.663248221
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1712650047
Short name T690
Test name
Test status
Simulation time 173763312713 ps
CPU time 1500.01 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:51:10 PM PDT 24
Peak memory 268920 kb
Host smart-ef120fef-5b8c-4193-939d-ef3643a4dd9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712650047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1712650047
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.508865650
Short name T631
Test name
Test status
Simulation time 1667621374 ps
CPU time 135.54 seconds
Started Jun 27 05:26:17 PM PDT 24
Finished Jun 27 05:28:33 PM PDT 24
Peak memory 256984 kb
Host smart-609f77b2-3ad1-4e91-a22f-349182647c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50886
5650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.508865650
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1330079424
Short name T603
Test name
Test status
Simulation time 1136531598 ps
CPU time 38.18 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:26:49 PM PDT 24
Peak memory 256960 kb
Host smart-c6432973-da5a-47e5-ae4f-42171f211c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13300
79424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1330079424
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2856258347
Short name T91
Test name
Test status
Simulation time 175035673506 ps
CPU time 2540.72 seconds
Started Jun 27 05:26:07 PM PDT 24
Finished Jun 27 06:08:28 PM PDT 24
Peak memory 290300 kb
Host smart-533053c9-9f88-4369-b1de-af2915130af5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856258347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2856258347
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3024646742
Short name T299
Test name
Test status
Simulation time 26230591810 ps
CPU time 559.78 seconds
Started Jun 27 05:26:14 PM PDT 24
Finished Jun 27 05:35:35 PM PDT 24
Peak memory 249328 kb
Host smart-0c2fe19a-a6e2-4a5b-83bf-c0b3040f236a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024646742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3024646742
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2795041130
Short name T641
Test name
Test status
Simulation time 1863174917 ps
CPU time 20.03 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:30 PM PDT 24
Peak memory 249176 kb
Host smart-c20a488a-9144-42cc-b0e4-09eadaee372f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27950
41130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2795041130
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.824167166
Short name T195
Test name
Test status
Simulation time 1524684010 ps
CPU time 51.08 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:27:02 PM PDT 24
Peak memory 256628 kb
Host smart-5980bb10-f12d-4a95-8296-5b40480be407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82416
7166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.824167166
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2428369586
Short name T524
Test name
Test status
Simulation time 163652643 ps
CPU time 15.1 seconds
Started Jun 27 05:26:10 PM PDT 24
Finished Jun 27 05:26:26 PM PDT 24
Peak memory 257480 kb
Host smart-bd901a15-37ac-4261-8029-5f29402887a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
69586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2428369586
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2907053005
Short name T97
Test name
Test status
Simulation time 234763478009 ps
CPU time 3242.2 seconds
Started Jun 27 05:26:18 PM PDT 24
Finished Jun 27 06:20:21 PM PDT 24
Peak memory 298516 kb
Host smart-833e3d85-901e-4849-8b89-2cf31ee948e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907053005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2907053005
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1900501557
Short name T638
Test name
Test status
Simulation time 16082003702 ps
CPU time 1254.88 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:47:25 PM PDT 24
Peak memory 290140 kb
Host smart-7acb64c9-d21a-40cc-aa38-eab7d5078bac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900501557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1900501557
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.540547010
Short name T491
Test name
Test status
Simulation time 6253716834 ps
CPU time 129.15 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:28:38 PM PDT 24
Peak memory 257524 kb
Host smart-c46a29a4-da1d-4ad3-83da-d935cece402f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54054
7010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.540547010
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3612459184
Short name T577
Test name
Test status
Simulation time 779621353 ps
CPU time 45.94 seconds
Started Jun 27 05:26:35 PM PDT 24
Finished Jun 27 05:27:22 PM PDT 24
Peak memory 257260 kb
Host smart-4bf74c1a-b94c-48f7-a489-94b476e886e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
59184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3612459184
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3249158909
Short name T100
Test name
Test status
Simulation time 8484307962 ps
CPU time 693.05 seconds
Started Jun 27 05:26:25 PM PDT 24
Finished Jun 27 05:38:00 PM PDT 24
Peak memory 273888 kb
Host smart-cb2444b8-edcb-4706-837c-ddba339dc354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249158909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3249158909
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2471872052
Short name T507
Test name
Test status
Simulation time 79989575231 ps
CPU time 1761.88 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:55:49 PM PDT 24
Peak memory 290160 kb
Host smart-9eac14eb-531f-44a0-aae1-71a80b93bccc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471872052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2471872052
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.370968156
Short name T661
Test name
Test status
Simulation time 12958389108 ps
CPU time 290.6 seconds
Started Jun 27 05:26:29 PM PDT 24
Finished Jun 27 05:31:22 PM PDT 24
Peak memory 249448 kb
Host smart-4a8bd258-088a-4307-b51e-53ba5fa01952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370968156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.370968156
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.851707736
Short name T628
Test name
Test status
Simulation time 117869082 ps
CPU time 8.85 seconds
Started Jun 27 05:26:09 PM PDT 24
Finished Jun 27 05:26:19 PM PDT 24
Peak memory 252004 kb
Host smart-9eb55e7f-4837-40d5-a0e8-5d54eea58c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85170
7736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.851707736
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3459370006
Short name T635
Test name
Test status
Simulation time 3085176039 ps
CPU time 51.03 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:27:21 PM PDT 24
Peak memory 249184 kb
Host smart-9c4865fd-8ef0-4b35-9c82-00c2814db945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
70006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3459370006
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1184389323
Short name T543
Test name
Test status
Simulation time 168285150 ps
CPU time 6.22 seconds
Started Jun 27 05:26:25 PM PDT 24
Finished Jun 27 05:26:33 PM PDT 24
Peak memory 253164 kb
Host smart-6d094b7d-0504-4fbd-95c9-b9c84fdf23c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11843
89323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1184389323
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3719837171
Short name T194
Test name
Test status
Simulation time 1045096016 ps
CPU time 22.64 seconds
Started Jun 27 05:26:11 PM PDT 24
Finished Jun 27 05:26:36 PM PDT 24
Peak memory 257212 kb
Host smart-bfa148e2-4308-4f93-b9f2-fe27aad00924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198
37171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3719837171
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1735470525
Short name T648
Test name
Test status
Simulation time 1139920934 ps
CPU time 76.25 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:27:47 PM PDT 24
Peak memory 257472 kb
Host smart-776ffe05-52d8-4bcf-8bc9-f232126e0623
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735470525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1735470525
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.866739774
Short name T110
Test name
Test status
Simulation time 26799780399 ps
CPU time 2904.45 seconds
Started Jun 27 05:26:35 PM PDT 24
Finished Jun 27 06:15:01 PM PDT 24
Peak memory 321652 kb
Host smart-92f315a6-f33c-4af9-899e-e50bb41c55de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866739774 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.866739774
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1639944040
Short name T214
Test name
Test status
Simulation time 158024297 ps
CPU time 2.31 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:23:53 PM PDT 24
Peak memory 249528 kb
Host smart-22872ae6-b675-4447-a768-f85114fe2251
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1639944040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1639944040
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1179497685
Short name T534
Test name
Test status
Simulation time 41757869214 ps
CPU time 1014.75 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 05:40:44 PM PDT 24
Peak memory 289336 kb
Host smart-20373822-a370-4164-acb7-ea85e94388c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179497685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1179497685
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3587686249
Short name T419
Test name
Test status
Simulation time 3389299838 ps
CPU time 18.14 seconds
Started Jun 27 05:23:49 PM PDT 24
Finished Jun 27 05:24:10 PM PDT 24
Peak memory 249432 kb
Host smart-13808fe5-a8a6-493a-8e84-1fec8fc835ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3587686249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3587686249
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2061123726
Short name T607
Test name
Test status
Simulation time 14318508900 ps
CPU time 127.32 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:25:58 PM PDT 24
Peak memory 257584 kb
Host smart-a656c063-752a-4530-9e87-3bf0b3688e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20611
23726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2061123726
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.563068713
Short name T686
Test name
Test status
Simulation time 53146339 ps
CPU time 4.46 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:23:55 PM PDT 24
Peak memory 240424 kb
Host smart-bc5e0969-4a11-4520-ba09-58443c8bdc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56306
8713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.563068713
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3491677479
Short name T614
Test name
Test status
Simulation time 86459961976 ps
CPU time 758.53 seconds
Started Jun 27 05:23:50 PM PDT 24
Finished Jun 27 05:36:31 PM PDT 24
Peak memory 274008 kb
Host smart-e955f58b-9312-4ae1-91b5-ba47c228acc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491677479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3491677479
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3924276936
Short name T677
Test name
Test status
Simulation time 286850017577 ps
CPU time 1956.98 seconds
Started Jun 27 05:23:48 PM PDT 24
Finished Jun 27 05:56:28 PM PDT 24
Peak memory 290124 kb
Host smart-4ee45cec-f0fe-4ed8-bebe-70d33f424494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924276936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3924276936
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.729694586
Short name T300
Test name
Test status
Simulation time 6084289965 ps
CPU time 251.52 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:28:02 PM PDT 24
Peak memory 249404 kb
Host smart-379c18ab-9579-4006-8b3a-37ee4f8429bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729694586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.729694586
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2663009431
Short name T439
Test name
Test status
Simulation time 161260564 ps
CPU time 4.49 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:23:55 PM PDT 24
Peak memory 249260 kb
Host smart-7a07198b-316f-4bf2-a433-379cceb66579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
09431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2663009431
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2775724114
Short name T693
Test name
Test status
Simulation time 1329731821 ps
CPU time 23.2 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 05:24:13 PM PDT 24
Peak memory 248580 kb
Host smart-ecbd9b1c-5c95-462d-b38f-baf0a91acbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27757
24114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2775724114
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1222916388
Short name T33
Test name
Test status
Simulation time 1151509260 ps
CPU time 12.67 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:24:03 PM PDT 24
Peak memory 271316 kb
Host smart-724684ef-5d88-4b41-912d-b822be34875d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1222916388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1222916388
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2649882379
Short name T658
Test name
Test status
Simulation time 655095678 ps
CPU time 29.91 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:24:20 PM PDT 24
Peak memory 256680 kb
Host smart-5818832c-b994-4ffe-b70e-40f004c02549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
82379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2649882379
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.574432525
Short name T427
Test name
Test status
Simulation time 519611753 ps
CPU time 28.81 seconds
Started Jun 27 05:23:28 PM PDT 24
Finished Jun 27 05:23:59 PM PDT 24
Peak memory 257416 kb
Host smart-030d2e96-45f8-4521-bfcd-dd21f7b08d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57443
2525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.574432525
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2868850652
Short name T98
Test name
Test status
Simulation time 33473006075 ps
CPU time 882.33 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 05:38:32 PM PDT 24
Peak memory 273968 kb
Host smart-b5512d67-4dfa-47d8-8c12-1092712ef6ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868850652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2868850652
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4042344711
Short name T40
Test name
Test status
Simulation time 48346352940 ps
CPU time 2680.88 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 06:11:11 PM PDT 24
Peak memory 289552 kb
Host smart-12edc3dc-80cb-4e23-991b-0ea6d3b351ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042344711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4042344711
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2369307238
Short name T582
Test name
Test status
Simulation time 642517561 ps
CPU time 42.2 seconds
Started Jun 27 05:26:29 PM PDT 24
Finished Jun 27 05:27:14 PM PDT 24
Peak memory 256748 kb
Host smart-22534d0f-e336-41ab-b21d-8869c49d5988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
07238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2369307238
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.769343658
Short name T573
Test name
Test status
Simulation time 4364606744 ps
CPU time 46.94 seconds
Started Jun 27 05:26:35 PM PDT 24
Finished Jun 27 05:27:23 PM PDT 24
Peak memory 257396 kb
Host smart-d669e984-ba5a-46d8-8cd1-72a8a916fd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76934
3658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.769343658
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3606066502
Short name T474
Test name
Test status
Simulation time 12096643636 ps
CPU time 1215.31 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:46:46 PM PDT 24
Peak memory 289596 kb
Host smart-f9d6a1bd-5514-48cb-b93b-3554774fa6e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606066502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3606066502
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.120923553
Short name T407
Test name
Test status
Simulation time 87824760477 ps
CPU time 618.16 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:36:47 PM PDT 24
Peak memory 273536 kb
Host smart-5cd46656-d6f1-4d88-bf35-796bf0e94767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120923553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.120923553
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.970134971
Short name T284
Test name
Test status
Simulation time 30130242820 ps
CPU time 307.33 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:31:36 PM PDT 24
Peak memory 248924 kb
Host smart-c70b6399-45ae-4c89-8975-56adabea0eb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970134971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.970134971
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1180154968
Short name T390
Test name
Test status
Simulation time 126039403 ps
CPU time 14.66 seconds
Started Jun 27 05:26:35 PM PDT 24
Finished Jun 27 05:26:51 PM PDT 24
Peak memory 255872 kb
Host smart-2e591db8-3f4f-45f3-8f6b-3b18f729984b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11801
54968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1180154968
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4223832649
Short name T411
Test name
Test status
Simulation time 419223172 ps
CPU time 14.45 seconds
Started Jun 27 05:26:29 PM PDT 24
Finished Jun 27 05:26:46 PM PDT 24
Peak memory 255424 kb
Host smart-544c78dc-0fb5-4bfe-881f-490f88eaa0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42238
32649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4223832649
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.754757504
Short name T254
Test name
Test status
Simulation time 495868775 ps
CPU time 17.41 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:26:47 PM PDT 24
Peak memory 256300 kb
Host smart-3b1a519e-9ffe-45d7-a397-ff8f969b0eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75475
7504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.754757504
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2987209629
Short name T73
Test name
Test status
Simulation time 794464050 ps
CPU time 53.88 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:27:21 PM PDT 24
Peak memory 257348 kb
Host smart-8c6308f3-6feb-4532-b9dc-7de278836d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872
09629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2987209629
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.207142768
Short name T256
Test name
Test status
Simulation time 53216020763 ps
CPU time 941.02 seconds
Started Jun 27 05:26:30 PM PDT 24
Finished Jun 27 05:42:13 PM PDT 24
Peak memory 289960 kb
Host smart-cb5526ba-c286-4caa-ba54-ec941a265746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207142768 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.207142768
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.283706456
Short name T103
Test name
Test status
Simulation time 66655077381 ps
CPU time 1968.24 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:59:17 PM PDT 24
Peak memory 289244 kb
Host smart-e5e80521-820c-4747-af68-fb357e0261f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283706456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.283706456
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1522639346
Short name T385
Test name
Test status
Simulation time 8443769303 ps
CPU time 292.79 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:31:24 PM PDT 24
Peak memory 257544 kb
Host smart-aa2888a8-8a23-4e90-b0f5-8779da53f02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15226
39346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1522639346
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3062400402
Short name T685
Test name
Test status
Simulation time 232506766 ps
CPU time 17.01 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:26:46 PM PDT 24
Peak memory 248744 kb
Host smart-02d70f43-890b-4cea-b5f0-6d830b47d5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
00402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3062400402
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1131887088
Short name T472
Test name
Test status
Simulation time 11041823520 ps
CPU time 1454.71 seconds
Started Jun 27 05:26:34 PM PDT 24
Finished Jun 27 05:50:50 PM PDT 24
Peak memory 290396 kb
Host smart-dc9f4f89-b7ef-410e-946f-9f66ced4eccb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131887088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1131887088
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1963084446
Short name T280
Test name
Test status
Simulation time 5444990383 ps
CPU time 112.71 seconds
Started Jun 27 05:26:27 PM PDT 24
Finished Jun 27 05:28:23 PM PDT 24
Peak memory 249356 kb
Host smart-0b9359e9-f3c6-4570-b198-acf4977dfb17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963084446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1963084446
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3635919542
Short name T530
Test name
Test status
Simulation time 686970591 ps
CPU time 42.57 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:27:13 PM PDT 24
Peak memory 257244 kb
Host smart-bbf6b4c9-6a66-4f69-9bdd-94a20aaadc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359
19542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3635919542
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2781563474
Short name T392
Test name
Test status
Simulation time 3154354284 ps
CPU time 36.99 seconds
Started Jun 27 05:26:29 PM PDT 24
Finished Jun 27 05:27:09 PM PDT 24
Peak memory 257160 kb
Host smart-155b391b-8d71-444e-b300-f4319896ecce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27815
63474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2781563474
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2127450665
Short name T578
Test name
Test status
Simulation time 299894124 ps
CPU time 22.08 seconds
Started Jun 27 05:26:26 PM PDT 24
Finished Jun 27 05:26:50 PM PDT 24
Peak memory 256772 kb
Host smart-7a8e650a-0d3c-4942-91b1-da0c55a220e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274
50665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2127450665
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.20056271
Short name T656
Test name
Test status
Simulation time 3876488152 ps
CPU time 58.34 seconds
Started Jun 27 05:26:28 PM PDT 24
Finished Jun 27 05:27:29 PM PDT 24
Peak memory 257588 kb
Host smart-f85d2c4d-55a1-4ba8-9267-7d5be6c7e75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20056
271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.20056271
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3884298463
Short name T55
Test name
Test status
Simulation time 9940551344 ps
CPU time 258.38 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:31:03 PM PDT 24
Peak memory 257564 kb
Host smart-0a79c9e1-dfc2-420e-baa5-5840eaf4c721
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884298463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3884298463
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.857814580
Short name T395
Test name
Test status
Simulation time 4860628985 ps
CPU time 564.44 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:36:11 PM PDT 24
Peak memory 265832 kb
Host smart-fb4706e4-4d16-47d5-adac-c0968ce2db98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857814580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.857814580
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3219198721
Short name T574
Test name
Test status
Simulation time 1515813459 ps
CPU time 122.18 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:28:48 PM PDT 24
Peak memory 257380 kb
Host smart-bf63f391-10fa-4864-bc75-25af1e8826cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32191
98721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3219198721
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3251059159
Short name T59
Test name
Test status
Simulation time 357837664 ps
CPU time 5.79 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:26:54 PM PDT 24
Peak memory 248556 kb
Host smart-9a2f13df-751b-4d8d-8dc7-f6864bdf2376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32510
59159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3251059159
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1553739683
Short name T663
Test name
Test status
Simulation time 16956335266 ps
CPU time 1381.93 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:49:48 PM PDT 24
Peak memory 290296 kb
Host smart-fbfbd256-3aa8-4f13-bfba-cc6edee51ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553739683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1553739683
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.440521813
Short name T643
Test name
Test status
Simulation time 15750888800 ps
CPU time 1423.18 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:50:32 PM PDT 24
Peak memory 288476 kb
Host smart-5ef1e4cb-b53d-4a01-8b9f-6cfcced6fd3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440521813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.440521813
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2787591839
Short name T10
Test name
Test status
Simulation time 3547133825 ps
CPU time 152.72 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:29:17 PM PDT 24
Peak memory 249324 kb
Host smart-08e9fb6b-eaa8-4a92-b4f9-5f2c8f103f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787591839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2787591839
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2022644428
Short name T389
Test name
Test status
Simulation time 574450930 ps
CPU time 35.39 seconds
Started Jun 27 05:26:46 PM PDT 24
Finished Jun 27 05:27:23 PM PDT 24
Peak memory 249420 kb
Host smart-215ebf06-755d-42bf-a199-cb737ce63b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20226
44428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2022644428
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3130628932
Short name T637
Test name
Test status
Simulation time 1077324528 ps
CPU time 27.23 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:27:13 PM PDT 24
Peak memory 257344 kb
Host smart-17186186-61e3-48f2-8191-babcee699bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31306
28932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3130628932
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1009339269
Short name T464
Test name
Test status
Simulation time 94833405 ps
CPU time 8.11 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:26:54 PM PDT 24
Peak memory 248808 kb
Host smart-bb621e2f-bb72-4f47-9815-72fa1873f6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
39269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1009339269
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3054804581
Short name T703
Test name
Test status
Simulation time 1220046385 ps
CPU time 36.89 seconds
Started Jun 27 05:26:43 PM PDT 24
Finished Jun 27 05:27:21 PM PDT 24
Peak memory 256496 kb
Host smart-43d8897d-068c-49a0-b4b6-0a5364388c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30548
04581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3054804581
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2898259970
Short name T629
Test name
Test status
Simulation time 85123023140 ps
CPU time 1555.71 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:52:41 PM PDT 24
Peak memory 290288 kb
Host smart-b26330b3-e486-44e9-9c43-cb1ccba64ed3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898259970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2898259970
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.36842469
Short name T509
Test name
Test status
Simulation time 41967474269 ps
CPU time 819.72 seconds
Started Jun 27 05:26:43 PM PDT 24
Finished Jun 27 05:40:23 PM PDT 24
Peak memory 290396 kb
Host smart-11326b1d-0637-4646-a5d5-8fa263374ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36842469 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.36842469
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2455756066
Short name T477
Test name
Test status
Simulation time 38653951716 ps
CPU time 1833.73 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:57:22 PM PDT 24
Peak memory 283444 kb
Host smart-9b36ac8a-f590-4ab1-bf70-c57c7c995366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455756066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2455756066
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1407181310
Short name T555
Test name
Test status
Simulation time 1776826951 ps
CPU time 156.81 seconds
Started Jun 27 05:26:46 PM PDT 24
Finished Jun 27 05:29:25 PM PDT 24
Peak memory 257684 kb
Host smart-06125d17-46f6-4ecc-b484-aeee7b7b40f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
81310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1407181310
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1123747625
Short name T266
Test name
Test status
Simulation time 4539780157 ps
CPU time 56.54 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:27:45 PM PDT 24
Peak memory 248776 kb
Host smart-a0292bab-a9a0-4f7b-9191-f25fa394e30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11237
47625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1123747625
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3489360820
Short name T608
Test name
Test status
Simulation time 101296785 ps
CPU time 9.98 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:26:56 PM PDT 24
Peak memory 249216 kb
Host smart-e11c16eb-5087-4602-8d13-532c61e4bb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
60820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3489360820
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3971008341
Short name T372
Test name
Test status
Simulation time 729188995 ps
CPU time 6.04 seconds
Started Jun 27 05:26:48 PM PDT 24
Finished Jun 27 05:26:55 PM PDT 24
Peak memory 251732 kb
Host smart-f965b998-9508-4e86-a142-37ceea88f3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39710
08341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3971008341
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.4136141948
Short name T612
Test name
Test status
Simulation time 163510244 ps
CPU time 12.04 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:26:58 PM PDT 24
Peak memory 255268 kb
Host smart-09e213f1-ba20-40f5-957c-6e2311d0e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41361
41948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4136141948
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1396769329
Short name T371
Test name
Test status
Simulation time 675035306 ps
CPU time 44.31 seconds
Started Jun 27 05:26:47 PM PDT 24
Finished Jun 27 05:27:33 PM PDT 24
Peak memory 249208 kb
Host smart-15ad483b-e0b7-46b9-9679-32c25cc46eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13967
69329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1396769329
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.156745153
Short name T581
Test name
Test status
Simulation time 189699299740 ps
CPU time 2015.49 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 06:00:39 PM PDT 24
Peak memory 273868 kb
Host smart-4b9d2274-34cd-4956-9dd1-6781902f978d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156745153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.156745153
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3268107105
Short name T449
Test name
Test status
Simulation time 4716139449 ps
CPU time 273.29 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:31:18 PM PDT 24
Peak memory 256888 kb
Host smart-694f47a7-e6d8-4e9f-bc0d-5a4b4b168da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32681
07105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3268107105
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3811112358
Short name T709
Test name
Test status
Simulation time 55930858 ps
CPU time 2.67 seconds
Started Jun 27 05:26:44 PM PDT 24
Finished Jun 27 05:26:47 PM PDT 24
Peak memory 249284 kb
Host smart-dfb9be80-2bcf-40bc-b4d3-06cfd0e951e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38111
12358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3811112358
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1016675750
Short name T272
Test name
Test status
Simulation time 68787761063 ps
CPU time 1055.7 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:44:39 PM PDT 24
Peak memory 273284 kb
Host smart-96f42057-59bb-49fc-b2bf-96efccbd2da4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016675750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1016675750
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3597265309
Short name T714
Test name
Test status
Simulation time 55030270675 ps
CPU time 1064.62 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:44:47 PM PDT 24
Peak memory 273876 kb
Host smart-9972313a-574b-4e92-82c7-d1855e4683cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597265309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3597265309
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.866409272
Short name T591
Test name
Test status
Simulation time 30477134773 ps
CPU time 307.36 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:32:10 PM PDT 24
Peak memory 255956 kb
Host smart-2cadf44c-9135-4ef8-b80f-8307020f3977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866409272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.866409272
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.513719597
Short name T610
Test name
Test status
Simulation time 2973523805 ps
CPU time 19.99 seconds
Started Jun 27 05:26:49 PM PDT 24
Finished Jun 27 05:27:10 PM PDT 24
Peak memory 257428 kb
Host smart-16294bf5-4f6b-4d74-b2e3-14dd19264087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51371
9597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.513719597
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3508935700
Short name T192
Test name
Test status
Simulation time 71729246 ps
CPU time 5.42 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:26:52 PM PDT 24
Peak memory 252352 kb
Host smart-cbb992d3-6d73-4229-b2e7-c206ca0df68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
35700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3508935700
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4048251255
Short name T310
Test name
Test status
Simulation time 883112386 ps
CPU time 28.09 seconds
Started Jun 27 05:26:43 PM PDT 24
Finished Jun 27 05:27:12 PM PDT 24
Peak memory 257016 kb
Host smart-759282f7-2f44-427b-a8ca-eab74eb89b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
51255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4048251255
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3561147855
Short name T668
Test name
Test status
Simulation time 390840872 ps
CPU time 14.45 seconds
Started Jun 27 05:26:45 PM PDT 24
Finished Jun 27 05:27:00 PM PDT 24
Peak memory 249188 kb
Host smart-3fb059bb-631a-4306-a8b4-2091dea70f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35611
47855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3561147855
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1365047135
Short name T314
Test name
Test status
Simulation time 60277890475 ps
CPU time 2107.35 seconds
Started Jun 27 05:27:03 PM PDT 24
Finished Jun 27 06:02:12 PM PDT 24
Peak memory 290320 kb
Host smart-9c2c2a88-519a-4481-a599-dc9713de01c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365047135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1365047135
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.505144321
Short name T239
Test name
Test status
Simulation time 17138809210 ps
CPU time 1178.48 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:46:42 PM PDT 24
Peak memory 274000 kb
Host smart-f3ad8ed6-586d-4cdf-950d-6956cc89c6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505144321 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.505144321
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2606320005
Short name T433
Test name
Test status
Simulation time 132962126095 ps
CPU time 1957.1 seconds
Started Jun 27 05:27:03 PM PDT 24
Finished Jun 27 05:59:42 PM PDT 24
Peak memory 284868 kb
Host smart-b992b40d-7360-42a2-8af8-3591ab9fc22a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606320005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2606320005
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3449826429
Short name T489
Test name
Test status
Simulation time 16616210660 ps
CPU time 259 seconds
Started Jun 27 05:27:03 PM PDT 24
Finished Jun 27 05:31:24 PM PDT 24
Peak memory 252412 kb
Host smart-b7e86ee1-6638-4b2a-8bde-1bc749cf195e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498
26429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3449826429
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.65666950
Short name T699
Test name
Test status
Simulation time 483479577 ps
CPU time 20.18 seconds
Started Jun 27 05:27:00 PM PDT 24
Finished Jun 27 05:27:21 PM PDT 24
Peak memory 249788 kb
Host smart-bb4933d4-0e28-489f-bc43-a12de122fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65666
950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.65666950
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1231868303
Short name T529
Test name
Test status
Simulation time 12478101341 ps
CPU time 661.92 seconds
Started Jun 27 05:27:02 PM PDT 24
Finished Jun 27 05:38:06 PM PDT 24
Peak memory 271628 kb
Host smart-37525ad0-14d1-4fc7-9177-aa40b91ed6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231868303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1231868303
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4140153628
Short name T84
Test name
Test status
Simulation time 28580363303 ps
CPU time 1293.92 seconds
Started Jun 27 05:27:04 PM PDT 24
Finished Jun 27 05:48:40 PM PDT 24
Peak memory 289460 kb
Host smart-091e74d5-2b94-4f6f-9735-1d976ae6b739
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140153628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4140153628
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1710340778
Short name T417
Test name
Test status
Simulation time 7787148169 ps
CPU time 59.75 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:28:02 PM PDT 24
Peak memory 257136 kb
Host smart-181fa4fa-7348-4604-a39f-fcf4514f43fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17103
40778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1710340778
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1107817625
Short name T653
Test name
Test status
Simulation time 71448875 ps
CPU time 6.12 seconds
Started Jun 27 05:27:03 PM PDT 24
Finished Jun 27 05:27:11 PM PDT 24
Peak memory 248448 kb
Host smart-c2f01479-b3a2-498c-b28b-7ab748c96a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
17625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1107817625
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1515132079
Short name T724
Test name
Test status
Simulation time 1088366137 ps
CPU time 23.43 seconds
Started Jun 27 05:27:00 PM PDT 24
Finished Jun 27 05:27:25 PM PDT 24
Peak memory 256188 kb
Host smart-3d648174-036b-4ae8-88bd-eeb6e3a820f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
32079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1515132079
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2952822377
Short name T584
Test name
Test status
Simulation time 534857214 ps
CPU time 35.55 seconds
Started Jun 27 05:27:05 PM PDT 24
Finished Jun 27 05:27:42 PM PDT 24
Peak memory 257352 kb
Host smart-e93c2476-813d-444f-af4c-004ab304d0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29528
22377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2952822377
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.87477049
Short name T655
Test name
Test status
Simulation time 71042057851 ps
CPU time 1716.57 seconds
Started Jun 27 05:27:04 PM PDT 24
Finished Jun 27 05:55:43 PM PDT 24
Peak memory 289664 kb
Host smart-b227851b-e599-48ed-912c-bc398920016d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87477049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_hand
ler_stress_all.87477049
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3426051117
Short name T649
Test name
Test status
Simulation time 360707610703 ps
CPU time 2185.31 seconds
Started Jun 27 05:27:02 PM PDT 24
Finished Jun 27 06:03:29 PM PDT 24
Peak memory 290136 kb
Host smart-d0e6583e-89b3-4a0a-affa-4739cf40c0a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426051117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3426051117
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3156204095
Short name T606
Test name
Test status
Simulation time 10716745040 ps
CPU time 163.3 seconds
Started Jun 27 05:27:00 PM PDT 24
Finished Jun 27 05:29:45 PM PDT 24
Peak memory 257548 kb
Host smart-9a7205a6-1732-46dd-9983-95640b67a11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
04095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3156204095
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3662844679
Short name T422
Test name
Test status
Simulation time 1221343549 ps
CPU time 40.63 seconds
Started Jun 27 05:27:00 PM PDT 24
Finished Jun 27 05:27:43 PM PDT 24
Peak memory 249680 kb
Host smart-8178180c-163e-48be-ba08-3e544bbe2187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36628
44679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3662844679
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2430375655
Short name T343
Test name
Test status
Simulation time 69663257841 ps
CPU time 2141.91 seconds
Started Jun 27 05:27:00 PM PDT 24
Finished Jun 27 06:02:43 PM PDT 24
Peak memory 289604 kb
Host smart-3b0b6fe6-22e8-43a7-a674-8440dc9532b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430375655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2430375655
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1048220779
Short name T623
Test name
Test status
Simulation time 39385810672 ps
CPU time 1265.59 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:48:42 PM PDT 24
Peak memory 289436 kb
Host smart-b51ba8d2-48de-4e51-9229-cc81b9dffe23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048220779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1048220779
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2705893269
Short name T523
Test name
Test status
Simulation time 3216167849 ps
CPU time 137.14 seconds
Started Jun 27 05:27:04 PM PDT 24
Finished Jun 27 05:29:23 PM PDT 24
Peak memory 249372 kb
Host smart-1d0b98f0-09db-4c7b-bf15-dc8b102239ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705893269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2705893269
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3392166005
Short name T571
Test name
Test status
Simulation time 761684638 ps
CPU time 29.36 seconds
Started Jun 27 05:27:01 PM PDT 24
Finished Jun 27 05:27:32 PM PDT 24
Peak memory 249292 kb
Host smart-9476cd2d-be24-4336-b235-928d7614fe7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33921
66005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3392166005
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3586370986
Short name T678
Test name
Test status
Simulation time 180827082 ps
CPU time 12.12 seconds
Started Jun 27 05:27:03 PM PDT 24
Finished Jun 27 05:27:17 PM PDT 24
Peak memory 249248 kb
Host smart-1373ad14-8cb9-436c-ae59-fca585de7640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863
70986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3586370986
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.285652805
Short name T408
Test name
Test status
Simulation time 440559883 ps
CPU time 26.52 seconds
Started Jun 27 05:27:02 PM PDT 24
Finished Jun 27 05:27:30 PM PDT 24
Peak memory 256500 kb
Host smart-45fe287f-feb8-49d2-ac48-c06884f00d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28565
2805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.285652805
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.398921796
Short name T47
Test name
Test status
Simulation time 65192836326 ps
CPU time 1296.22 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:49:14 PM PDT 24
Peak memory 287292 kb
Host smart-b3afcb96-0d65-473e-8ba2-acd4a266f1cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398921796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.398921796
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3413842497
Short name T384
Test name
Test status
Simulation time 27093707688 ps
CPU time 1632.63 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:54:49 PM PDT 24
Peak memory 273588 kb
Host smart-7acabfef-2f28-4e19-8cfe-46174fd0a487
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413842497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3413842497
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3976046375
Short name T609
Test name
Test status
Simulation time 42914149 ps
CPU time 5.53 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:27:41 PM PDT 24
Peak memory 248744 kb
Host smart-0b29e586-b9c7-41f6-a1a7-8ca62cd484f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
46375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3976046375
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.265547030
Short name T442
Test name
Test status
Simulation time 989762912 ps
CPU time 53.68 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:28:32 PM PDT 24
Peak memory 249880 kb
Host smart-0e258c33-2081-467f-a8fe-ec2d83e326c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554
7030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.265547030
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.83996503
Short name T80
Test name
Test status
Simulation time 131081157700 ps
CPU time 2108.85 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 06:02:46 PM PDT 24
Peak memory 289664 kb
Host smart-8dda89ad-71d7-4930-941c-0ac3bf3e3050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83996503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.83996503
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1253895024
Short name T518
Test name
Test status
Simulation time 78285071330 ps
CPU time 1823.9 seconds
Started Jun 27 05:27:32 PM PDT 24
Finished Jun 27 05:57:57 PM PDT 24
Peak memory 273916 kb
Host smart-a1655736-787c-4a64-8c16-94f8d08f5866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253895024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1253895024
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1584469453
Short name T424
Test name
Test status
Simulation time 61319298 ps
CPU time 7.37 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:27:43 PM PDT 24
Peak memory 254244 kb
Host smart-b8dc6215-f8c1-43e1-8d1f-1c84d35106cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
69453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1584469453
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2746921008
Short name T381
Test name
Test status
Simulation time 246241154 ps
CPU time 14.7 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:27:51 PM PDT 24
Peak memory 248764 kb
Host smart-e867fad0-35b1-4cfa-9b28-11d03568aeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27469
21008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2746921008
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3381377856
Short name T604
Test name
Test status
Simulation time 242360521 ps
CPU time 7.97 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:27:46 PM PDT 24
Peak memory 249268 kb
Host smart-1c3987ca-ec9a-4c2b-9ca1-35bd6c1057bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
77856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3381377856
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1196902431
Short name T513
Test name
Test status
Simulation time 263494788 ps
CPU time 17.73 seconds
Started Jun 27 05:27:33 PM PDT 24
Finished Jun 27 05:27:51 PM PDT 24
Peak memory 257404 kb
Host smart-e3f7dac5-d4d4-42e6-b77d-2e521626b5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11969
02431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1196902431
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3785924651
Short name T532
Test name
Test status
Simulation time 228977877217 ps
CPU time 2081.55 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 06:02:19 PM PDT 24
Peak memory 283528 kb
Host smart-e388090d-17c9-4925-8206-2b2070d4c61b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785924651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3785924651
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2133218492
Short name T403
Test name
Test status
Simulation time 11236523000 ps
CPU time 297.33 seconds
Started Jun 27 05:27:33 PM PDT 24
Finished Jun 27 05:32:32 PM PDT 24
Peak memory 256908 kb
Host smart-193b877b-7614-4a37-b6b4-93dad3978d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21332
18492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2133218492
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3141793019
Short name T387
Test name
Test status
Simulation time 609532817 ps
CPU time 20.11 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:27:57 PM PDT 24
Peak memory 249260 kb
Host smart-168226c7-8691-424f-afff-989d491665f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417
93019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3141793019
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1018925121
Short name T317
Test name
Test status
Simulation time 402786757506 ps
CPU time 1454.91 seconds
Started Jun 27 05:27:37 PM PDT 24
Finished Jun 27 05:51:54 PM PDT 24
Peak memory 272416 kb
Host smart-955ab593-2a11-4627-b084-5d2169029817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018925121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1018925121
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3254169141
Short name T426
Test name
Test status
Simulation time 221591014812 ps
CPU time 2352.59 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 06:06:51 PM PDT 24
Peak memory 282076 kb
Host smart-fd42e2df-57fc-4c15-ae0e-675112d0389e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254169141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3254169141
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1810345711
Short name T659
Test name
Test status
Simulation time 14519389871 ps
CPU time 583.97 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:37:21 PM PDT 24
Peak memory 248240 kb
Host smart-c0709919-5ebd-4138-86d0-f665b2cf6c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810345711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1810345711
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.125340451
Short name T671
Test name
Test status
Simulation time 394476950 ps
CPU time 39.12 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:28:17 PM PDT 24
Peak memory 257280 kb
Host smart-44dfb3c0-acf5-4063-a8c7-016ca22d93ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12534
0451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.125340451
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2353485304
Short name T398
Test name
Test status
Simulation time 564467392 ps
CPU time 17.21 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:27:55 PM PDT 24
Peak memory 249004 kb
Host smart-2435e064-cf0f-4355-9e6c-e4389d4ddfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
85304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2353485304
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2351552551
Short name T487
Test name
Test status
Simulation time 1049528860 ps
CPU time 61.81 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:28:39 PM PDT 24
Peak memory 250248 kb
Host smart-01b222b7-95d6-4713-ab7c-0380641bafa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515
52551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2351552551
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1550548983
Short name T556
Test name
Test status
Simulation time 427108991 ps
CPU time 12.99 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:27:49 PM PDT 24
Peak memory 249268 kb
Host smart-55969784-9a60-41db-a1da-15b5e15d4e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505
48983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1550548983
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2609303771
Short name T112
Test name
Test status
Simulation time 23321984636 ps
CPU time 355.75 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:33:32 PM PDT 24
Peak memory 257604 kb
Host smart-704604b1-fede-4786-a9ba-910487a74e3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609303771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2609303771
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.368043244
Short name T106
Test name
Test status
Simulation time 69926483150 ps
CPU time 1220.63 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:47:57 PM PDT 24
Peak memory 288572 kb
Host smart-7829275d-248e-4a74-ae37-a7e09285b75d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368043244 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.368043244
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4122502805
Short name T541
Test name
Test status
Simulation time 38130332627 ps
CPU time 2307.88 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 06:06:05 PM PDT 24
Peak memory 289484 kb
Host smart-9b9ef072-a49b-47a1-8b70-83a350d8cce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122502805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4122502805
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1324418714
Short name T657
Test name
Test status
Simulation time 4529090550 ps
CPU time 136.52 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:29:52 PM PDT 24
Peak memory 257040 kb
Host smart-7d8efd2a-b489-47ac-a2c9-03c9b95be566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13244
18714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1324418714
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.193360817
Short name T37
Test name
Test status
Simulation time 86248922 ps
CPU time 4.26 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:27:42 PM PDT 24
Peak memory 241040 kb
Host smart-8655d047-02de-4ffa-af27-47588ab1e1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
0817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.193360817
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3549469696
Short name T613
Test name
Test status
Simulation time 141760923631 ps
CPU time 1967.88 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 06:00:25 PM PDT 24
Peak memory 273972 kb
Host smart-48b5cb6c-78c0-4ad9-9ae3-d063784b7d0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549469696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3549469696
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1630298665
Short name T425
Test name
Test status
Simulation time 36719782607 ps
CPU time 2130.3 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 06:03:05 PM PDT 24
Peak memory 273604 kb
Host smart-f0467cca-3e39-4d2f-891c-8b544e14c204
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630298665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1630298665
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2224978553
Short name T290
Test name
Test status
Simulation time 15839022089 ps
CPU time 607.95 seconds
Started Jun 27 05:27:35 PM PDT 24
Finished Jun 27 05:37:45 PM PDT 24
Peak memory 248264 kb
Host smart-cb178ff0-6c2f-49a5-8698-1ebbc785a209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224978553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2224978553
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4110349275
Short name T664
Test name
Test status
Simulation time 264536713 ps
CPU time 31.16 seconds
Started Jun 27 05:27:36 PM PDT 24
Finished Jun 27 05:28:09 PM PDT 24
Peak memory 257392 kb
Host smart-380b4f47-c622-4712-913f-6d181810eab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41103
49275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4110349275
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.870270622
Short name T368
Test name
Test status
Simulation time 828407942 ps
CPU time 55.22 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:28:30 PM PDT 24
Peak memory 257388 kb
Host smart-94640e94-f366-4552-afab-9f030a440ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87027
0622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.870270622
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3317855478
Short name T44
Test name
Test status
Simulation time 420304586 ps
CPU time 21.51 seconds
Started Jun 27 05:27:34 PM PDT 24
Finished Jun 27 05:27:57 PM PDT 24
Peak memory 248800 kb
Host smart-39abba08-6517-4c45-a2c8-e9b46083780a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
55478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3317855478
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3560873107
Short name T514
Test name
Test status
Simulation time 374429085 ps
CPU time 31.17 seconds
Started Jun 27 05:27:37 PM PDT 24
Finished Jun 27 05:28:09 PM PDT 24
Peak memory 249208 kb
Host smart-1511213a-edc4-4fc7-9425-d7322a61e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35608
73107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3560873107
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3374839167
Short name T30
Test name
Test status
Simulation time 37722470971 ps
CPU time 735.34 seconds
Started Jun 27 05:27:33 PM PDT 24
Finished Jun 27 05:39:49 PM PDT 24
Peak memory 273228 kb
Host smart-2d20f05a-0fe4-4c15-b64a-a43494ce2853
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374839167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3374839167
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3896836689
Short name T211
Test name
Test status
Simulation time 24141495 ps
CPU time 2.27 seconds
Started Jun 27 05:23:49 PM PDT 24
Finished Jun 27 05:23:54 PM PDT 24
Peak memory 249596 kb
Host smart-6eeeb36d-f672-467e-9ec0-d960961c05fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3896836689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3896836689
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3810332067
Short name T615
Test name
Test status
Simulation time 769790915 ps
CPU time 11.49 seconds
Started Jun 27 05:23:48 PM PDT 24
Finished Jun 27 05:24:03 PM PDT 24
Peak memory 249240 kb
Host smart-90e8cac7-c3bb-473e-bfdd-833da663b1f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3810332067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3810332067
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1654603535
Short name T580
Test name
Test status
Simulation time 2526333092 ps
CPU time 148.75 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:26:19 PM PDT 24
Peak memory 251328 kb
Host smart-89df7d1b-90b5-4b70-904e-45b4627319bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
03535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1654603535
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2568847411
Short name T101
Test name
Test status
Simulation time 111933692 ps
CPU time 11.46 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:24:02 PM PDT 24
Peak memory 248856 kb
Host smart-46260524-49ca-461f-b0ef-cdba9c90453b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688
47411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2568847411
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2134483327
Short name T341
Test name
Test status
Simulation time 214739514972 ps
CPU time 2816.84 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 06:10:46 PM PDT 24
Peak memory 282072 kb
Host smart-fd821694-82c9-48f8-9d58-76341a70c0fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134483327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2134483327
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2232452295
Short name T549
Test name
Test status
Simulation time 32880706043 ps
CPU time 1998.97 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:57:10 PM PDT 24
Peak memory 288384 kb
Host smart-e363e144-a729-48fe-a61f-0ebea8902135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232452295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2232452295
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1574913398
Short name T293
Test name
Test status
Simulation time 52402802423 ps
CPU time 529.55 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:32:39 PM PDT 24
Peak memory 249380 kb
Host smart-e104f1ca-a735-4e09-8829-0ebf8af76e38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574913398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1574913398
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.785186416
Short name T537
Test name
Test status
Simulation time 86859800 ps
CPU time 5.76 seconds
Started Jun 27 05:23:48 PM PDT 24
Finished Jun 27 05:23:57 PM PDT 24
Peak memory 249344 kb
Host smart-a35ee6be-d5da-407d-b8b2-c19ebfbd37ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78518
6416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.785186416
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2388846771
Short name T365
Test name
Test status
Simulation time 1786149483 ps
CPU time 55.22 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 05:24:45 PM PDT 24
Peak memory 249464 kb
Host smart-3031c8fa-0570-4c11-a2df-5452d39c11e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888
46771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2388846771
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2661823499
Short name T34
Test name
Test status
Simulation time 946934924 ps
CPU time 11.17 seconds
Started Jun 27 05:24:03 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 271308 kb
Host smart-c8a388cf-1aee-40c5-8085-86db0fd1e838
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2661823499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2661823499
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.883942790
Short name T501
Test name
Test status
Simulation time 1964536041 ps
CPU time 59.69 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 248820 kb
Host smart-dafbc08e-8f6a-44a6-8263-575ca5db35b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88394
2790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.883942790
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3636694152
Short name T315
Test name
Test status
Simulation time 1172308827 ps
CPU time 23.41 seconds
Started Jun 27 05:23:46 PM PDT 24
Finished Jun 27 05:24:13 PM PDT 24
Peak memory 249588 kb
Host smart-8234192f-a46b-4b3a-a02f-6e1ec3bb05b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
94152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3636694152
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3276052289
Short name T594
Test name
Test status
Simulation time 243150911440 ps
CPU time 3475.7 seconds
Started Jun 27 05:23:47 PM PDT 24
Finished Jun 27 06:21:46 PM PDT 24
Peak memory 306040 kb
Host smart-5f97aac3-5df6-4909-aa43-92a1f0d909e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276052289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3276052289
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1676347000
Short name T96
Test name
Test status
Simulation time 183051252482 ps
CPU time 2718.03 seconds
Started Jun 27 05:27:52 PM PDT 24
Finished Jun 27 06:13:11 PM PDT 24
Peak memory 289548 kb
Host smart-c5f8a80c-25ec-4c28-9119-72bcf053f204
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676347000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1676347000
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.176260799
Short name T233
Test name
Test status
Simulation time 6475726405 ps
CPU time 53.7 seconds
Started Jun 27 05:27:58 PM PDT 24
Finished Jun 27 05:28:53 PM PDT 24
Peak memory 256956 kb
Host smart-cc8099c1-fdd3-400d-a0b7-1d14b8c351a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
0799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.176260799
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1601312363
Short name T229
Test name
Test status
Simulation time 1382355348 ps
CPU time 69.4 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:29:06 PM PDT 24
Peak memory 249172 kb
Host smart-83bf7ccc-1b1d-404b-ba6f-dcf33113baeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
12363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1601312363
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1056520134
Short name T227
Test name
Test status
Simulation time 131433948688 ps
CPU time 1810.99 seconds
Started Jun 27 05:27:58 PM PDT 24
Finished Jun 27 05:58:10 PM PDT 24
Peak memory 273896 kb
Host smart-6ef1751f-1a2f-4d4c-92a4-203b211832f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056520134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1056520134
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1279376435
Short name T342
Test name
Test status
Simulation time 8412660255 ps
CPU time 894.12 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:42:51 PM PDT 24
Peak memory 272884 kb
Host smart-e3f44816-416e-411d-ba45-fcf40f662abf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279376435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1279376435
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.69880894
Short name T568
Test name
Test status
Simulation time 21056000233 ps
CPU time 452.59 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:35:28 PM PDT 24
Peak memory 249304 kb
Host smart-507a5854-392b-44e1-ba74-f7bfd5b5e8a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69880894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.69880894
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3001105278
Short name T383
Test name
Test status
Simulation time 547578573 ps
CPU time 25.96 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:28:24 PM PDT 24
Peak memory 256844 kb
Host smart-1b8c24fe-f81c-4c4d-b625-11dc7b6a41ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30011
05278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3001105278
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3156223032
Short name T550
Test name
Test status
Simulation time 50203928 ps
CPU time 4.17 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:27:59 PM PDT 24
Peak memory 241112 kb
Host smart-8949a29c-561d-495b-8380-133fa2bb7ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
23032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3156223032
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.820773469
Short name T262
Test name
Test status
Simulation time 3018886537 ps
CPU time 36.86 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:28:31 PM PDT 24
Peak memory 256604 kb
Host smart-60a0c273-9ea7-4ccc-ac65-ee6c60c6e36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82077
3469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.820773469
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4075235707
Short name T332
Test name
Test status
Simulation time 6449918605 ps
CPU time 56.98 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:28:52 PM PDT 24
Peak memory 256624 kb
Host smart-3c530e42-ba27-4f55-b8df-9e56d67c89e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40752
35707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4075235707
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3608677265
Short name T531
Test name
Test status
Simulation time 43264025412 ps
CPU time 2622.45 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 06:11:37 PM PDT 24
Peak memory 290396 kb
Host smart-f496103a-bebc-4e3c-a395-d809e814a48e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608677265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3608677265
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1207377200
Short name T279
Test name
Test status
Simulation time 28878547920 ps
CPU time 1782.6 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:57:38 PM PDT 24
Peak memory 273700 kb
Host smart-7c38eb36-7837-498f-91e7-8887b5e6d81f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207377200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1207377200
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3015863577
Short name T561
Test name
Test status
Simulation time 183114273 ps
CPU time 13.11 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:28:10 PM PDT 24
Peak memory 253712 kb
Host smart-2851e65a-e346-43ae-9a47-64bd263b83a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30158
63577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3015863577
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.435189291
Short name T102
Test name
Test status
Simulation time 432096511 ps
CPU time 29.31 seconds
Started Jun 27 05:27:59 PM PDT 24
Finished Jun 27 05:28:29 PM PDT 24
Peak memory 255772 kb
Host smart-23cf8c73-b4eb-4df1-83f7-c84787c5f912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43518
9291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.435189291
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1348201074
Short name T717
Test name
Test status
Simulation time 12810123214 ps
CPU time 1006.81 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:44:41 PM PDT 24
Peak memory 273976 kb
Host smart-8dd6a755-657f-4937-90c8-c7da59e64ffd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348201074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1348201074
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2865881338
Short name T469
Test name
Test status
Simulation time 8234512124 ps
CPU time 1012.21 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:44:47 PM PDT 24
Peak memory 283108 kb
Host smart-db119591-685a-4a0f-8463-061537eb7685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865881338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2865881338
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.356808547
Short name T304
Test name
Test status
Simulation time 55051523065 ps
CPU time 496.75 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:36:13 PM PDT 24
Peak memory 256004 kb
Host smart-014ab769-0e81-4174-bc4b-72951972ab42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356808547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.356808547
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3679042448
Short name T323
Test name
Test status
Simulation time 804571397 ps
CPU time 17.79 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:28:14 PM PDT 24
Peak memory 249152 kb
Host smart-83ed3985-b513-4ce1-b3f5-90edf7ce0b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36790
42448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3679042448
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.117530410
Short name T8
Test name
Test status
Simulation time 1766545703 ps
CPU time 53.6 seconds
Started Jun 27 05:27:52 PM PDT 24
Finished Jun 27 05:28:46 PM PDT 24
Peak memory 249244 kb
Host smart-13c26217-e9b6-4a47-9ae8-b1a168f6cfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
0410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.117530410
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.633989141
Short name T706
Test name
Test status
Simulation time 243808911 ps
CPU time 13.23 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:28:10 PM PDT 24
Peak memory 248464 kb
Host smart-99d49ed6-89bc-4181-8ce1-c6e3cfafba94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63398
9141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.633989141
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3822361036
Short name T56
Test name
Test status
Simulation time 609416387 ps
CPU time 44.33 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:28:42 PM PDT 24
Peak memory 257448 kb
Host smart-55f9e9d8-c1f4-4a91-8d0a-828ca9d2ebcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38223
61036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3822361036
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1503728600
Short name T520
Test name
Test status
Simulation time 51255491823 ps
CPU time 1178.69 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:47:35 PM PDT 24
Peak memory 289992 kb
Host smart-03d7deaa-218b-4544-8f45-f052d88de369
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503728600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1503728600
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4244926543
Short name T562
Test name
Test status
Simulation time 88823742848 ps
CPU time 2507.9 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 06:09:43 PM PDT 24
Peak memory 289492 kb
Host smart-4a53ed25-5ca7-4a2e-bd2d-97198aa0c480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244926543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4244926543
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4048131023
Short name T517
Test name
Test status
Simulation time 3101565039 ps
CPU time 120.69 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:29:57 PM PDT 24
Peak memory 256984 kb
Host smart-15130b15-b6e0-41dd-82bd-235a03251626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481
31023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4048131023
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.702100713
Short name T117
Test name
Test status
Simulation time 1309246174 ps
CPU time 29.63 seconds
Started Jun 27 05:27:58 PM PDT 24
Finished Jun 27 05:28:29 PM PDT 24
Peak memory 249248 kb
Host smart-1540c32c-2448-42e1-8602-638228367e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70210
0713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.702100713
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4218652862
Short name T650
Test name
Test status
Simulation time 14627569658 ps
CPU time 1352.94 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:50:48 PM PDT 24
Peak memory 290360 kb
Host smart-cd2a1d21-271d-4be0-91be-6cff1811ca5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218652862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4218652862
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4059788671
Short name T380
Test name
Test status
Simulation time 287514387741 ps
CPU time 2412.39 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 06:08:10 PM PDT 24
Peak memory 289656 kb
Host smart-a93f6e59-00fb-4911-afa7-f7e44aa436c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059788671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4059788671
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3360949127
Short name T713
Test name
Test status
Simulation time 3102193973 ps
CPU time 131.29 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:30:08 PM PDT 24
Peak memory 249200 kb
Host smart-fe4cff5a-c6d8-4591-991b-d4346d867486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360949127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3360949127
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2412876748
Short name T7
Test name
Test status
Simulation time 436470035 ps
CPU time 28.4 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:28:26 PM PDT 24
Peak memory 256720 kb
Host smart-73e691be-f9fc-4555-8f27-8a3d6ed5fc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
76748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2412876748
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.877207487
Short name T319
Test name
Test status
Simulation time 4363671564 ps
CPU time 43.64 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:28:40 PM PDT 24
Peak memory 256000 kb
Host smart-fb29a0d6-5f27-4209-9118-f06ebc881022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87720
7487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.877207487
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3873732639
Short name T43
Test name
Test status
Simulation time 211687445 ps
CPU time 21.95 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:28:20 PM PDT 24
Peak memory 256844 kb
Host smart-a93d88aa-74e7-4913-84be-504fd94f4d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38737
32639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3873732639
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3450982960
Short name T667
Test name
Test status
Simulation time 355182619 ps
CPU time 10.3 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:28:05 PM PDT 24
Peak memory 254496 kb
Host smart-fbf6b4af-6429-487f-966f-a47aef02b6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34509
82960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3450982960
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1189337367
Short name T46
Test name
Test status
Simulation time 11618650431 ps
CPU time 1247.88 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:48:43 PM PDT 24
Peak memory 282148 kb
Host smart-d88f74a1-b058-447c-be7b-74156d3f650c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189337367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1189337367
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1159989508
Short name T27
Test name
Test status
Simulation time 39852931374 ps
CPU time 655.15 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:38:52 PM PDT 24
Peak memory 267724 kb
Host smart-38f93a13-314b-4450-9870-937d81d091d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159989508 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1159989508
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1855944367
Short name T539
Test name
Test status
Simulation time 21604507267 ps
CPU time 860.82 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:42:18 PM PDT 24
Peak memory 289424 kb
Host smart-dd2cd249-ad00-4df1-b889-f37836033ff9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855944367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1855944367
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2049869674
Short name T228
Test name
Test status
Simulation time 10160310961 ps
CPU time 169.61 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:30:48 PM PDT 24
Peak memory 257556 kb
Host smart-daad46d1-3908-4506-a798-88ce33a74d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498
69674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2049869674
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3347356406
Short name T418
Test name
Test status
Simulation time 719750305 ps
CPU time 42 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:28:36 PM PDT 24
Peak memory 249248 kb
Host smart-9ab53a31-425f-440e-b77e-83c77e1f06fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
56406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3347356406
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3265744445
Short name T646
Test name
Test status
Simulation time 12576030323 ps
CPU time 1033.1 seconds
Started Jun 27 05:27:58 PM PDT 24
Finished Jun 27 05:45:12 PM PDT 24
Peak memory 284760 kb
Host smart-b059d8f2-aeeb-405d-8ae8-f704696e608b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265744445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3265744445
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.527228103
Short name T391
Test name
Test status
Simulation time 22946293367 ps
CPU time 904.1 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:42:58 PM PDT 24
Peak memory 272784 kb
Host smart-90de5d3b-3558-4026-ac4a-cb900a8bc2f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527228103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.527228103
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.777514234
Short name T298
Test name
Test status
Simulation time 12128471577 ps
CPU time 136.34 seconds
Started Jun 27 05:27:53 PM PDT 24
Finished Jun 27 05:30:11 PM PDT 24
Peak memory 256828 kb
Host smart-a59ab0f1-b155-4be4-92a0-761d75457b32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777514234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.777514234
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.931370439
Short name T366
Test name
Test status
Simulation time 2611941812 ps
CPU time 38.79 seconds
Started Jun 27 05:27:54 PM PDT 24
Finished Jun 27 05:28:35 PM PDT 24
Peak memory 256864 kb
Host smart-cf00b279-b2a1-4401-b48e-988146fd4efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93137
0439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.931370439
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2408922813
Short name T683
Test name
Test status
Simulation time 134010398 ps
CPU time 15.67 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:28:13 PM PDT 24
Peak memory 248588 kb
Host smart-ef33af61-dcc3-4084-91b5-7590d37e7f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24089
22813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2408922813
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3240925397
Short name T260
Test name
Test status
Simulation time 2754713150 ps
CPU time 49.14 seconds
Started Jun 27 05:27:55 PM PDT 24
Finished Jun 27 05:28:47 PM PDT 24
Peak memory 249468 kb
Host smart-7f8214d3-028b-4e12-b61e-b92ff5507a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
25397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3240925397
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3983968130
Short name T502
Test name
Test status
Simulation time 885211860 ps
CPU time 54.65 seconds
Started Jun 27 05:27:58 PM PDT 24
Finished Jun 27 05:28:54 PM PDT 24
Peak memory 256504 kb
Host smart-1b064482-9168-4027-a441-f3634921a0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
68130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3983968130
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3962034304
Short name T481
Test name
Test status
Simulation time 259865114 ps
CPU time 17.4 seconds
Started Jun 27 05:27:57 PM PDT 24
Finished Jun 27 05:28:16 PM PDT 24
Peak memory 248712 kb
Host smart-5da90240-e54a-4f34-b8bc-4c6e1f4c9027
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962034304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3962034304
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1436481749
Short name T31
Test name
Test status
Simulation time 6732263183 ps
CPU time 576.95 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:37:52 PM PDT 24
Peak memory 265696 kb
Host smart-3c982a1d-cdee-4ddf-a694-97aebe485715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436481749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1436481749
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3268787449
Short name T318
Test name
Test status
Simulation time 31284389552 ps
CPU time 282.36 seconds
Started Jun 27 05:28:10 PM PDT 24
Finished Jun 27 05:32:53 PM PDT 24
Peak memory 257584 kb
Host smart-ff5a1ea3-258a-44b7-a82a-d941a4269fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32687
87449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3268787449
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.899316272
Short name T25
Test name
Test status
Simulation time 296031723 ps
CPU time 35.8 seconds
Started Jun 27 05:28:12 PM PDT 24
Finished Jun 27 05:28:49 PM PDT 24
Peak memory 249272 kb
Host smart-29bc69b6-91f5-4804-85b1-96d7168df6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89931
6272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.899316272
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4088468923
Short name T432
Test name
Test status
Simulation time 46626899679 ps
CPU time 2083.28 seconds
Started Jun 27 05:28:12 PM PDT 24
Finished Jun 27 06:02:56 PM PDT 24
Peak memory 269920 kb
Host smart-b187a7c1-5f6e-44c9-ad17-daac91aaaf70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088468923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4088468923
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1698058441
Short name T305
Test name
Test status
Simulation time 147070309176 ps
CPU time 397.12 seconds
Started Jun 27 05:28:11 PM PDT 24
Finished Jun 27 05:34:49 PM PDT 24
Peak memory 249276 kb
Host smart-b4a0c358-97aa-429e-a868-3a39ce508b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698058441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1698058441
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3607403487
Short name T307
Test name
Test status
Simulation time 978046064 ps
CPU time 38.98 seconds
Started Jun 27 05:28:11 PM PDT 24
Finished Jun 27 05:28:51 PM PDT 24
Peak memory 256896 kb
Host smart-8cc53d8a-7eef-4e3a-adec-cf7a4167aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36074
03487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3607403487
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3773962292
Short name T510
Test name
Test status
Simulation time 1243901592 ps
CPU time 33.46 seconds
Started Jun 27 05:28:11 PM PDT 24
Finished Jun 27 05:28:46 PM PDT 24
Peak memory 248728 kb
Host smart-7c9fe2db-3b0a-4c47-9724-1c51dad78562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37739
62292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3773962292
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3332875214
Short name T70
Test name
Test status
Simulation time 721368593 ps
CPU time 18.71 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:28:34 PM PDT 24
Peak memory 248460 kb
Host smart-c5282310-12ea-4172-a9ec-7a1c6273df30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328
75214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3332875214
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2540027993
Short name T495
Test name
Test status
Simulation time 882865262 ps
CPU time 52.59 seconds
Started Jun 27 05:27:56 PM PDT 24
Finished Jun 27 05:28:50 PM PDT 24
Peak memory 257352 kb
Host smart-113e9a0c-c5ad-4309-9869-1582ee417e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25400
27993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2540027993
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3066689679
Short name T331
Test name
Test status
Simulation time 275949741061 ps
CPU time 1258.12 seconds
Started Jun 27 05:28:16 PM PDT 24
Finished Jun 27 05:49:15 PM PDT 24
Peak memory 290088 kb
Host smart-261cb2f9-36cd-42cd-9823-fe7cb002fc62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066689679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3066689679
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1736150663
Short name T712
Test name
Test status
Simulation time 403895467110 ps
CPU time 2668.34 seconds
Started Jun 27 05:28:12 PM PDT 24
Finished Jun 27 06:12:41 PM PDT 24
Peak memory 282076 kb
Host smart-552303be-b4c7-411a-a33b-bb5e7ebf6b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736150663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1736150663
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1879854210
Short name T393
Test name
Test status
Simulation time 506886755 ps
CPU time 4.33 seconds
Started Jun 27 05:28:16 PM PDT 24
Finished Jun 27 05:28:21 PM PDT 24
Peak memory 240616 kb
Host smart-7a363b6b-2baf-4419-b21a-cd643bbb494e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
54210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1879854210
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3380569897
Short name T662
Test name
Test status
Simulation time 5260166239 ps
CPU time 78.34 seconds
Started Jun 27 05:28:13 PM PDT 24
Finished Jun 27 05:29:33 PM PDT 24
Peak memory 249468 kb
Host smart-4f6b3695-b3fd-4520-be52-b60f80960ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
69897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3380569897
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2643299051
Short name T88
Test name
Test status
Simulation time 20153092697 ps
CPU time 1035.29 seconds
Started Jun 27 05:28:15 PM PDT 24
Finished Jun 27 05:45:32 PM PDT 24
Peak memory 272424 kb
Host smart-f36c590b-c8a0-4d91-98b9-ec2995bd9a04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643299051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2643299051
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1366235586
Short name T634
Test name
Test status
Simulation time 5786252060 ps
CPU time 236.78 seconds
Started Jun 27 05:28:16 PM PDT 24
Finished Jun 27 05:32:14 PM PDT 24
Peak memory 248188 kb
Host smart-33f8eb6a-1d67-48f3-9946-d345b0e47947
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366235586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1366235586
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1296842682
Short name T500
Test name
Test status
Simulation time 1960408124 ps
CPU time 31.86 seconds
Started Jun 27 05:28:10 PM PDT 24
Finished Jun 27 05:28:43 PM PDT 24
Peak memory 256452 kb
Host smart-5a89dc11-4214-4b8f-ad67-78fdb0aff13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968
42682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1296842682
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.490769535
Short name T592
Test name
Test status
Simulation time 174432937 ps
CPU time 15.66 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:28:32 PM PDT 24
Peak memory 249024 kb
Host smart-5a73c3ae-e382-48c6-b3af-fe9ee14c1808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49076
9535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.490769535
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.860323188
Short name T506
Test name
Test status
Simulation time 1121829609 ps
CPU time 23.28 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:28:39 PM PDT 24
Peak memory 255544 kb
Host smart-6bf90eac-7efc-4015-8220-4ee67468fd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86032
3188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.860323188
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3960523378
Short name T378
Test name
Test status
Simulation time 2364757585 ps
CPU time 31.2 seconds
Started Jun 27 05:28:16 PM PDT 24
Finished Jun 27 05:28:48 PM PDT 24
Peak memory 257416 kb
Host smart-133f7c74-d907-4cdb-bbd1-33fcb3bb227a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
23378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3960523378
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.379552521
Short name T321
Test name
Test status
Simulation time 2438041561 ps
CPU time 51.43 seconds
Started Jun 27 05:28:10 PM PDT 24
Finished Jun 27 05:29:03 PM PDT 24
Peak memory 256400 kb
Host smart-c3a8d937-aeb6-41a5-9b5f-d6ae96c156a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379552521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.379552521
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1981283824
Short name T90
Test name
Test status
Simulation time 33339229961 ps
CPU time 3838.3 seconds
Started Jun 27 05:28:11 PM PDT 24
Finished Jun 27 06:32:11 PM PDT 24
Peak memory 332924 kb
Host smart-761fb510-f969-4b0c-aaa3-7fa083f1abd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981283824 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1981283824
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.783954082
Short name T645
Test name
Test status
Simulation time 131512323274 ps
CPU time 735.12 seconds
Started Jun 27 05:28:09 PM PDT 24
Finished Jun 27 05:40:26 PM PDT 24
Peak memory 273916 kb
Host smart-5c740a44-d865-4ac1-b591-28f8e74ae48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783954082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.783954082
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.378104684
Short name T617
Test name
Test status
Simulation time 18118264045 ps
CPU time 237.93 seconds
Started Jun 27 05:28:16 PM PDT 24
Finished Jun 27 05:32:15 PM PDT 24
Peak memory 256852 kb
Host smart-7779805f-2811-43cb-9f72-abdae723476e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
4684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.378104684
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.173720977
Short name T197
Test name
Test status
Simulation time 581332000 ps
CPU time 19.56 seconds
Started Jun 27 05:28:13 PM PDT 24
Finished Jun 27 05:28:34 PM PDT 24
Peak memory 257000 kb
Host smart-b1683581-0646-489f-ac69-f7a2bd6e0044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
0977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.173720977
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.703306370
Short name T654
Test name
Test status
Simulation time 13411402078 ps
CPU time 686.97 seconds
Started Jun 27 05:28:10 PM PDT 24
Finished Jun 27 05:39:38 PM PDT 24
Peak memory 272528 kb
Host smart-6db19fc7-432c-493d-9fd5-aaa0501b0fed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703306370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.703306370
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4162755001
Short name T108
Test name
Test status
Simulation time 65294306030 ps
CPU time 1980.06 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 06:01:32 PM PDT 24
Peak memory 273980 kb
Host smart-60e9fd2e-8f40-429b-8875-00070805adaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162755001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4162755001
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.966668897
Short name T621
Test name
Test status
Simulation time 4930572223 ps
CPU time 231.77 seconds
Started Jun 27 05:28:12 PM PDT 24
Finished Jun 27 05:32:05 PM PDT 24
Peak memory 249192 kb
Host smart-49349416-e19d-4db7-bc34-6f6fd618c81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966668897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.966668897
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3020044257
Short name T544
Test name
Test status
Simulation time 444988413 ps
CPU time 22.65 seconds
Started Jun 27 05:28:12 PM PDT 24
Finished Jun 27 05:28:36 PM PDT 24
Peak memory 256656 kb
Host smart-e13b7877-a7dd-46dc-8a66-85e40995a2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
44257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3020044257
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1113294342
Short name T688
Test name
Test status
Simulation time 142561102 ps
CPU time 16.09 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:28:32 PM PDT 24
Peak memory 248744 kb
Host smart-81969663-7a60-478a-94b5-81256839a540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11132
94342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1113294342
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3228233775
Short name T467
Test name
Test status
Simulation time 341105778 ps
CPU time 11.63 seconds
Started Jun 27 05:28:14 PM PDT 24
Finished Jun 27 05:28:27 PM PDT 24
Peak memory 248500 kb
Host smart-8e45b562-36f0-49fa-b57a-075a517d80f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32282
33775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3228233775
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.724037314
Short name T504
Test name
Test status
Simulation time 378727863 ps
CPU time 14.12 seconds
Started Jun 27 05:28:15 PM PDT 24
Finished Jun 27 05:28:31 PM PDT 24
Peak memory 249220 kb
Host smart-4c506349-8cd0-4665-a16f-4cb9ec66ce61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72403
7314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.724037314
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1776992895
Short name T468
Test name
Test status
Simulation time 77221010473 ps
CPU time 1510.04 seconds
Started Jun 27 05:28:31 PM PDT 24
Finished Jun 27 05:53:43 PM PDT 24
Peak memory 289980 kb
Host smart-6eb26924-a7b4-4a71-b6cc-db6b9f97bf85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776992895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1776992895
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.575196013
Short name T231
Test name
Test status
Simulation time 178657982865 ps
CPU time 2615.25 seconds
Started Jun 27 05:28:31 PM PDT 24
Finished Jun 27 06:12:08 PM PDT 24
Peak memory 289544 kb
Host smart-9188affa-a5b9-4f90-89f2-1c2d3a01b4ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575196013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.575196013
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2598991089
Short name T494
Test name
Test status
Simulation time 1128254452 ps
CPU time 89.01 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:30:00 PM PDT 24
Peak memory 257444 kb
Host smart-b3c90f4d-2e6e-4afc-a7da-8fc77670dd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
91089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2598991089
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.427229073
Short name T600
Test name
Test status
Simulation time 124423013 ps
CPU time 7.05 seconds
Started Jun 27 05:28:29 PM PDT 24
Finished Jun 27 05:28:37 PM PDT 24
Peak memory 249180 kb
Host smart-275953f4-f9da-41e8-a639-8c077a261400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42722
9073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.427229073
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.904633387
Short name T337
Test name
Test status
Simulation time 30833341687 ps
CPU time 762.12 seconds
Started Jun 27 05:28:31 PM PDT 24
Finished Jun 27 05:41:15 PM PDT 24
Peak memory 265708 kb
Host smart-885ffdff-9d52-424a-8894-3e86df4bed8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904633387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.904633387
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3448448406
Short name T431
Test name
Test status
Simulation time 24189048543 ps
CPU time 1492.43 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:53:24 PM PDT 24
Peak memory 273912 kb
Host smart-2d5789cf-e5c3-46b8-b92d-7255cfb57ccc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448448406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3448448406
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.201289051
Short name T282
Test name
Test status
Simulation time 9113114025 ps
CPU time 362.26 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:34:34 PM PDT 24
Peak memory 249400 kb
Host smart-5277c09f-8a4e-45e2-bb2f-8413c4752829
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201289051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.201289051
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1710806820
Short name T512
Test name
Test status
Simulation time 3754663345 ps
CPU time 57.88 seconds
Started Jun 27 05:28:29 PM PDT 24
Finished Jun 27 05:29:27 PM PDT 24
Peak memory 257540 kb
Host smart-5c9bbe15-9c60-47ef-b628-e8f81637c5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17108
06820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1710806820
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1775780685
Short name T716
Test name
Test status
Simulation time 1469987312 ps
CPU time 49.94 seconds
Started Jun 27 05:28:29 PM PDT 24
Finished Jun 27 05:29:21 PM PDT 24
Peak memory 248948 kb
Host smart-37a3edcd-8431-42cc-bbf6-eae94e551670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17757
80685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1775780685
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2280193499
Short name T416
Test name
Test status
Simulation time 1553248583 ps
CPU time 51.29 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:29:23 PM PDT 24
Peak memory 248592 kb
Host smart-e07afb9c-5e88-4ac6-aa19-5fbe2ca91804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
93499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2280193499
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3362826462
Short name T376
Test name
Test status
Simulation time 597039918 ps
CPU time 34.86 seconds
Started Jun 27 05:28:29 PM PDT 24
Finished Jun 27 05:29:05 PM PDT 24
Peak memory 257424 kb
Host smart-0594f747-0232-4d01-b4f3-0a4ecf4eca6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33628
26462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3362826462
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2884649537
Short name T259
Test name
Test status
Simulation time 58782173906 ps
CPU time 3742.38 seconds
Started Jun 27 05:28:32 PM PDT 24
Finished Jun 27 06:30:56 PM PDT 24
Peak memory 306848 kb
Host smart-2842797e-e77a-4e9f-952b-6cce52b84b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884649537 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2884649537
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4194333208
Short name T87
Test name
Test status
Simulation time 127461245761 ps
CPU time 1926.87 seconds
Started Jun 27 05:28:49 PM PDT 24
Finished Jun 27 06:00:57 PM PDT 24
Peak memory 273964 kb
Host smart-25636c07-cd91-49bf-9afe-241fc8608fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194333208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4194333208
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1122247282
Short name T587
Test name
Test status
Simulation time 12372506731 ps
CPU time 172.25 seconds
Started Jun 27 05:28:31 PM PDT 24
Finished Jun 27 05:31:25 PM PDT 24
Peak memory 257564 kb
Host smart-09580f71-bce3-4472-b7d8-190e2641b238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11222
47282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1122247282
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2950351597
Short name T575
Test name
Test status
Simulation time 1458502741 ps
CPU time 26.5 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:28:58 PM PDT 24
Peak memory 257488 kb
Host smart-04597fc2-5948-420a-873a-a07e40d9e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29503
51597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2950351597
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2557537456
Short name T679
Test name
Test status
Simulation time 35710021994 ps
CPU time 1811.9 seconds
Started Jun 27 05:28:49 PM PDT 24
Finished Jun 27 05:59:02 PM PDT 24
Peak memory 289556 kb
Host smart-d84e0597-e77d-443c-9014-b1ed9d614dfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557537456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2557537456
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1487372980
Short name T221
Test name
Test status
Simulation time 47506477239 ps
CPU time 1235.95 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:49:24 PM PDT 24
Peak memory 289864 kb
Host smart-c321ca7a-46a9-4796-bec6-8b7f8ae1e9ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487372980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1487372980
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.451162196
Short name T297
Test name
Test status
Simulation time 25298692261 ps
CPU time 274.59 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:33:24 PM PDT 24
Peak memory 249336 kb
Host smart-f7b8eba0-5173-49e0-bfba-f8509f74bfc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451162196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.451162196
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2531318883
Short name T375
Test name
Test status
Simulation time 503880800 ps
CPU time 36.11 seconds
Started Jun 27 05:28:31 PM PDT 24
Finished Jun 27 05:29:09 PM PDT 24
Peak memory 256752 kb
Host smart-4512606f-e89e-4e12-8ef7-47b0fc512881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25313
18883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2531318883
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3166354881
Short name T486
Test name
Test status
Simulation time 1732097103 ps
CPU time 33.28 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:29:05 PM PDT 24
Peak memory 256568 kb
Host smart-bf82a113-7d29-4644-9b60-a306be671734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31663
54881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3166354881
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2093959920
Short name T410
Test name
Test status
Simulation time 598948584 ps
CPU time 19.04 seconds
Started Jun 27 05:28:46 PM PDT 24
Finished Jun 27 05:29:06 PM PDT 24
Peak memory 256524 kb
Host smart-5b406567-ce38-49e5-8679-13a71ed0e0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20939
59920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2093959920
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2401476537
Short name T695
Test name
Test status
Simulation time 1524354015 ps
CPU time 31.09 seconds
Started Jun 27 05:28:30 PM PDT 24
Finished Jun 27 05:29:02 PM PDT 24
Peak memory 249780 kb
Host smart-51024ad4-e46a-4f05-87bf-0f84b815f594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
76537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2401476537
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2730441360
Short name T694
Test name
Test status
Simulation time 225351729928 ps
CPU time 2895.01 seconds
Started Jun 27 05:28:50 PM PDT 24
Finished Jun 27 06:17:06 PM PDT 24
Peak memory 322912 kb
Host smart-1973175e-846f-444a-aa95-7e917e28b72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730441360 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2730441360
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3344152251
Short name T224
Test name
Test status
Simulation time 87666087588 ps
CPU time 1224.04 seconds
Started Jun 27 05:28:49 PM PDT 24
Finished Jun 27 05:49:14 PM PDT 24
Peak memory 273452 kb
Host smart-0d4f8c5a-7fdf-4f5e-a63a-a163b51031fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344152251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3344152251
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1247330698
Short name T516
Test name
Test status
Simulation time 1237114228 ps
CPU time 103.23 seconds
Started Jun 27 05:28:52 PM PDT 24
Finished Jun 27 05:30:36 PM PDT 24
Peak memory 256808 kb
Host smart-3a8f3240-4732-4b33-a540-c889196385bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
30698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1247330698
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.677733463
Short name T77
Test name
Test status
Simulation time 432782311 ps
CPU time 31.89 seconds
Started Jun 27 05:28:49 PM PDT 24
Finished Jun 27 05:29:22 PM PDT 24
Peak memory 248852 kb
Host smart-9c23e70e-6072-4b09-b6ee-b79180b6af40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67773
3463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.677733463
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.950636044
Short name T277
Test name
Test status
Simulation time 29011140939 ps
CPU time 1425.53 seconds
Started Jun 27 05:28:51 PM PDT 24
Finished Jun 27 05:52:37 PM PDT 24
Peak memory 289800 kb
Host smart-cce11a73-04bc-441c-97c9-cd6c120e92f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950636044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.950636044
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1477890375
Short name T429
Test name
Test status
Simulation time 28603704068 ps
CPU time 1646.86 seconds
Started Jun 27 05:28:50 PM PDT 24
Finished Jun 27 05:56:18 PM PDT 24
Peak memory 285020 kb
Host smart-fcfc8fd7-2fcd-4301-b37d-dd8674aa8607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477890375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1477890375
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1541428830
Short name T99
Test name
Test status
Simulation time 59639040306 ps
CPU time 316.13 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:34:05 PM PDT 24
Peak memory 249364 kb
Host smart-747619b5-566e-40e8-aec9-cec552c0c564
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541428830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1541428830
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.690957098
Short name T471
Test name
Test status
Simulation time 1829113255 ps
CPU time 36.1 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:29:26 PM PDT 24
Peak memory 256688 kb
Host smart-902b6049-b9ac-4711-a4a5-a1f5be921869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69095
7098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.690957098
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.878386813
Short name T405
Test name
Test status
Simulation time 1320819298 ps
CPU time 24.71 seconds
Started Jun 27 05:28:51 PM PDT 24
Finished Jun 27 05:29:17 PM PDT 24
Peak memory 248708 kb
Host smart-1304ebed-46de-486b-8f8c-0ab9c87a528a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87838
6813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.878386813
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2978098664
Short name T700
Test name
Test status
Simulation time 473837329 ps
CPU time 16.7 seconds
Started Jun 27 05:28:47 PM PDT 24
Finished Jun 27 05:29:04 PM PDT 24
Peak memory 256888 kb
Host smart-d2a52787-979d-4508-847f-f3197893b87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
98664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2978098664
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1567872558
Short name T68
Test name
Test status
Simulation time 647650043 ps
CPU time 17.91 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:29:06 PM PDT 24
Peak memory 256716 kb
Host smart-e2cf341d-1c57-4994-bd5d-d3d578033473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
72558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1567872558
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2149445266
Short name T545
Test name
Test status
Simulation time 50893781244 ps
CPU time 1310.47 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:50:40 PM PDT 24
Peak memory 290372 kb
Host smart-f62f16f9-9f58-486a-a8d9-308e10bf7aab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149445266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2149445266
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.396793134
Short name T86
Test name
Test status
Simulation time 57227210330 ps
CPU time 1776.37 seconds
Started Jun 27 05:28:48 PM PDT 24
Finished Jun 27 05:58:26 PM PDT 24
Peak memory 290324 kb
Host smart-3f981378-fee1-4dc5-a46d-22c8894977c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396793134 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.396793134
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.785677079
Short name T205
Test name
Test status
Simulation time 153241965 ps
CPU time 3.71 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:13 PM PDT 24
Peak memory 249580 kb
Host smart-4c74f2aa-acc4-4c4c-9f6d-b75a7cee7bbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=785677079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.785677079
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4293064602
Short name T456
Test name
Test status
Simulation time 16036640404 ps
CPU time 864.81 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:38:37 PM PDT 24
Peak memory 269784 kb
Host smart-59a65f95-1446-4b3f-bbd5-6998fc547b1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293064602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4293064602
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1810962456
Short name T640
Test name
Test status
Simulation time 12906303161 ps
CPU time 51.48 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 05:25:02 PM PDT 24
Peak memory 249432 kb
Host smart-a7ded3f8-d8fd-478b-b5da-48256395cf0a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1810962456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1810962456
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4043773703
Short name T583
Test name
Test status
Simulation time 3412831505 ps
CPU time 197.61 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:27:23 PM PDT 24
Peak memory 257608 kb
Host smart-4e2bd80a-3533-425e-9d16-bac8082f7f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40437
73703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4043773703
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1369066791
Short name T116
Test name
Test status
Simulation time 103228599 ps
CPU time 7.57 seconds
Started Jun 27 05:24:05 PM PDT 24
Finished Jun 27 05:24:14 PM PDT 24
Peak memory 251468 kb
Host smart-f67cdf3b-86c2-4ddd-a920-34d68f39c56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13690
66791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1369066791
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1343656274
Short name T616
Test name
Test status
Simulation time 170096405297 ps
CPU time 1923.82 seconds
Started Jun 27 05:24:03 PM PDT 24
Finished Jun 27 05:56:08 PM PDT 24
Peak memory 289864 kb
Host smart-b5c4615a-0e5d-4339-a8da-bab0cba3d5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343656274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1343656274
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.68543270
Short name T632
Test name
Test status
Simulation time 41341356952 ps
CPU time 2556.79 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 06:06:44 PM PDT 24
Peak memory 289724 kb
Host smart-c6cecdf2-c64c-4a5c-850e-c4217fbb104a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68543270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.68543270
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4024027356
Short name T234
Test name
Test status
Simulation time 53138858111 ps
CPU time 591.03 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:34:00 PM PDT 24
Peak memory 249188 kb
Host smart-079d38ea-7062-4b12-bdb3-b5d0fdaa3626
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024027356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4024027356
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3627936968
Short name T652
Test name
Test status
Simulation time 291020687 ps
CPU time 8.6 seconds
Started Jun 27 05:24:05 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 249268 kb
Host smart-7034ccb4-f153-4b83-9c89-910ba56792ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
36968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3627936968
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4266200924
Short name T569
Test name
Test status
Simulation time 4556577427 ps
CPU time 74.13 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 05:25:24 PM PDT 24
Peak memory 249392 kb
Host smart-7b419358-762a-4fd7-b9de-f5ef636bd3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42662
00924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4266200924
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2196151351
Short name T255
Test name
Test status
Simulation time 988807764 ps
CPU time 32.3 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:42 PM PDT 24
Peak memory 256808 kb
Host smart-c6b2c61f-1b49-46f1-bfcd-fc31f4ded195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
51351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2196151351
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.256008758
Short name T329
Test name
Test status
Simulation time 561446679 ps
CPU time 26.51 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:35 PM PDT 24
Peak memory 257304 kb
Host smart-4a8a5e71-d65c-4b71-9a5a-578bc7941a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25600
8758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.256008758
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3709045335
Short name T488
Test name
Test status
Simulation time 8626560986 ps
CPU time 872.9 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:38:42 PM PDT 24
Peak memory 273976 kb
Host smart-eec297f5-f734-4ba4-87bd-39ff446fe42a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709045335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3709045335
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2864880426
Short name T200
Test name
Test status
Simulation time 58904890865 ps
CPU time 4348.3 seconds
Started Jun 27 05:24:05 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 331392 kb
Host smart-feaf953a-6912-45d1-921e-1d79a69b5d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864880426 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2864880426
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1047491427
Short name T219
Test name
Test status
Simulation time 48515842 ps
CPU time 2.7 seconds
Started Jun 27 05:24:10 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 249600 kb
Host smart-074fd812-fc74-47b4-b771-4ce617065250
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1047491427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1047491427
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.616748351
Short name T564
Test name
Test status
Simulation time 41981864666 ps
CPU time 1234.87 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 05:44:46 PM PDT 24
Peak memory 289896 kb
Host smart-3aef010d-43cc-4106-aff1-d8380ff82a0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616748351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.616748351
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2485708142
Short name T719
Test name
Test status
Simulation time 135228999 ps
CPU time 8.74 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:21 PM PDT 24
Peak memory 249288 kb
Host smart-6e67a659-7f97-4625-a9b5-2ff54be17d33
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2485708142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2485708142
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2043083462
Short name T434
Test name
Test status
Simulation time 4512638145 ps
CPU time 131.65 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:26:17 PM PDT 24
Peak memory 257548 kb
Host smart-c0c5fc0a-ac88-4c2f-8974-d1191edb36bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20430
83462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2043083462
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4223385183
Short name T681
Test name
Test status
Simulation time 1002067716 ps
CPU time 29.78 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:24:38 PM PDT 24
Peak memory 248848 kb
Host smart-7fa26332-3aac-4b42-ae36-63ea19744333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
85183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4223385183
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3049176525
Short name T346
Test name
Test status
Simulation time 241225319028 ps
CPU time 2673.86 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 290404 kb
Host smart-37d59ab9-720b-49ef-8ce9-a37152487958
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049176525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3049176525
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1191231312
Short name T222
Test name
Test status
Simulation time 147552186433 ps
CPU time 2519.17 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 06:06:05 PM PDT 24
Peak memory 289968 kb
Host smart-d09ba058-3d01-4147-af20-71c9df67b5ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191231312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1191231312
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4026254993
Short name T288
Test name
Test status
Simulation time 9344318298 ps
CPU time 160.85 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:26:46 PM PDT 24
Peak memory 256388 kb
Host smart-608018e3-7092-47ea-9125-671f47822642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026254993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4026254993
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2800386305
Short name T39
Test name
Test status
Simulation time 122085429 ps
CPU time 8.72 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:20 PM PDT 24
Peak memory 249280 kb
Host smart-a9425ed0-f868-4bd2-9323-6b4451e22431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28003
86305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2800386305
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2257586734
Short name T20
Test name
Test status
Simulation time 597060252 ps
CPU time 37.48 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 248792 kb
Host smart-ea16cbf1-c78a-414f-be2c-8c13f00df057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
86734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2257586734
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2531867811
Short name T95
Test name
Test status
Simulation time 1303659005 ps
CPU time 19.54 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:31 PM PDT 24
Peak memory 249204 kb
Host smart-de91bd11-e4d9-434f-a210-f439a12ab7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
67811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2531867811
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2811449538
Short name T586
Test name
Test status
Simulation time 42890016 ps
CPU time 3.16 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:12 PM PDT 24
Peak memory 249412 kb
Host smart-a723ef88-11f7-4fd8-8d8a-e99bc927ca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
49538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2811449538
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2280147209
Short name T558
Test name
Test status
Simulation time 940039828 ps
CPU time 4.87 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:24:13 PM PDT 24
Peak memory 241068 kb
Host smart-16331db0-545f-4714-83bc-688ee1a39505
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280147209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2280147209
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3383795594
Short name T240
Test name
Test status
Simulation time 15638646248 ps
CPU time 1012.83 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:40:59 PM PDT 24
Peak memory 272420 kb
Host smart-62840986-fd87-4818-9e76-e0a996dd0f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383795594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3383795594
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4241440897
Short name T216
Test name
Test status
Simulation time 112567441 ps
CPU time 3.3 seconds
Started Jun 27 05:24:10 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 249520 kb
Host smart-01b982fc-5c59-41a3-b4fd-7868c197bee5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4241440897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4241440897
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.765576118
Short name T572
Test name
Test status
Simulation time 79245330879 ps
CPU time 2787.11 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 06:10:38 PM PDT 24
Peak memory 290272 kb
Host smart-69e69ffa-537a-4350-a34c-069581f10b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765576118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.765576118
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2318437566
Short name T379
Test name
Test status
Simulation time 310673158 ps
CPU time 8.42 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:20 PM PDT 24
Peak memory 249228 kb
Host smart-97930981-a7cf-4ad1-a8e1-e3ae44b88e6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2318437566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2318437566
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.363076406
Short name T36
Test name
Test status
Simulation time 2575419194 ps
CPU time 137.89 seconds
Started Jun 27 05:24:05 PM PDT 24
Finished Jun 27 05:26:25 PM PDT 24
Peak memory 257104 kb
Host smart-1b22706f-cd6a-46a7-b83c-4523993d2bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36307
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.363076406
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.868461010
Short name T409
Test name
Test status
Simulation time 179395252 ps
CPU time 5.04 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 05:24:16 PM PDT 24
Peak memory 241252 kb
Host smart-3c51cfbc-ed06-488a-93fa-715d429326ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86846
1010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.868461010
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4141904285
Short name T459
Test name
Test status
Simulation time 60013730360 ps
CPU time 1176.88 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:43:44 PM PDT 24
Peak memory 289396 kb
Host smart-8c6a40d8-6add-4614-aa08-8817cb46f8f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141904285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4141904285
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2883186513
Short name T563
Test name
Test status
Simulation time 108264957730 ps
CPU time 1342.15 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:46:34 PM PDT 24
Peak memory 271824 kb
Host smart-48524613-4d73-4ce6-88f7-c6a4d6900a3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883186513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2883186513
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3671783314
Short name T311
Test name
Test status
Simulation time 2862280350 ps
CPU time 63.43 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:25:09 PM PDT 24
Peak memory 257788 kb
Host smart-573e73bf-fb05-4d4e-9d32-3b7dd8614dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
83314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3671783314
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3736828272
Short name T312
Test name
Test status
Simulation time 268571237 ps
CPU time 26.26 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:24:33 PM PDT 24
Peak memory 256408 kb
Host smart-647cba9f-fc30-4df0-bf30-6b63c837ad78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
28272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3736828272
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1785357459
Short name T710
Test name
Test status
Simulation time 1382399478 ps
CPU time 27.42 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:37 PM PDT 24
Peak memory 256388 kb
Host smart-d1f444fe-6a82-4977-bb08-48cd1d4c0114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
57459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1785357459
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2261334622
Short name T23
Test name
Test status
Simulation time 521479041 ps
CPU time 36.64 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:24:41 PM PDT 24
Peak memory 257332 kb
Host smart-8dc119d2-de76-4758-9882-c1fa34eef7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22613
34622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2261334622
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2443970690
Short name T463
Test name
Test status
Simulation time 65976612 ps
CPU time 3.86 seconds
Started Jun 27 05:24:10 PM PDT 24
Finished Jun 27 05:24:16 PM PDT 24
Peak memory 240988 kb
Host smart-35b4ccc2-5468-4f2d-a776-7a5b69ca80e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443970690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2443970690
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.924088781
Short name T28
Test name
Test status
Simulation time 99792948644 ps
CPU time 2458.16 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 06:05:06 PM PDT 24
Peak memory 305216 kb
Host smart-39b8c7a9-9a4f-4372-b893-948534ed2d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924088781 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.924088781
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3527193045
Short name T217
Test name
Test status
Simulation time 17929894 ps
CPU time 2.68 seconds
Started Jun 27 05:24:08 PM PDT 24
Finished Jun 27 05:24:14 PM PDT 24
Peak memory 249516 kb
Host smart-558da1a1-25af-4ab1-80f9-c12756d171a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3527193045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3527193045
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.410093018
Short name T533
Test name
Test status
Simulation time 43665211391 ps
CPU time 950.67 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:39:58 PM PDT 24
Peak memory 289644 kb
Host smart-be07c942-e1d9-460d-aa95-660325791f48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410093018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.410093018
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.44308881
Short name T622
Test name
Test status
Simulation time 2638560652 ps
CPU time 42.53 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:54 PM PDT 24
Peak memory 249296 kb
Host smart-876ca093-9e9f-4bb4-a932-0bcb74e62673
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=44308881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.44308881
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2160974665
Short name T715
Test name
Test status
Simulation time 10845954968 ps
CPU time 152.82 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:26:42 PM PDT 24
Peak memory 251356 kb
Host smart-838a9230-3125-4fa3-9c93-e11b24fa814d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
74665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2160974665
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2163418462
Short name T465
Test name
Test status
Simulation time 815726861 ps
CPU time 41.71 seconds
Started Jun 27 05:24:06 PM PDT 24
Finished Jun 27 05:24:50 PM PDT 24
Peak memory 249808 kb
Host smart-637a13f9-47de-4354-9a91-94983fd51201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21634
18462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2163418462
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1404436041
Short name T340
Test name
Test status
Simulation time 397682842030 ps
CPU time 2085.64 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:58:56 PM PDT 24
Peak memory 286836 kb
Host smart-dc443517-2033-46d2-b414-ec4618bae8ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404436041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1404436041
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.418415318
Short name T114
Test name
Test status
Simulation time 33617278606 ps
CPU time 1002.44 seconds
Started Jun 27 05:24:11 PM PDT 24
Finished Jun 27 05:40:55 PM PDT 24
Peak memory 286380 kb
Host smart-a5928e4e-e5fa-4aec-9151-8b850ef08510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418415318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.418415318
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1645015928
Short name T281
Test name
Test status
Simulation time 15567653973 ps
CPU time 174.34 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:27:04 PM PDT 24
Peak memory 249348 kb
Host smart-83ad77de-9fc3-416d-a3d5-7366538e2989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645015928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1645015928
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1866122658
Short name T553
Test name
Test status
Simulation time 133558695 ps
CPU time 12.52 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:21 PM PDT 24
Peak memory 257312 kb
Host smart-9e26afb3-69e5-40c7-ba18-329362697dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
22658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1866122658
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.792558293
Short name T21
Test name
Test status
Simulation time 1559286559 ps
CPU time 17.98 seconds
Started Jun 27 05:24:07 PM PDT 24
Finished Jun 27 05:24:27 PM PDT 24
Peak memory 249284 kb
Host smart-68f89f6f-02e2-45b1-9680-93999f21efeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79255
8293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.792558293
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.833053079
Short name T50
Test name
Test status
Simulation time 121816993 ps
CPU time 7.8 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:19 PM PDT 24
Peak memory 249244 kb
Host smart-31f51887-0f89-401d-b90c-b6f19e8ad894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83305
3079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.833053079
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2729273893
Short name T552
Test name
Test status
Simulation time 486429627 ps
CPU time 21.13 seconds
Started Jun 27 05:24:04 PM PDT 24
Finished Jun 27 05:24:26 PM PDT 24
Peak memory 257252 kb
Host smart-ec7b24cb-f692-45b1-ba31-74271659f61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
73893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2729273893
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1281264163
Short name T218
Test name
Test status
Simulation time 19439178 ps
CPU time 2.78 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:24:30 PM PDT 24
Peak memory 249588 kb
Host smart-e2e4dcbf-28c0-406e-8225-dce4e74c5793
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1281264163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1281264163
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3837356624
Short name T430
Test name
Test status
Simulation time 19293595015 ps
CPU time 1242.26 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:45:07 PM PDT 24
Peak memory 273992 kb
Host smart-9099d973-26b0-48e2-868d-f0a3826b94d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837356624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3837356624
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.505698143
Short name T62
Test name
Test status
Simulation time 325880581 ps
CPU time 9.05 seconds
Started Jun 27 05:24:27 PM PDT 24
Finished Jun 27 05:24:37 PM PDT 24
Peak memory 249304 kb
Host smart-4da084d4-3115-4d76-abc1-9b474586c62f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=505698143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.505698143
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3279388798
Short name T316
Test name
Test status
Simulation time 17381390850 ps
CPU time 292.55 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:29:20 PM PDT 24
Peak memory 257420 kb
Host smart-21c5754e-6960-4df4-9c08-77897b5a105f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
88798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3279388798
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.797628289
Short name T76
Test name
Test status
Simulation time 2413360163 ps
CPU time 38.98 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:25:02 PM PDT 24
Peak memory 249340 kb
Host smart-ab11dfdc-ce30-486f-a4fc-c343299e4ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79762
8289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.797628289
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.972377947
Short name T232
Test name
Test status
Simulation time 436089777497 ps
CPU time 1933.07 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:56:37 PM PDT 24
Peak memory 282656 kb
Host smart-bbac46cd-8a09-4461-a620-c9ed00ae92df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972377947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.972377947
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1540483343
Short name T470
Test name
Test status
Simulation time 33905360873 ps
CPU time 2259.83 seconds
Started Jun 27 05:24:29 PM PDT 24
Finished Jun 27 06:02:10 PM PDT 24
Peak memory 289660 kb
Host smart-c8d990d6-08c0-486e-b6f5-e26fc6061259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540483343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1540483343
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1508091166
Short name T547
Test name
Test status
Simulation time 5125897093 ps
CPU time 215.35 seconds
Started Jun 27 05:24:26 PM PDT 24
Finished Jun 27 05:28:03 PM PDT 24
Peak memory 249372 kb
Host smart-a9055961-5cda-4448-b34b-d3878bdd386b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508091166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1508091166
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1532570880
Short name T546
Test name
Test status
Simulation time 1212675459 ps
CPU time 19.08 seconds
Started Jun 27 05:24:09 PM PDT 24
Finished Jun 27 05:24:31 PM PDT 24
Peak memory 249240 kb
Host smart-f9ffc77f-1da1-4646-a7df-2e9f69650a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
70880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1532570880
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2869173236
Short name T689
Test name
Test status
Simulation time 230504419 ps
CPU time 24.76 seconds
Started Jun 27 05:24:21 PM PDT 24
Finished Jun 27 05:24:47 PM PDT 24
Peak memory 249216 kb
Host smart-67fd52fe-e5a3-47ba-8ea0-f04283db965c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28691
73236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2869173236
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.4071725039
Short name T324
Test name
Test status
Simulation time 618411992 ps
CPU time 30.79 seconds
Started Jun 27 05:24:23 PM PDT 24
Finished Jun 27 05:24:54 PM PDT 24
Peak memory 256196 kb
Host smart-476ffc00-6174-4388-8c33-7f9bda1540ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40717
25039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4071725039
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2865792081
Short name T601
Test name
Test status
Simulation time 478080739 ps
CPU time 11.33 seconds
Started Jun 27 05:24:10 PM PDT 24
Finished Jun 27 05:24:24 PM PDT 24
Peak memory 256828 kb
Host smart-9d95b29f-a56c-4883-921a-2ad2736c8ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28657
92081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2865792081
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.573633781
Short name T241
Test name
Test status
Simulation time 21452514725 ps
CPU time 477.06 seconds
Started Jun 27 05:24:28 PM PDT 24
Finished Jun 27 05:32:26 PM PDT 24
Peak memory 274084 kb
Host smart-3cab492e-c0e4-4946-b7ca-345ed928dc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573633781 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.573633781
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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