Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	79075	1			T2	4		T9	5140		T34	1495
class_i[0x1]	49595	1			T1	541		T7	9		T8	13
class_i[0x2]	88765	1			T1	655		T14	3300		T29	5
class_i[0x3]	65411	1			T14	13		T28	4106		T29	6

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68845	1			T1	474		T8	4		T9	1313
alert[0x1]	69706	1			T1	690		T2	3		T7	8
alert[0x2]	72550	1			T1	14		T2	1		T7	1
alert[0x3]	71745	1			T1	18		T8	4		T9	1256

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

282551

1

T1

1196

T2

4

T7

9

esc_ping_fail

295

1

T8

11

T103

3

T188

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68774	1			T1	474		T8	2		T9	1313
esc_integrity_fail	alert[0x1]	69625	1			T1	690		T2	3		T7	8
esc_integrity_fail	alert[0x2]	72477	1			T1	14		T2	1		T7	1
esc_integrity_fail	alert[0x3]	71675	1			T1	18		T9	1256		T34	837
esc_ping_fail	alert[0x0]	71	1			T8	2		T188	1		T294	3
esc_ping_fail	alert[0x1]	81	1			T8	3		T103	2		T188	2
esc_ping_fail	alert[0x2]	73	1			T8	2		T188	2		T294	2
esc_ping_fail	alert[0x3]	70	1			T8	4		T103	1		T188	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	79006	1			T2	4		T9	5140		T34	1495
esc_integrity_fail	class_i[0x1]	49550	1			T1	541		T7	9		T8	2
esc_integrity_fail	class_i[0x2]	88680	1			T1	655		T14	3300		T29	5
esc_integrity_fail	class_i[0x3]	65315	1			T14	13		T28	4106		T29	6
esc_ping_fail	class_i[0x0]	69	1			T188	7		T295	3		T81	1
esc_ping_fail	class_i[0x1]	45	1			T8	11		T295	2		T213	2
esc_ping_fail	class_i[0x2]	85	1			T103	3		T294	10		T295	3
esc_ping_fail	class_i[0x3]	96	1			T294	1		T295	1		T307	4