Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	649666724	0	0	620
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	649666724	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	649666724	649485939	0	0
tb.dut.CheckAccuCntDw	0	0	620	620	0	0
tb.dut.CheckEscCntDw	0	0	620	620	0	0
tb.dut.CheckNAlerts	0	0	620	620	0	0
tb.dut.CheckNClasses	0	0	620	620	0	0
tb.dut.CheckNEscSev	0	0	620	620	0	0
tb.dut.CrashdumpKnownO_A	0	0	649666724	649485939	0	0
tb.dut.EdnKnownO_A	0	0	649666724	649485939	0	0
tb.dut.EscPKnownO_A	0	0	649666724	649485939	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	649666724	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	649666724	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	649666724	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	649666724	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	649666724	90	0	0
tb.dut.IrqAKnownO_A	0	0	649666724	649485939	0	0
tb.dut.IrqBKnownO_A	0	0	649666724	649485939	0	0
tb.dut.IrqCKnownO_A	0	0	649666724	649485939	0	0
tb.dut.IrqDKnownO_A	0	0	649666724	649485939	0	0
tb.dut.TlAReadyKnownO_A	0	0	649666724	649485939	0	0
tb.dut.TlDValidKnownO_A	0	0	649666724	649485939	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	674278252	2718720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	674278252	10247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	674278252	10184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	674278252	10518	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	674278252	10229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	674278252	10132	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	674278252	10097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	674278252	10248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	674278252	10365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	674278252	10234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	674278252	10163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	674278252	10145	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	674278252	9934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	674278252	10648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	674278252	10124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	674278252	10039	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	674278252	10062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	674278252	9858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	674278252	10256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	674278252	10128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	674278252	10290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	674278252	10307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	674278252	10054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	674278252	10275	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	674278252	10161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	674278252	9943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	674278252	10157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	674278252	10321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	674278252	10198	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	674278252	10134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	674278252	10266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	674278252	10381	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	674278252	9999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	674278252	10115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	674278252	10080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	674278252	10097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	674278252	10018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	674278252	10160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	674278252	10003	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	674278252	10361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	674278252	9960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	674278252	10368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	674278252	10236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	674278252	10382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	674278252	10052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	674278252	9923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	674278252	10369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	674278252	10426	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	674278252	10007	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	674278252	9907	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	674278252	10293	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	674278252	10148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	674278252	10149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	674278252	10004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	674278252	10229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	674278252	10324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	674278252	9861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	674278252	10209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	674278252	10194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	674278252	9988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	674278252	9937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	674278252	10266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	674278252	10306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	674278252	10081	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	674278252	10399	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	674278252	10187	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	674278252	10039	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	674278252	10247	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	674278252	10373	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	674278252	10163	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	674278252	16397	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	674278252	10301	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	674278252	10071	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	674278252	10064	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	674278252	10382	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	674278252	10441	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	674278252	10016	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	674278252	10036	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	674278252	10128	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	649666724	2461	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	649666724	224285	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	649666724	327382018	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	649666724	330	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	649666724	765	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	649666724	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	649666724	385	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	649450110	256099304	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	649666724	849	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	649666724	836	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	649666724	814	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	649666724	801	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	649666724	1470	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	649666724	149542	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	649666724	1362	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	649666724	63	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	649666724	1590	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	649666724	1320	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	649448350	649382636	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	649666724	649485939	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	649666724	2249	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	649666724	160504	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	649666724	352054918	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	649666724	310	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	649666724	480	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	649666724	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	649666724	236	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	649450110	259159813	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	649666724	576	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	649666724	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	649666724	555	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	649666724	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	649666724	2313	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	649666724	220279	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	649666724	2205	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	649666724	84	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	649666724	1630	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	649666724	1360	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	649448350	649382636	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	649666724	649485939	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	649666724	1954	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	649666724	216535	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	649666724	331293445	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	649666724	296	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	649666724	497	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	649666724	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	649666724	237	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	649450110	265605376	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	649666724	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	649666724	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	649666724	529	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	649666724	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	649666724	700	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	649666724	76911	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	649666724	642	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	649666724	40	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	649666724	1551	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	649666724	1281	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	649448350	649382636	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	649666724	649485939	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	649666724	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	649666724	5714	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	649666724	184152	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	649666724	341117705	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	649666724	357	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	649666724	503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	649666724	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	649666724	245	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	649450110	258613825	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	649666724	587	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	649666724	582	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	649666724	565	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	649666724	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	649666724	1616	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	649666724	163774	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	649666724	1522	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	649666724	72	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	649666724	1605	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	649666724	1335	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	649448350	649382636	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	649666724	649485939	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	674278252	125134980	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	674278252	673588995	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	674278252	673588995	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	674278252	173374394	0	0
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