Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	63	1			T1	1		T5	1		T19	1
class_index[0x1]	84	1			T34	2		T14	4		T31	1
class_index[0x2]	40	1			T3	1		T34	2		T20	3
class_index[0x3]	72	1			T1	6		T2	1		T36	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	117	1			T1	6		T3	1		T5	1
intr_timeout_cnt[1]	57	1			T19	1		T64	1		T20	1
intr_timeout_cnt[2]	24	1			T1	1		T20	1		T248	1
intr_timeout_cnt[3]	18	1			T22	1		T61	1		T67	1
intr_timeout_cnt[4]	5	1			T88	1		T249	1		T250	1
intr_timeout_cnt[5]	12	1			T2	1		T20	2		T223	1
intr_timeout_cnt[6]	7	1			T63	1		T251	1		T252	1
intr_timeout_cnt[7]	7	1			T161	1		T47	1		T93	3
intr_timeout_cnt[8]	7	1			T22	1		T63	2		T161	1
intr_timeout_cnt[9]	5	1			T61	2		T253	1		T254	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	18	1			T5	1		T67	1		T70	1
class_index[0x0]	intr_timeout_cnt[1]	18	1			T19	1		T64	1		T65	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T1	1		T161	1		T47	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T69	1		T79	1		T253	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T88	1		T255	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T223	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T252	1		T256	1		T257	2
class_index[0x0]	intr_timeout_cnt[7]	2	1			T161	1		T47	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T63	1		T258	1		T259	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T254	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	46	1			T34	2		T14	4		T31	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T66	1		T161	2		T99	1
class_index[0x1]	intr_timeout_cnt[2]	10	1			T79	1		T260	1		T261	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T22	1		T61	1		T262	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T250	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T63	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T93	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T22	1		T257	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T253	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T3	1		T34	2		T41	1
class_index[0x2]	intr_timeout_cnt[1]	5	1			T20	1		T263	1		T264	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T20	1		T92	1		T265	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T258	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	1	1			T249	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	5	1			T20	1		T254	1		T257	3
class_index[0x2]	intr_timeout_cnt[6]	1	1			T263	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T93	1		T260	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	32	1			T1	6		T36	1		T14	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T65	1		T243	1		T266	1
class_index[0x3]	intr_timeout_cnt[2]	2	1			T248	1		T267	1		-	-
class_index[0x3]	intr_timeout_cnt[3]	6	1			T67	1		T244	1		T99	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T259	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	6	1			T2	1		T20	1		T268	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T93	1		T260	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T63	1		T161	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T61	2		T269	1		-	-