Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343033	1			T1	18		T2	8		T3	19
all_values[1]	343033	1			T1	18		T2	8		T3	19
all_values[2]	343033	1			T1	18		T2	8		T3	19
all_values[3]	343033	1			T1	18		T2	8		T3	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682150

1

T1

32

T2

14

T3

40

auto[1]

689982

1

T1

40

T2

18

T3

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814631

1

T1

9

T2

5

T3

40

auto[1]

557501

1

T1

63

T2

27

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98280	1			T1	1		T3	7		T4	10
all_values[0]	auto[0]	auto[1]	72440	1			T1	5		T2	5		T3	6
all_values[0]	auto[1]	auto[0]	99516	1			T1	4		T2	1		T3	3
all_values[0]	auto[1]	auto[1]	72797	1			T1	8		T2	2		T3	3
all_values[1]	auto[0]	auto[0]	100997	1			T3	5		T4	6		T5	1
all_values[1]	auto[0]	auto[1]	69414	1			T1	10		T2	3		T3	4
all_values[1]	auto[1]	auto[0]	102964	1			T1	1		T2	1		T3	5
all_values[1]	auto[1]	auto[1]	69658	1			T1	7		T2	4		T3	5
all_values[2]	auto[0]	auto[0]	102093	1			T1	1		T3	6		T4	17
all_values[2]	auto[0]	auto[1]	68080	1			T1	7		T2	3		T3	6
all_values[2]	auto[1]	auto[0]	104560	1			T1	1		T2	2		T3	4
all_values[2]	auto[1]	auto[1]	68300	1			T1	9		T2	3		T3	3
all_values[3]	auto[0]	auto[0]	102558	1			T2	1		T3	3		T4	11
all_values[3]	auto[0]	auto[1]	68288	1			T1	8		T2	2		T3	3
all_values[3]	auto[1]	auto[0]	103663	1			T1	1		T3	7		T4	12
all_values[3]	auto[1]	auto[1]	68524	1			T1	9		T2	5		T3	6