Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343033	1			T1	18		T2	8		T3	19
all_pins[1]	343033	1			T1	18		T2	8		T3	19
all_pins[2]	343033	1			T1	18		T2	8		T3	19
all_pins[3]	343033	1			T1	18		T2	8		T3	19

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1092853	1			T1	39		T2	18		T3	59
values[0x1]	279279	1			T1	33		T2	14		T3	17
transitions[0x0=>0x1]	184940	1			T1	21		T2	6		T3	12
transitions[0x1=>0x0]	185212	1			T1	21		T2	6		T3	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270236	1			T1	10		T2	6		T3	16
all_pins[0]	values[0x1]	72797	1			T1	8		T2	2		T3	3
all_pins[0]	transitions[0x0=>0x1]	72124	1			T1	6		T3	2		T5	1
all_pins[0]	transitions[0x1=>0x0]	68123	1			T1	7		T2	3		T3	6
all_pins[1]	values[0x0]	273375	1			T1	11		T2	4		T3	14
all_pins[1]	values[0x1]	69658	1			T1	7		T2	4		T3	5
all_pins[1]	transitions[0x0=>0x1]	38073	1			T1	5		T2	3		T3	4
all_pins[1]	transitions[0x1=>0x0]	41212	1			T1	6		T2	1		T3	2
all_pins[2]	values[0x0]	274733	1			T1	9		T2	5		T3	16
all_pins[2]	values[0x1]	68300	1			T1	9		T2	3		T3	3
all_pins[2]	transitions[0x0=>0x1]	37280	1			T1	6		T3	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	38638	1			T1	4		T2	1		T3	4
all_pins[3]	values[0x0]	274509	1			T1	9		T2	3		T3	13
all_pins[3]	values[0x1]	68524	1			T1	9		T2	5		T3	6
all_pins[3]	transitions[0x0=>0x1]	37463	1			T1	4		T2	3		T3	4
all_pins[3]	transitions[0x1=>0x0]	37239	1			T1	4		T2	1		T3	1