Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T142	4		T143	7		T144	7
all_values[1]	290	1			T142	4		T143	7		T144	7
all_values[2]	290	1			T142	4		T143	7		T144	7
all_values[3]	290	1			T142	4		T143	7		T144	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T142

5

T143

14

T144

22

auto[1]

487

1

T142

11

T143

14

T144

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

492

1

T142

10

T143

14

T144

10

auto[1]

668

1

T142

6

T143

14

T144

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

715

1

T142

10

T143

20

T144

19

auto[1]

445

1

T142

6

T143

8

T144

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

72

1

T142

1

T237

5

T339

1

all_values[0]

auto[0]

auto[0]

auto[1]

33

1

T143

1

T144

2

T339

2

all_values[0]

auto[0]

auto[1]

auto[0]

48

1

T142

2

T143

1

T144

1

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T143

2

T340

3

T341

1

all_values[0]

auto[1]

auto[0]

auto[1]

56

1

T143

1

T144

3

T339

1

all_values[0]

auto[1]

auto[1]

auto[1]

56

1

T142

1

T143

2

T144

1

all_values[1]

auto[0]

auto[0]

auto[0]

73

1

T142

1

T143

5

T144

2

all_values[1]

auto[0]

auto[0]

auto[1]

29

1

T339

1

T342

1

T343

1

all_values[1]

auto[0]

auto[1]

auto[0]

56

1

T142

3

T143

1

T144

1

all_values[1]

auto[0]

auto[1]

auto[1]

17

1

T144

2

T344

1

T345

2

all_values[1]

auto[1]

auto[0]

auto[1]

69

1

T144

2

T339

1

T342

4

all_values[1]

auto[1]

auto[1]

auto[1]

46

1

T143

1

T237

1

T343

4

all_values[2]

auto[0]

auto[0]

auto[0]

73

1

T143

2

T144

2

T237

1

all_values[2]

auto[0]

auto[0]

auto[1]

41

1

T144

3

T237

1

T342

1

all_values[2]

auto[0]

auto[1]

auto[0]

48

1

T142

2

T339

1

T342

2

all_values[2]

auto[0]

auto[1]

auto[1]

19

1

T143

2

T237

1

T342

1

all_values[2]

auto[1]

auto[0]

auto[1]

70

1

T142

1

T143

1

T144

2

all_values[2]

auto[1]

auto[1]

auto[1]

39

1

T142

1

T143

2

T237

3

all_values[3]

auto[0]

auto[0]

auto[0]

66

1

T143

3

T144

3

T237

2

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T143

1

T144

2

T339

1

all_values[3]

auto[0]

auto[1]

auto[0]

56

1

T142

1

T143

2

T144

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T344

1

T346

2

T340

1

all_values[3]

auto[1]

auto[0]

auto[1]

63

1

T142

2

T144

1

T237

2

all_values[3]

auto[1]

auto[1]

auto[1]

46

1

T142

1

T143

1

T237

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal