Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	97094	1			T7	633		T9	1510		T14	841
accum_cnt_1000	229615	1			T1	1		T6	1534		T7	1220
accum_cnt_100	23524	1			T6	219		T7	62		T9	89
accum_cnt_50	61126	1			T1	6		T3	20		T6	193
accum_cnt_10	184511	1			T1	48		T2	33		T3	48
accum_cnt_0	367635	1			T1	57		T2	11		T3	4

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	253224	1			T1	28		T2	11		T3	18
class_index[0x1]	253224	1			T1	28		T2	11		T3	18
class_index[0x2]	253224	1			T1	28		T2	11		T3	18
class_index[0x3]	253224	1			T1	28		T2	11		T3	18

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26413	1			T7	152		T14	131		T22	185
class_index[0x0]	accum_cnt_1000	55719	1			T7	147		T10	9		T34	2
class_index[0x0]	accum_cnt_100	5920	1			T7	6		T10	16		T14	1
class_index[0x0]	accum_cnt_50	17946	1			T1	6		T7	11		T10	11
class_index[0x0]	accum_cnt_10	46740	1			T1	21		T2	11		T3	16
class_index[0x0]	accum_cnt_0	87565	1			T1	1		T3	2		T4	16
class_index[0x1]	accum_cnt_2000	22029	1			T9	564		T14	466		T35	559
class_index[0x1]	accum_cnt_1000	63798	1			T6	655		T9	516		T10	10
class_index[0x1]	accum_cnt_100	6683	1			T6	162		T9	34		T10	16
class_index[0x1]	accum_cnt_50	17317	1			T3	8		T6	154		T9	25
class_index[0x1]	accum_cnt_10	50164	1			T2	11		T3	8		T5	2
class_index[0x1]	accum_cnt_0	85076	1			T1	28		T3	2		T4	16
class_index[0x2]	accum_cnt_2000	23682	1			T7	335		T9	467		T14	244
class_index[0x2]	accum_cnt_1000	56037	1			T1	1		T6	879		T7	449
class_index[0x2]	accum_cnt_100	5654	1			T6	57		T7	23		T9	29
class_index[0x2]	accum_cnt_50	8131	1			T3	12		T6	39		T7	30
class_index[0x2]	accum_cnt_10	47387	1			T3	6		T5	2		T6	21
class_index[0x2]	accum_cnt_0	95747	1			T1	27		T2	11		T4	16
class_index[0x3]	accum_cnt_2000	24970	1			T7	146		T9	479		T28	285
class_index[0x3]	accum_cnt_1000	54061	1			T7	624		T9	447		T28	250
class_index[0x3]	accum_cnt_100	5267	1			T7	33		T9	26		T28	22
class_index[0x3]	accum_cnt_50	17732	1			T7	34		T9	9		T14	46
class_index[0x3]	accum_cnt_10	40220	1			T1	27		T2	11		T3	18
class_index[0x3]	accum_cnt_0	99247	1			T1	1		T4	16		T5	4