Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	18637	1			T14	807		T28	473		T29	52
alert[0x1]	4894	1			T7	21		T29	70		T22	646
alert[0x2]	10048	1			T18	15		T22	2		T59	1
alert[0x3]	6496	1			T18	260		T22	98		T188	1
alert[0x4]	5851	1			T14	322		T18	48		T65	141
alert[0x5]	2258	1			T7	94		T9	3		T18	5
alert[0x6]	12183	1			T7	432		T9	3		T14	142
alert[0x7]	5048	1			T8	1		T29	135		T293	1
alert[0x8]	5465	1			T8	1		T28	265		T29	173
alert[0x9]	1774	1			T7	50		T8	2		T14	10
alert[0xa]	2799	1			T29	35		T18	36		T294	1
alert[0xb]	5709	1			T8	1		T14	36		T28	227
alert[0xc]	7129	1			T9	5		T22	1135		T38	1
alert[0xd]	3355	1			T18	3		T22	7		T38	1
alert[0xe]	4017	1			T9	20		T14	25		T42	1292
alert[0xf]	5651	1			T7	20		T29	2401		T18	154
alert[0x10]	1416	1			T7	176		T14	23		T29	18
alert[0x11]	6228	1			T7	113		T14	71		T29	35
alert[0x12]	12989	1			T9	1		T18	81		T22	1
alert[0x13]	7354	1			T7	16		T8	1		T14	15
alert[0x14]	1980	1			T14	249		T29	5		T18	4
alert[0x15]	14447	1			T8	2		T14	28		T29	189
alert[0x16]	3219	1			T8	1		T28	129		T22	159
alert[0x17]	7741	1			T14	160		T28	496		T18	57
alert[0x18]	7629	1			T7	92		T14	58		T28	106
alert[0x19]	3700	1			T22	28		T20	9		T295	1
alert[0x1a]	8463	1			T1	1		T7	852		T29	525
alert[0x1b]	5655	1			T29	869		T18	52		T103	1
alert[0x1c]	14050	1			T14	22		T18	139		T22	260
alert[0x1d]	4174	1			T9	1		T28	291		T68	4
alert[0x1e]	9803	1			T7	177		T14	166		T29	11
alert[0x1f]	6948	1			T7	60		T8	2		T294	1
alert[0x20]	1983	1			T14	5		T59	1		T188	2
alert[0x21]	2992	1			T28	8		T38	1		T59	1
alert[0x22]	3675	1			T7	91		T33	1		T38	9
alert[0x23]	6078	1			T7	70		T14	28		T18	283
alert[0x24]	2222	1			T7	20		T22	78		T43	50
alert[0x25]	4313	1			T7	87		T29	139		T22	147
alert[0x26]	6332	1			T28	42		T29	2		T18	42
alert[0x27]	2956	1			T7	71		T8	2		T18	18
alert[0x28]	6034	1			T27	2		T294	1		T296	2
alert[0x29]	6849	1			T7	1438		T8	1		T14	3
alert[0x2a]	9753	1			T7	348		T14	1		T38	1
alert[0x2b]	9954	1			T9	1		T14	117		T28	340
alert[0x2c]	4411	1			T7	113		T14	319		T28	747
alert[0x2d]	7080	1			T7	25		T29	243		T22	17
alert[0x2e]	15616	1			T7	13		T8	1		T14	4986
alert[0x2f]	4890	1			T7	958		T14	19		T29	150
alert[0x30]	12312	1			T14	87		T29	878		T18	40
alert[0x31]	17245	1			T2	2		T7	141		T8	2
alert[0x32]	7975	1			T7	44		T9	4		T14	32
alert[0x33]	5698	1			T7	12		T14	211		T28	335
alert[0x34]	3129	1			T18	17		T22	34		T61	4
alert[0x35]	3514	1			T7	287		T34	2		T28	209
alert[0x36]	5788	1			T7	28		T28	96		T29	193
alert[0x37]	1827	1			T1	1		T14	13		T20	24
alert[0x38]	4555	1			T14	755		T28	31		T29	77
alert[0x39]	3539	1			T2	7		T8	1		T18	1
alert[0x3a]	10906	1			T7	272		T18	19		T38	32
alert[0x3b]	1611	1			T294	1		T224	9		T274	141
alert[0x3c]	4169	1			T7	399		T9	1		T28	210
alert[0x3d]	19479	1			T29	75		T22	37		T59	11
alert[0x3e]	3870	1			T14	40		T18	2		T22	35
alert[0x3f]	5664	1			T8	1		T9	11		T14	9
alert[0x40]	2361	1			T18	65		T38	12		T65	14

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	143710	1			T1	2		T2	9		T7	6519
class_i[0x1]	83600	1			T7	1		T8	1		T9	21
class_i[0x2]	106991	1			T8	15		T9	4		T14	125
class_i[0x3]	91589	1			T8	2		T9	18		T14	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

425229

1

T1

2

T2

9

T7

6520

alert_ping_fail

661

1

T8

19

T27

2

T33

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	18627	1			T14	807		T28	473		T29	52
alert_integrity_fail	alert[0x1]	4884	1			T7	21		T29	70		T22	646
alert_integrity_fail	alert[0x2]	10038	1			T18	15		T22	2		T59	1
alert_integrity_fail	alert[0x3]	6487	1			T18	260		T22	98		T73	2
alert_integrity_fail	alert[0x4]	5843	1			T14	322		T18	48		T65	141
alert_integrity_fail	alert[0x5]	2248	1			T7	94		T9	3		T18	5
alert_integrity_fail	alert[0x6]	12178	1			T7	432		T9	3		T14	142
alert_integrity_fail	alert[0x7]	5036	1			T29	135		T75	162		T223	6
alert_integrity_fail	alert[0x8]	5440	1			T28	265		T29	173		T18	4
alert_integrity_fail	alert[0x9]	1766	1			T7	50		T14	10		T29	117
alert_integrity_fail	alert[0xa]	2788	1			T29	35		T18	36		T42	614
alert_integrity_fail	alert[0xb]	5698	1			T14	36		T28	227		T59	2
alert_integrity_fail	alert[0xc]	7123	1			T9	5		T22	1135		T38	1
alert_integrity_fail	alert[0xd]	3343	1			T18	3		T22	7		T38	1
alert_integrity_fail	alert[0xe]	4009	1			T9	20		T14	25		T42	1292
alert_integrity_fail	alert[0xf]	5643	1			T7	20		T29	2401		T18	154
alert_integrity_fail	alert[0x10]	1406	1			T7	176		T14	23		T29	18
alert_integrity_fail	alert[0x11]	6220	1			T7	113		T14	71		T29	35
alert_integrity_fail	alert[0x12]	12982	1			T9	1		T18	81		T22	1
alert_integrity_fail	alert[0x13]	7337	1			T7	16		T14	15		T28	1294
alert_integrity_fail	alert[0x14]	1968	1			T14	249		T29	5		T18	4
alert_integrity_fail	alert[0x15]	14437	1			T14	28		T29	189		T18	450
alert_integrity_fail	alert[0x16]	3204	1			T28	129		T22	159		T73	3
alert_integrity_fail	alert[0x17]	7727	1			T14	160		T28	496		T18	57
alert_integrity_fail	alert[0x18]	7620	1			T7	92		T14	58		T28	106
alert_integrity_fail	alert[0x19]	3690	1			T22	28		T20	9		T44	1
alert_integrity_fail	alert[0x1a]	8459	1			T1	1		T7	852		T29	525
alert_integrity_fail	alert[0x1b]	5643	1			T29	869		T18	52		T65	8
alert_integrity_fail	alert[0x1c]	14043	1			T14	22		T18	139		T22	260
alert_integrity_fail	alert[0x1d]	4162	1			T9	1		T28	291		T68	4
alert_integrity_fail	alert[0x1e]	9792	1			T7	177		T14	166		T29	11
alert_integrity_fail	alert[0x1f]	6941	1			T7	60		T65	28		T286	249
alert_integrity_fail	alert[0x20]	1959	1			T14	5		T59	1		T68	3
alert_integrity_fail	alert[0x21]	2987	1			T28	8		T38	1		T59	1
alert_integrity_fail	alert[0x22]	3661	1			T7	91		T38	9		T20	18
alert_integrity_fail	alert[0x23]	6072	1			T7	70		T14	28		T18	283
alert_integrity_fail	alert[0x24]	2211	1			T7	20		T22	78		T43	50
alert_integrity_fail	alert[0x25]	4306	1			T7	87		T29	139		T22	147
alert_integrity_fail	alert[0x26]	6323	1			T28	42		T29	2		T18	42
alert_integrity_fail	alert[0x27]	2946	1			T7	71		T18	18		T65	64
alert_integrity_fail	alert[0x28]	6014	1			T44	53		T76	1800		T244	12
alert_integrity_fail	alert[0x29]	6841	1			T7	1438		T14	3		T29	517
alert_integrity_fail	alert[0x2a]	9745	1			T7	348		T14	1		T38	1
alert_integrity_fail	alert[0x2b]	9944	1			T9	1		T14	117		T28	340
alert_integrity_fail	alert[0x2c]	4403	1			T7	113		T14	319		T28	747
alert_integrity_fail	alert[0x2d]	7070	1			T7	25		T29	243		T22	17
alert_integrity_fail	alert[0x2e]	15602	1			T7	13		T14	4986		T22	5
alert_integrity_fail	alert[0x2f]	4880	1			T7	958		T14	19		T29	150
alert_integrity_fail	alert[0x30]	12303	1			T14	87		T29	878		T18	40
alert_integrity_fail	alert[0x31]	17232	1			T2	2		T7	141		T29	50
alert_integrity_fail	alert[0x32]	7958	1			T7	44		T9	4		T14	32
alert_integrity_fail	alert[0x33]	5687	1			T7	12		T14	211		T28	335
alert_integrity_fail	alert[0x34]	3117	1			T18	17		T22	34		T61	4
alert_integrity_fail	alert[0x35]	3502	1			T7	287		T34	2		T28	209
alert_integrity_fail	alert[0x36]	5774	1			T7	28		T28	96		T29	193
alert_integrity_fail	alert[0x37]	1823	1			T1	1		T14	13		T20	24
alert_integrity_fail	alert[0x38]	4546	1			T14	755		T28	31		T29	77
alert_integrity_fail	alert[0x39]	3531	1			T2	7		T18	1		T22	7
alert_integrity_fail	alert[0x3a]	10895	1			T7	272		T18	19		T38	32
alert_integrity_fail	alert[0x3b]	1600	1			T224	9		T274	141		T48	7
alert_integrity_fail	alert[0x3c]	4162	1			T7	399		T9	1		T28	210
alert_integrity_fail	alert[0x3d]	19472	1			T29	75		T22	37		T59	11
alert_integrity_fail	alert[0x3e]	3863	1			T14	40		T18	2		T22	35
alert_integrity_fail	alert[0x3f]	5658	1			T9	11		T14	9		T29	121
alert_integrity_fail	alert[0x40]	2360	1			T18	65		T38	12		T65	14
alert_ping_fail	alert[0x0]	10	1			T188	1		T294	1		T297	2
alert_ping_fail	alert[0x1]	10	1			T188	1		T294	1		T295	1
alert_ping_fail	alert[0x2]	10	1			T295	1		T297	1		T227	1
alert_ping_fail	alert[0x3]	9	1			T188	1		T294	1		T295	1
alert_ping_fail	alert[0x4]	8	1			T298	1		T299	1		T300	1
alert_ping_fail	alert[0x5]	10	1			T103	1		T301	1		T297	1
alert_ping_fail	alert[0x6]	5	1			T302	1		T303	1		T304	1
alert_ping_fail	alert[0x7]	12	1			T8	1		T293	1		T221	1
alert_ping_fail	alert[0x8]	25	1			T8	1		T188	1		T294	1
alert_ping_fail	alert[0x9]	8	1			T8	2		T188	1		T305	1
alert_ping_fail	alert[0xa]	11	1			T294	1		T213	1		T216	1
alert_ping_fail	alert[0xb]	11	1			T8	1		T103	1		T302	1
alert_ping_fail	alert[0xc]	6	1			T306	1		T182	1		T298	1
alert_ping_fail	alert[0xd]	12	1			T294	1		T307	1		T308	1
alert_ping_fail	alert[0xe]	8	1			T213	1		T309	1		T308	2
alert_ping_fail	alert[0xf]	8	1			T103	1		T307	1		T301	1
alert_ping_fail	alert[0x10]	10	1			T81	1		T213	1		T298	2
alert_ping_fail	alert[0x11]	8	1			T307	1		T227	1		T310	1
alert_ping_fail	alert[0x12]	7	1			T294	1		T295	1		T311	1
alert_ping_fail	alert[0x13]	17	1			T8	1		T103	1		T307	1
alert_ping_fail	alert[0x14]	12	1			T312	1		T229	1		T182	1
alert_ping_fail	alert[0x15]	10	1			T8	2		T33	1		T313	1
alert_ping_fail	alert[0x16]	15	1			T8	1		T296	1		T81	1
alert_ping_fail	alert[0x17]	14	1			T188	2		T294	1		T307	1
alert_ping_fail	alert[0x18]	9	1			T213	1		T297	1		T309	1
alert_ping_fail	alert[0x19]	10	1			T295	1		T309	1		T311	1
alert_ping_fail	alert[0x1a]	4	1			T103	1		T303	1		T305	1
alert_ping_fail	alert[0x1b]	12	1			T103	1		T188	1		T309	1
alert_ping_fail	alert[0x1c]	7	1			T307	1		T302	1		T213	1
alert_ping_fail	alert[0x1d]	12	1			T302	1		T297	3		T306	1
alert_ping_fail	alert[0x1e]	11	1			T297	1		T314	1		T315	2
alert_ping_fail	alert[0x1f]	7	1			T8	2		T294	1		T316	1
alert_ping_fail	alert[0x20]	24	1			T188	2		T295	2		T307	2
alert_ping_fail	alert[0x21]	5	1			T309	1		T317	1		T305	1
alert_ping_fail	alert[0x22]	14	1			T33	1		T296	1		T213	1
alert_ping_fail	alert[0x23]	6	1			T294	1		T310	1		T318	1
alert_ping_fail	alert[0x24]	11	1			T227	1		T298	1		T313	1
alert_ping_fail	alert[0x25]	7	1			T294	1		T309	1		T319	1
alert_ping_fail	alert[0x26]	9	1			T103	1		T188	1		T295	1
alert_ping_fail	alert[0x27]	10	1			T8	2		T311	1		T298	1
alert_ping_fail	alert[0x28]	20	1			T27	2		T294	1		T296	2
alert_ping_fail	alert[0x29]	8	1			T8	1		T302	1		T320	1
alert_ping_fail	alert[0x2a]	8	1			T295	1		T297	1		T288	2
alert_ping_fail	alert[0x2b]	10	1			T310	1		T299	1		T321	2
alert_ping_fail	alert[0x2c]	8	1			T322	1		T311	1		T298	1
alert_ping_fail	alert[0x2d]	10	1			T188	1		T294	1		T306	1
alert_ping_fail	alert[0x2e]	14	1			T8	1		T294	1		T295	2
alert_ping_fail	alert[0x2f]	10	1			T295	1		T301	1		T306	2
alert_ping_fail	alert[0x30]	9	1			T282	2		T310	1		T321	1
alert_ping_fail	alert[0x31]	13	1			T8	2		T309	1		T298	1
alert_ping_fail	alert[0x32]	17	1			T294	1		T295	1		T301	1
alert_ping_fail	alert[0x33]	11	1			T295	1		T307	1		T309	1
alert_ping_fail	alert[0x34]	12	1			T213	1		T306	1		T311	3
alert_ping_fail	alert[0x35]	12	1			T309	1		T311	1		T299	1
alert_ping_fail	alert[0x36]	14	1			T188	1		T294	1		T81	1
alert_ping_fail	alert[0x37]	4	1			T311	1		T323	1		T300	2
alert_ping_fail	alert[0x38]	9	1			T294	1		T302	1		T320	1
alert_ping_fail	alert[0x39]	8	1			T8	1		T103	1		T297	1
alert_ping_fail	alert[0x3a]	11	1			T188	1		T295	1		T307	1
alert_ping_fail	alert[0x3b]	11	1			T294	1		T313	2		T304	1
alert_ping_fail	alert[0x3c]	7	1			T309	1		T308	1		T323	1
alert_ping_fail	alert[0x3d]	7	1			T213	1		T227	1		T319	2
alert_ping_fail	alert[0x3e]	7	1			T294	1		T307	1		T311	1
alert_ping_fail	alert[0x3f]	6	1			T8	1		T306	1		T299	1
alert_ping_fail	alert[0x40]	1	1			T227	1		-	-		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	143472	1			T1	2		T2	9		T7	6519
alert_integrity_fail	class_i[0x1]	83436	1			T7	1		T9	21		T34	2
alert_integrity_fail	class_i[0x2]	106850	1			T9	4		T14	125		T28	5299
alert_integrity_fail	class_i[0x3]	91471	1			T9	18		T14	7		T29	11285
alert_ping_fail	class_i[0x0]	238	1			T8	1		T103	8		T188	1
alert_ping_fail	class_i[0x1]	164	1			T8	1		T27	2		T33	2
alert_ping_fail	class_i[0x2]	141	1			T8	15		T188	12		T295	1
alert_ping_fail	class_i[0x3]	118	1			T8	2		T188	1		T294	1