Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.71 100.00 100.00 100.00 99.38 99.60


Total test records in report: 825
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3895543667 Jun 28 04:59:14 PM PDT 24 Jun 28 04:59:26 PM PDT 24 123165388 ps
T772 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.917819220 Jun 28 04:59:38 PM PDT 24 Jun 28 04:59:40 PM PDT 24 15184930 ps
T773 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.447059657 Jun 28 04:59:44 PM PDT 24 Jun 28 04:59:47 PM PDT 24 11518508 ps
T774 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2460164416 Jun 28 04:59:34 PM PDT 24 Jun 28 05:00:26 PM PDT 24 4933163800 ps
T775 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.680098112 Jun 28 04:59:25 PM PDT 24 Jun 28 05:00:19 PM PDT 24 5129343591 ps
T776 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3037455889 Jun 28 04:59:45 PM PDT 24 Jun 28 04:59:47 PM PDT 24 7478505 ps
T777 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1506976077 Jun 28 04:59:44 PM PDT 24 Jun 28 04:59:46 PM PDT 24 42624174 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.35879814 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:54 PM PDT 24 633312259 ps
T150 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3277228584 Jun 28 04:59:27 PM PDT 24 Jun 28 04:59:33 PM PDT 24 214784222 ps
T145 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1257040977 Jun 28 04:59:16 PM PDT 24 Jun 28 04:59:21 PM PDT 24 195917846 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3289857181 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:35 PM PDT 24 97477695 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2734944854 Jun 28 04:59:14 PM PDT 24 Jun 28 05:01:41 PM PDT 24 4054211272 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3081270308 Jun 28 04:59:26 PM PDT 24 Jun 28 05:00:34 PM PDT 24 568402021 ps
T782 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.404245874 Jun 28 04:59:26 PM PDT 24 Jun 28 05:00:04 PM PDT 24 490635763 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.732040335 Jun 28 04:59:35 PM PDT 24 Jun 28 04:59:41 PM PDT 24 37899090 ps
T784 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2247339613 Jun 28 04:59:27 PM PDT 24 Jun 28 04:59:43 PM PDT 24 220666127 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1679632455 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:35 PM PDT 24 32368861 ps
T129 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.180233923 Jun 28 04:59:26 PM PDT 24 Jun 28 05:01:05 PM PDT 24 6726889165 ps
T118 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.811093983 Jun 28 04:59:15 PM PDT 24 Jun 28 05:02:21 PM PDT 24 6251870071 ps
T137 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2402241950 Jun 28 04:59:27 PM PDT 24 Jun 28 05:10:11 PM PDT 24 17382277087 ps
T786 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2898389521 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:50 PM PDT 24 1178570458 ps
T787 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2722333679 Jun 28 04:59:46 PM PDT 24 Jun 28 04:59:49 PM PDT 24 8274856 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2697514047 Jun 28 04:59:26 PM PDT 24 Jun 28 04:59:28 PM PDT 24 15514316 ps
T789 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3663926721 Jun 28 04:59:34 PM PDT 24 Jun 28 04:59:49 PM PDT 24 713057224 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1254075554 Jun 28 04:59:15 PM PDT 24 Jun 28 04:59:21 PM PDT 24 193145682 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3992937522 Jun 28 04:59:16 PM PDT 24 Jun 28 05:02:46 PM PDT 24 1653976705 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3279075250 Jun 28 04:59:29 PM PDT 24 Jun 28 05:05:35 PM PDT 24 22778687374 ps
T793 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4236353631 Jun 28 04:59:39 PM PDT 24 Jun 28 05:01:04 PM PDT 24 1380423808 ps
T155 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.422896727 Jun 28 04:59:30 PM PDT 24 Jun 28 04:59:34 PM PDT 24 46613515 ps
T794 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.498694167 Jun 28 04:59:37 PM PDT 24 Jun 28 05:00:14 PM PDT 24 446012183 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.838362713 Jun 28 04:59:25 PM PDT 24 Jun 28 04:59:35 PM PDT 24 198432090 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1332310789 Jun 28 04:59:16 PM PDT 24 Jun 28 04:59:20 PM PDT 24 33588880 ps
T134 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2746795265 Jun 28 04:59:14 PM PDT 24 Jun 28 05:02:33 PM PDT 24 5712281280 ps
T136 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.6024926 Jun 28 04:59:15 PM PDT 24 Jun 28 05:04:24 PM PDT 24 2258246600 ps
T797 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3773204971 Jun 28 04:59:29 PM PDT 24 Jun 28 04:59:54 PM PDT 24 331565870 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2412732131 Jun 28 04:59:18 PM PDT 24 Jun 28 05:03:41 PM PDT 24 16465695727 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1719725764 Jun 28 04:59:14 PM PDT 24 Jun 28 04:59:16 PM PDT 24 13412114 ps
T351 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1347075725 Jun 28 04:59:23 PM PDT 24 Jun 28 05:07:47 PM PDT 24 24646693337 ps
T133 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1499418036 Jun 28 04:59:34 PM PDT 24 Jun 28 05:16:20 PM PDT 24 50391020357 ps
T154 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.219756649 Jun 28 04:59:25 PM PDT 24 Jun 28 04:59:28 PM PDT 24 56136886 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1431770347 Jun 28 04:59:38 PM PDT 24 Jun 28 04:59:45 PM PDT 24 69051153 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1262550494 Jun 28 04:59:17 PM PDT 24 Jun 28 04:59:19 PM PDT 24 8265369 ps
T802 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3309471481 Jun 28 04:59:47 PM PDT 24 Jun 28 04:59:50 PM PDT 24 23119481 ps
T158 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3529051473 Jun 28 04:59:40 PM PDT 24 Jun 28 05:00:54 PM PDT 24 1148582630 ps
T803 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2607484654 Jun 28 04:59:40 PM PDT 24 Jun 28 04:59:46 PM PDT 24 94577217 ps
T135 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3204863709 Jun 28 04:59:33 PM PDT 24 Jun 28 05:17:23 PM PDT 24 14673568317 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1699302670 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:31 PM PDT 24 24005773 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4213501236 Jun 28 04:59:27 PM PDT 24 Jun 28 04:59:30 PM PDT 24 15160791 ps
T132 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3709209260 Jun 28 04:59:28 PM PDT 24 Jun 28 05:01:51 PM PDT 24 7313191447 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1777621810 Jun 28 04:59:13 PM PDT 24 Jun 28 04:59:18 PM PDT 24 130227550 ps
T191 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1186785405 Jun 28 04:59:17 PM PDT 24 Jun 28 05:02:06 PM PDT 24 2689461683 ps
T807 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.748866665 Jun 28 04:59:46 PM PDT 24 Jun 28 04:59:48 PM PDT 24 6257574 ps
T149 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4128656616 Jun 28 04:59:39 PM PDT 24 Jun 28 05:01:04 PM PDT 24 23769579817 ps
T808 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2591525638 Jun 28 04:59:27 PM PDT 24 Jun 28 04:59:42 PM PDT 24 148507836 ps
T809 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4112355435 Jun 28 04:59:47 PM PDT 24 Jun 28 04:59:50 PM PDT 24 11421582 ps
T810 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4093067699 Jun 28 04:59:38 PM PDT 24 Jun 28 04:59:44 PM PDT 24 71016685 ps
T811 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1556382167 Jun 28 04:59:37 PM PDT 24 Jun 28 04:59:40 PM PDT 24 10491616 ps
T350 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1942445476 Jun 28 04:59:31 PM PDT 24 Jun 28 05:16:20 PM PDT 24 12194120556 ps
T812 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4170312109 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:37 PM PDT 24 83732646 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.580149877 Jun 28 04:59:26 PM PDT 24 Jun 28 04:59:47 PM PDT 24 2536012130 ps
T814 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3435362597 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:48 PM PDT 24 242452718 ps
T815 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3905371426 Jun 28 04:59:45 PM PDT 24 Jun 28 04:59:47 PM PDT 24 9289067 ps
T816 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2786271908 Jun 28 04:59:26 PM PDT 24 Jun 28 04:59:30 PM PDT 24 26180689 ps
T146 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4174314740 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:33 PM PDT 24 71250646 ps
T349 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2948208051 Jun 28 04:59:26 PM PDT 24 Jun 28 05:07:54 PM PDT 24 35693670764 ps
T138 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4210704415 Jun 28 04:59:35 PM PDT 24 Jun 28 05:04:34 PM PDT 24 16606774186 ps
T817 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.372803377 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:34 PM PDT 24 47227228 ps
T818 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.270547903 Jun 28 04:59:28 PM PDT 24 Jun 28 04:59:40 PM PDT 24 692175115 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3389443319 Jun 28 04:59:25 PM PDT 24 Jun 28 04:59:29 PM PDT 24 174710614 ps
T820 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4235665844 Jun 28 04:59:36 PM PDT 24 Jun 28 04:59:46 PM PDT 24 436905310 ps
T821 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2067244857 Jun 28 04:59:36 PM PDT 24 Jun 28 04:59:48 PM PDT 24 171670346 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3426825991 Jun 28 04:59:15 PM PDT 24 Jun 28 05:03:30 PM PDT 24 14009427029 ps
T823 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.361654964 Jun 28 04:59:34 PM PDT 24 Jun 28 04:59:44 PM PDT 24 95053615 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2072500641 Jun 28 04:59:29 PM PDT 24 Jun 28 04:59:36 PM PDT 24 205105661 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3355584732 Jun 28 04:59:35 PM PDT 24 Jun 28 05:00:03 PM PDT 24 344548065 ps

Test location /workspace/coverage/default/37.alert_handler_entropy.1638672107
Short name T7
Test name
Test status
Simulation time 31498292752 ps
CPU time 1804.28 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:51:40 PM PDT 24
Peak memory 273764 kb
Host smart-f60432c0-ae60-4af9-a430-12595df4d141
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638672107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1638672107
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1837958128
Short name T22
Test name
Test status
Simulation time 84343012380 ps
CPU time 7283.24 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 07:23:12 PM PDT 24
Peak memory 339056 kb
Host smart-17d46442-9121-45e5-b484-62c1f09da791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837958128 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1837958128
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3806886794
Short name T6
Test name
Test status
Simulation time 114259680182 ps
CPU time 1169.74 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:42:11 PM PDT 24
Peak memory 273920 kb
Host smart-592915fb-236e-49b3-912e-51574c2c236c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806886794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3806886794
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2123784528
Short name T25
Test name
Test status
Simulation time 421130875 ps
CPU time 24.9 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:50 PM PDT 24
Peak memory 277672 kb
Host smart-c7643624-e72b-40bb-ac1e-e327b7b59b0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2123784528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2123784528
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1981086261
Short name T140
Test name
Test status
Simulation time 4065232853 ps
CPU time 82.55 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 05:00:55 PM PDT 24
Peak memory 240616 kb
Host smart-04bc86f5-cce4-4448-8a9e-68af2cf35780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1981086261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1981086261
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1985568572
Short name T14
Test name
Test status
Simulation time 171127919894 ps
CPU time 2931.68 seconds
Started Jun 28 05:19:16 PM PDT 24
Finished Jun 28 06:08:09 PM PDT 24
Peak memory 298948 kb
Host smart-9cebb7af-1ff6-4c01-85e1-0689741e7b36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985568572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1985568572
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2743688052
Short name T20
Test name
Test status
Simulation time 205034147200 ps
CPU time 3437.11 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 300312 kb
Host smart-a47f4c58-4ea0-4933-bcfb-ae141fcaa912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743688052 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2743688052
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2185003906
Short name T76
Test name
Test status
Simulation time 86416203224 ps
CPU time 2466.99 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 06:01:55 PM PDT 24
Peak memory 287120 kb
Host smart-d4db3657-3f86-47a6-8575-38c5dc4709ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185003906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2185003906
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4229365064
Short name T109
Test name
Test status
Simulation time 1585139244 ps
CPU time 184.08 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 05:02:43 PM PDT 24
Peak memory 265388 kb
Host smart-e83a9242-2029-498c-9041-1e57eba9f448
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4229365064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.4229365064
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2801721857
Short name T30
Test name
Test status
Simulation time 638674294 ps
CPU time 29.66 seconds
Started Jun 28 05:19:16 PM PDT 24
Finished Jun 28 05:19:47 PM PDT 24
Peak memory 249240 kb
Host smart-34ecc3c5-4e29-4546-808c-334fe130144d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2801721857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2801721857
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.148575142
Short name T48
Test name
Test status
Simulation time 58464204855 ps
CPU time 772.23 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 273608 kb
Host smart-c219c023-4589-4654-b401-f1235e59b7bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148575142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.148575142
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1977525920
Short name T110
Test name
Test status
Simulation time 5387341210 ps
CPU time 364.4 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 05:05:31 PM PDT 24
Peak memory 273636 kb
Host smart-9b8c83f3-3e76-4a2e-92d9-ab16a981665e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1977525920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1977525920
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1708327085
Short name T104
Test name
Test status
Simulation time 15373919798 ps
CPU time 653.51 seconds
Started Jun 28 04:59:17 PM PDT 24
Finished Jun 28 05:10:12 PM PDT 24
Peak memory 265408 kb
Host smart-ecc7de7f-fee1-4898-af37-68ed84c5d2d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708327085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1708327085
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1305669429
Short name T21
Test name
Test status
Simulation time 43102061569 ps
CPU time 2668.27 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 06:04:10 PM PDT 24
Peak memory 285504 kb
Host smart-a42800bb-52c8-4767-b13e-ddba9619970c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305669429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1305669429
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2282780999
Short name T8
Test name
Test status
Simulation time 14336974961 ps
CPU time 605.24 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:31:17 PM PDT 24
Peak memory 249136 kb
Host smart-10be9f8f-5498-4962-bfdd-1819a4a7672e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282780999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2282780999
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2941550640
Short name T97
Test name
Test status
Simulation time 226423265496 ps
CPU time 3080.35 seconds
Started Jun 28 05:19:28 PM PDT 24
Finished Jun 28 06:10:50 PM PDT 24
Peak memory 290024 kb
Host smart-42293f25-22e7-4731-bae7-52b36dcb80ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941550640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2941550640
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.660240891
Short name T56
Test name
Test status
Simulation time 31867785896 ps
CPU time 1981.86 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:52:43 PM PDT 24
Peak memory 290356 kb
Host smart-86cf3d87-6e3d-4ed6-9224-e9d478ca9dbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660240891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.660240891
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.765565930
Short name T128
Test name
Test status
Simulation time 49262935772 ps
CPU time 1026.93 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 05:16:44 PM PDT 24
Peak memory 265416 kb
Host smart-07ea0cd8-15ea-400a-a2cb-654cb44331e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765565930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.765565930
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1513850411
Short name T342
Test name
Test status
Simulation time 46422917 ps
CPU time 1.71 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 237508 kb
Host smart-f4907a4b-7ccf-4373-a5d8-07f7c7ba37b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1513850411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1513850411
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2937195399
Short name T126
Test name
Test status
Simulation time 15928279677 ps
CPU time 1130.29 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:18:20 PM PDT 24
Peak memory 265408 kb
Host smart-7df8baaa-33cb-480b-9de2-85221e56c256
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937195399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2937195399
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.17094580
Short name T294
Test name
Test status
Simulation time 50261599317 ps
CPU time 570.81 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:28:59 PM PDT 24
Peak memory 255916 kb
Host smart-74c12db8-cf44-4853-8b0a-80b8aef1def1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17094580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.17094580
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3548369713
Short name T58
Test name
Test status
Simulation time 35051464670 ps
CPU time 2109.86 seconds
Started Jun 28 05:22:12 PM PDT 24
Finished Jun 28 05:57:22 PM PDT 24
Peak memory 282212 kb
Host smart-0d05c249-e4ac-432a-9af5-6e1238568d2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548369713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3548369713
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3991520008
Short name T67
Test name
Test status
Simulation time 287275145788 ps
CPU time 3405.03 seconds
Started Jun 28 05:20:16 PM PDT 24
Finished Jun 28 06:17:02 PM PDT 24
Peak memory 301936 kb
Host smart-6e0803f1-9e61-44af-9ff5-9871e6d50988
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991520008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3991520008
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4104645857
Short name T125
Test name
Test status
Simulation time 4346736587 ps
CPU time 645.31 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:10:16 PM PDT 24
Peak memory 265416 kb
Host smart-38d7397c-1a15-450d-83d5-30c6ca554046
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104645857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4104645857
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3841052723
Short name T309
Test name
Test status
Simulation time 57112833802 ps
CPU time 605.19 seconds
Started Jun 28 05:20:15 PM PDT 24
Finished Jun 28 05:30:21 PM PDT 24
Peak memory 249384 kb
Host smart-550ddc7f-f631-40fc-b616-5a0ab1ea849d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841052723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3841052723
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1579514901
Short name T124
Test name
Test status
Simulation time 3787345762 ps
CPU time 271.46 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:04:02 PM PDT 24
Peak memory 265300 kb
Host smart-6c5612b4-26a8-4e2d-9115-f56bce6201c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1579514901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1579514901
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1293742825
Short name T337
Test name
Test status
Simulation time 33176354847 ps
CPU time 1413.84 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:43:39 PM PDT 24
Peak memory 286512 kb
Host smart-8016772b-a154-45d4-ae87-865b1961f9a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293742825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1293742825
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2949177048
Short name T332
Test name
Test status
Simulation time 105112069674 ps
CPU time 1633.02 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:48:36 PM PDT 24
Peak memory 273972 kb
Host smart-d2b7c810-e7f5-49e6-a165-12aee3a6b3ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949177048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2949177048
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.134476064
Short name T298
Test name
Test status
Simulation time 25588669943 ps
CPU time 542.07 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:28:27 PM PDT 24
Peak memory 249036 kb
Host smart-59b00b25-7e6d-4423-9b9b-4cbc43f3fb49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134476064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.134476064
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.234307128
Short name T263
Test name
Test status
Simulation time 124920790830 ps
CPU time 3715.36 seconds
Started Jun 28 05:19:41 PM PDT 24
Finished Jun 28 06:21:38 PM PDT 24
Peak memory 298504 kb
Host smart-0b204cab-72e0-40c2-8756-8ee68d5be280
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234307128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.234307128
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2065998675
Short name T107
Test name
Test status
Simulation time 13008579845 ps
CPU time 509.2 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 05:07:57 PM PDT 24
Peak memory 265404 kb
Host smart-8af193a1-8d22-49ff-b45f-22964886cf13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065998675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2065998675
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3000304964
Short name T29
Test name
Test status
Simulation time 172305852858 ps
CPU time 2531.79 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 06:03:35 PM PDT 24
Peak memory 285072 kb
Host smart-d23225f5-c61d-421e-a861-2ba4db6e2ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000304964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3000304964
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1019527688
Short name T345
Test name
Test status
Simulation time 10929760 ps
CPU time 1.33 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 04:59:36 PM PDT 24
Peak memory 237604 kb
Host smart-6718346d-cf65-4362-92a4-cf8f94933758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019527688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1019527688
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1282208744
Short name T47
Test name
Test status
Simulation time 46158805659 ps
CPU time 4387.51 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 354512 kb
Host smart-e411d968-82f5-49b8-aa1c-a73878ea540e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282208744 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1282208744
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.925790835
Short name T131
Test name
Test status
Simulation time 10377800688 ps
CPU time 374.94 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 05:05:47 PM PDT 24
Peak memory 266444 kb
Host smart-4ad98f20-33d2-4f54-b424-da344e9940bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=925790835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.925790835
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1252350693
Short name T295
Test name
Test status
Simulation time 44824623169 ps
CPU time 494.99 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:28:09 PM PDT 24
Peak memory 256560 kb
Host smart-75a184ab-4389-4419-8798-68725ac6c155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252350693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1252350693
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3948672590
Short name T330
Test name
Test status
Simulation time 40030626940 ps
CPU time 2317.36 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:59:49 PM PDT 24
Peak memory 290308 kb
Host smart-40eb5817-6d5a-46dc-9d2c-e62f262f4f74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948672590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3948672590
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.811093983
Short name T118
Test name
Test status
Simulation time 6251870071 ps
CPU time 185.4 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 05:02:21 PM PDT 24
Peak memory 272040 kb
Host smart-085dcf62-cb9d-445c-ab36-01323cd74b7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=811093983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.811093983
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.4228572688
Short name T259
Test name
Test status
Simulation time 8788925693 ps
CPU time 496.85 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:27:43 PM PDT 24
Peak memory 257580 kb
Host smart-84dcf3ae-05b2-420a-a5a8-82988315caa8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228572688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.4228572688
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3229698042
Short name T222
Test name
Test status
Simulation time 25025447721 ps
CPU time 690.26 seconds
Started Jun 28 05:20:33 PM PDT 24
Finished Jun 28 05:32:04 PM PDT 24
Peak memory 273440 kb
Host smart-6ae02602-101e-4123-a881-22f7c4ff0bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229698042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3229698042
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.823025954
Short name T79
Test name
Test status
Simulation time 36545973051 ps
CPU time 1634.75 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:48:06 PM PDT 24
Peak memory 290172 kb
Host smart-941417b6-7849-44ab-a127-8a8c61992c3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823025954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.823025954
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1019656061
Short name T321
Test name
Test status
Simulation time 470128623325 ps
CPU time 1717.98 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:49:51 PM PDT 24
Peak memory 273932 kb
Host smart-7a04afb9-d082-4553-961b-7ad141d08bc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019656061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1019656061
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1094287543
Short name T613
Test name
Test status
Simulation time 13347164716 ps
CPU time 576.24 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:31:13 PM PDT 24
Peak memory 249348 kb
Host smart-0f34e56c-1657-43f3-ac03-e5eb224ffa7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094287543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1094287543
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3438662957
Short name T269
Test name
Test status
Simulation time 11227756634 ps
CPU time 172.26 seconds
Started Jun 28 05:19:53 PM PDT 24
Finished Jun 28 05:22:47 PM PDT 24
Peak memory 257536 kb
Host smart-06b9f5e9-c605-4ed2-996d-e56fae822e88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438662957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3438662957
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2406541083
Short name T280
Test name
Test status
Simulation time 86785552123 ps
CPU time 2740 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 06:07:04 PM PDT 24
Peak memory 306496 kb
Host smart-a51f61ba-761a-44e2-aa62-a9090bb3d7a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406541083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2406541083
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.355701944
Short name T93
Test name
Test status
Simulation time 1130078705 ps
CPU time 75.76 seconds
Started Jun 28 05:22:21 PM PDT 24
Finished Jun 28 05:23:37 PM PDT 24
Peak memory 257488 kb
Host smart-a3cfb611-3833-4ce1-915c-eb049492b02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
1944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.355701944
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1603249379
Short name T103
Test name
Test status
Simulation time 5477773015 ps
CPU time 169.24 seconds
Started Jun 28 05:23:06 PM PDT 24
Finished Jun 28 05:25:56 PM PDT 24
Peak memory 248288 kb
Host smart-5e02ba4d-bc16-4822-8d45-c46d5aee627b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603249379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1603249379
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3164715659
Short name T147
Test name
Test status
Simulation time 1336760645 ps
CPU time 88.04 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 05:00:56 PM PDT 24
Peak memory 240552 kb
Host smart-5b44323d-8760-41e8-81a5-1e955eaa8d20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3164715659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3164715659
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.194020437
Short name T41
Test name
Test status
Simulation time 38287680484 ps
CPU time 2150.8 seconds
Started Jun 28 05:19:42 PM PDT 24
Finished Jun 28 05:55:34 PM PDT 24
Peak memory 306372 kb
Host smart-0077e0f2-8d12-4cde-885c-4c7b7299ab3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194020437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.194020437
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1942445476
Short name T350
Test name
Test status
Simulation time 12194120556 ps
CPU time 1007.88 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 05:16:20 PM PDT 24
Peak memory 273520 kb
Host smart-c986b57b-310f-4620-837d-3f290b7d0099
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942445476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1942445476
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1580198406
Short name T27
Test name
Test status
Simulation time 39148109126 ps
CPU time 819.71 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 274076 kb
Host smart-b525df6b-0bc5-49a9-afec-4c01d3a1b95d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580198406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1580198406
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1754970317
Short name T19
Test name
Test status
Simulation time 227738669705 ps
CPU time 3150.72 seconds
Started Jun 28 05:20:08 PM PDT 24
Finished Jun 28 06:12:40 PM PDT 24
Peak memory 289376 kb
Host smart-4c287844-14f7-40b9-9b8d-a2b8a2dd3aeb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754970317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1754970317
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.852359561
Short name T202
Test name
Test status
Simulation time 39541043 ps
CPU time 2.32 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:19:19 PM PDT 24
Peak memory 249520 kb
Host smart-ede22ed3-c9ff-4cf5-ad8a-f09dfacc1910
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=852359561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.852359561
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2120452960
Short name T195
Test name
Test status
Simulation time 18783030 ps
CPU time 2.75 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:18 PM PDT 24
Peak memory 249564 kb
Host smart-e75d590e-f98a-42f9-9f2c-9056c57e7114
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2120452960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2120452960
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2186460783
Short name T212
Test name
Test status
Simulation time 204435371 ps
CPU time 4.01 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:19:54 PM PDT 24
Peak memory 249520 kb
Host smart-8dc8b0ea-92fd-4e65-9ff4-88b587db70bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2186460783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2186460783
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3956450119
Short name T200
Test name
Test status
Simulation time 130482762 ps
CPU time 3.26 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:19:55 PM PDT 24
Peak memory 249568 kb
Host smart-ed0ee427-dcb8-47e9-8220-63d8bef142a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3956450119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3956450119
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.780545247
Short name T341
Test name
Test status
Simulation time 8546870 ps
CPU time 1.45 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237472 kb
Host smart-446aeb52-98c2-42a5-ab76-30e648a1e7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=780545247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.780545247
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.239848287
Short name T629
Test name
Test status
Simulation time 34408800888 ps
CPU time 1351.91 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:42:09 PM PDT 24
Peak memory 273928 kb
Host smart-096e1376-da36-414d-bfec-9823bb85021a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239848287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.239848287
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.948049177
Short name T284
Test name
Test status
Simulation time 13522336356 ps
CPU time 216.7 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:23:30 PM PDT 24
Peak memory 257536 kb
Host smart-d09b4963-a037-47d0-bc8c-0ea5e34f6c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94804
9177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.948049177
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3238581030
Short name T63
Test name
Test status
Simulation time 3240639563 ps
CPU time 32.59 seconds
Started Jun 28 05:20:56 PM PDT 24
Finished Jun 28 05:21:29 PM PDT 24
Peak memory 249424 kb
Host smart-43906e6c-532e-4c83-8cc4-2ed2c9b363f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
81030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3238581030
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2427112859
Short name T227
Test name
Test status
Simulation time 10233934211 ps
CPU time 235.46 seconds
Started Jun 28 05:21:58 PM PDT 24
Finished Jun 28 05:25:54 PM PDT 24
Peak memory 249048 kb
Host smart-4b5bf14f-8af4-4501-8cbb-9e91910e2731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427112859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2427112859
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3594927409
Short name T271
Test name
Test status
Simulation time 188017165024 ps
CPU time 2774.12 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 06:09:19 PM PDT 24
Peak memory 282176 kb
Host smart-40270355-2052-4578-8666-4ac91e05cd85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594927409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3594927409
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2134125331
Short name T258
Test name
Test status
Simulation time 79444159 ps
CPU time 5.79 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:31 PM PDT 24
Peak memory 249840 kb
Host smart-a0a22471-e9cc-4722-8d9d-020252f0a891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21341
25331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2134125331
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1456232032
Short name T300
Test name
Test status
Simulation time 24384976970 ps
CPU time 511.07 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:28:11 PM PDT 24
Peak memory 256068 kb
Host smart-5e3ce690-4675-47ef-a888-5c4bc602d9f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456232032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1456232032
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2454918624
Short name T53
Test name
Test status
Simulation time 14784636255 ps
CPU time 1388.44 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:42:50 PM PDT 24
Peak memory 290152 kb
Host smart-eed898e7-e92d-43c1-864e-eae0b6d967d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454918624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2454918624
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1257040977
Short name T145
Test name
Test status
Simulation time 195917846 ps
CPU time 4.04 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 04:59:21 PM PDT 24
Peak memory 237780 kb
Host smart-a466d09d-f629-4c72-8554-3c2a76b94f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1257040977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1257040977
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.96423409
Short name T106
Test name
Test status
Simulation time 47100461452 ps
CPU time 363.96 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 05:05:33 PM PDT 24
Peak memory 272536 kb
Host smart-ad34320b-fcd5-4bf6-b965-d60b8c2b686b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96423409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors
.96423409
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3609005508
Short name T120
Test name
Test status
Simulation time 7150696094 ps
CPU time 137.62 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 05:01:43 PM PDT 24
Peak memory 265464 kb
Host smart-69939eaf-331f-4a7c-b1f1-3feb8f690fa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3609005508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3609005508
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3471473302
Short name T105
Test name
Test status
Simulation time 6336957798 ps
CPU time 532.83 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 05:08:08 PM PDT 24
Peak memory 268100 kb
Host smart-7837d863-d0b7-45a0-b33b-6a95777917e6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471473302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3471473302
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.632022503
Short name T248
Test name
Test status
Simulation time 246089545 ps
CPU time 28.5 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:18 PM PDT 24
Peak memory 256768 kb
Host smart-df314b90-71ac-46f4-bc77-ddface947b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63202
2503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.632022503
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2097568526
Short name T254
Test name
Test status
Simulation time 205093345367 ps
CPU time 4562.49 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 338360 kb
Host smart-45f65216-7640-4880-b796-990399ec0dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097568526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2097568526
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1958457132
Short name T338
Test name
Test status
Simulation time 20448726298 ps
CPU time 1432.89 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:43:47 PM PDT 24
Peak memory 289836 kb
Host smart-19c7055e-f4ea-4313-aa25-121bfbd99193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958457132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1958457132
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2752764009
Short name T257
Test name
Test status
Simulation time 417792715 ps
CPU time 32.94 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:36 PM PDT 24
Peak memory 256896 kb
Host smart-93612b35-9c20-4ee8-8e17-ee62c8a2366b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27527
64009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2752764009
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1482927405
Short name T249
Test name
Test status
Simulation time 264338296255 ps
CPU time 3737.03 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 06:22:21 PM PDT 24
Peak memory 337936 kb
Host smart-79460e8d-ca43-4f1c-b164-d5b23daebe78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482927405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1482927405
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1176760367
Short name T223
Test name
Test status
Simulation time 1399828546 ps
CPU time 27.36 seconds
Started Jun 28 05:20:08 PM PDT 24
Finished Jun 28 05:20:37 PM PDT 24
Peak memory 256428 kb
Host smart-d0b5991c-f3c5-4ee0-840a-77f01fd30823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767
60367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1176760367
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.870369039
Short name T334
Test name
Test status
Simulation time 56540061988 ps
CPU time 727.62 seconds
Started Jun 28 05:20:13 PM PDT 24
Finished Jun 28 05:32:21 PM PDT 24
Peak memory 272460 kb
Host smart-a8498eed-17a0-49aa-b426-b742ec8f4719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870369039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.870369039
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.619759210
Short name T100
Test name
Test status
Simulation time 3635995459 ps
CPU time 36.79 seconds
Started Jun 28 05:20:16 PM PDT 24
Finished Jun 28 05:20:53 PM PDT 24
Peak memory 256352 kb
Host smart-b9bdb1ab-8a11-46e0-9de2-ae5d81169ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61975
9210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.619759210
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3820289472
Short name T88
Test name
Test status
Simulation time 742994119 ps
CPU time 23.79 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 05:20:38 PM PDT 24
Peak memory 248608 kb
Host smart-2270e4f7-214a-4f89-b8e6-286981853d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
89472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3820289472
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1600938216
Short name T49
Test name
Test status
Simulation time 2140916927 ps
CPU time 14.83 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:21:06 PM PDT 24
Peak memory 249272 kb
Host smart-198aaf01-1280-4209-9f48-b641c5077660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
38216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1600938216
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2009965254
Short name T250
Test name
Test status
Simulation time 245747043 ps
CPU time 9.56 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:21:00 PM PDT 24
Peak memory 249300 kb
Host smart-5e7c5180-751b-4582-a143-a57189baf48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
65254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2009965254
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.315142747
Short name T275
Test name
Test status
Simulation time 12824998315 ps
CPU time 1032.86 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:38:35 PM PDT 24
Peak memory 283604 kb
Host smart-b6bc439d-85d0-4b97-b071-1a97b262d1ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315142747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.315142747
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.586855955
Short name T253
Test name
Test status
Simulation time 36658196593 ps
CPU time 923.23 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:38:18 PM PDT 24
Peak memory 273992 kb
Host smart-598d9f37-49be-4d88-b604-bc482d8da61a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586855955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.586855955
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3881011529
Short name T86
Test name
Test status
Simulation time 60553446173 ps
CPU time 1241.05 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:40:18 PM PDT 24
Peak memory 286780 kb
Host smart-eb4f8d58-0f37-4419-972e-bad4bde4b7ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881011529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3881011529
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.517538549
Short name T73
Test name
Test status
Simulation time 72103719456 ps
CPU time 1263.63 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:40:29 PM PDT 24
Peak memory 286020 kb
Host smart-16aef765-504a-41ea-bbaa-a3875dc14797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517538549 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.517538549
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1186785405
Short name T191
Test name
Test status
Simulation time 2689461683 ps
CPU time 168.98 seconds
Started Jun 28 04:59:17 PM PDT 24
Finished Jun 28 05:02:06 PM PDT 24
Peak memory 265460 kb
Host smart-c05f97c3-b02a-479c-9258-71f9f2c6ff6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1186785405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1186785405
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2801664215
Short name T113
Test name
Test status
Simulation time 6368726323 ps
CPU time 156.89 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 05:02:09 PM PDT 24
Peak memory 257260 kb
Host smart-56759e13-e9df-435d-89d8-a06ecee4c8da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2801664215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2801664215
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.911892298
Short name T139
Test name
Test status
Simulation time 942179356 ps
CPU time 68.04 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 05:00:43 PM PDT 24
Peak memory 240468 kb
Host smart-e7cb9c8c-90ca-4fb2-8611-66893515c9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=911892298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.911892298
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.503164178
Short name T153
Test name
Test status
Simulation time 73500130 ps
CPU time 2.2 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 04:59:42 PM PDT 24
Peak memory 237932 kb
Host smart-96e40abf-bc74-4581-a109-09a6b538fbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=503164178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.503164178
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3495029431
Short name T152
Test name
Test status
Simulation time 230163246 ps
CPU time 2.96 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 04:59:19 PM PDT 24
Peak memory 237448 kb
Host smart-ddcccbae-6aab-4053-9b77-aa799012b5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3495029431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3495029431
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.422896727
Short name T155
Test name
Test status
Simulation time 46613515 ps
CPU time 2.69 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 04:59:34 PM PDT 24
Peak memory 237592 kb
Host smart-29e9e404-3b79-4b30-9509-3ed139f095df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=422896727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.422896727
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4174314740
Short name T146
Test name
Test status
Simulation time 71250646 ps
CPU time 2.34 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:33 PM PDT 24
Peak memory 236644 kb
Host smart-4a9a463f-9e54-4ff3-aa43-c5310dae5bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4174314740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4174314740
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3899754307
Short name T123
Test name
Test status
Simulation time 18402037320 ps
CPU time 640.84 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 05:10:15 PM PDT 24
Peak memory 265416 kb
Host smart-623b81af-63ba-47c7-a8dc-da6f1cbaf4da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899754307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3899754307
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.482795951
Short name T141
Test name
Test status
Simulation time 11225011287 ps
CPU time 83.31 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 05:01:01 PM PDT 24
Peak memory 238732 kb
Host smart-e5a81d42-66f2-448c-9d84-304aa5913028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=482795951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.482795951
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3134561179
Short name T148
Test name
Test status
Simulation time 2459911092 ps
CPU time 49.27 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:00:20 PM PDT 24
Peak memory 240580 kb
Host smart-5d9b3d00-7ac3-4d25-821c-2e0e49174e06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3134561179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3134561179
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4128656616
Short name T149
Test name
Test status
Simulation time 23769579817 ps
CPU time 83.96 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 05:01:04 PM PDT 24
Peak memory 240552 kb
Host smart-a3eea070-1c83-4dfd-a73a-13bbc638ac03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4128656616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4128656616
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3529051473
Short name T158
Test name
Test status
Simulation time 1148582630 ps
CPU time 72.88 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 05:00:54 PM PDT 24
Peak memory 240492 kb
Host smart-2c87a887-dcb1-4980-a01d-c02101aae396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3529051473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3529051473
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1892436425
Short name T156
Test name
Test status
Simulation time 51673577 ps
CPU time 3.61 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 04:59:18 PM PDT 24
Peak memory 237600 kb
Host smart-bc6eb45d-9360-438e-91bb-1017cfb98f97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1892436425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1892436425
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3277228584
Short name T150
Test name
Test status
Simulation time 214784222 ps
CPU time 4.32 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 04:59:33 PM PDT 24
Peak memory 237856 kb
Host smart-c44ec976-9419-4efc-9bd4-736a33b75599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3277228584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3277228584
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.219756649
Short name T154
Test name
Test status
Simulation time 56136886 ps
CPU time 2.12 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 04:59:28 PM PDT 24
Peak memory 237592 kb
Host smart-b0aacfbc-76bd-4e55-a350-3c915e3fc4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=219756649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.219756649
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1815822083
Short name T15
Test name
Test status
Simulation time 261190862402 ps
CPU time 3663.36 seconds
Started Jun 28 05:23:04 PM PDT 24
Finished Jun 28 06:24:09 PM PDT 24
Peak memory 306452 kb
Host smart-5a4fc8b7-cb4f-4886-9b7a-dd7cc30cd92c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815822083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1815822083
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2538927488
Short name T177
Test name
Test status
Simulation time 1088544506 ps
CPU time 140.7 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 05:01:38 PM PDT 24
Peak memory 240552 kb
Host smart-da08594d-657d-493a-ab20-7d1e7b9e6fd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2538927488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2538927488
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3992937522
Short name T791
Test name
Test status
Simulation time 1653976705 ps
CPU time 208.77 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 05:02:46 PM PDT 24
Peak memory 240548 kb
Host smart-7b3ccb1f-7f59-4cd2-b633-bd0f3592ac0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3992937522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3992937522
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1254075554
Short name T790
Test name
Test status
Simulation time 193145682 ps
CPU time 5.03 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 04:59:21 PM PDT 24
Peak memory 248716 kb
Host smart-72b11ae5-b39c-4403-a183-416dcfce4b27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1254075554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1254075554
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2933924437
Short name T724
Test name
Test status
Simulation time 38522674 ps
CPU time 4.78 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 04:59:20 PM PDT 24
Peak memory 239576 kb
Host smart-a96cae4b-0ea2-4d0b-babc-50a7c8ed793a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933924437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2933924437
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1762614238
Short name T715
Test name
Test status
Simulation time 35399795 ps
CPU time 3.44 seconds
Started Jun 28 04:59:20 PM PDT 24
Finished Jun 28 04:59:23 PM PDT 24
Peak memory 237492 kb
Host smart-b19c0507-eb92-480e-8b40-c4b0b67427a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1762614238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1762614238
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1719725764
Short name T799
Test name
Test status
Simulation time 13412114 ps
CPU time 1.53 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 04:59:16 PM PDT 24
Peak memory 236656 kb
Host smart-640162de-376c-442e-820e-5b547644bb4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719725764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1719725764
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3673354712
Short name T727
Test name
Test status
Simulation time 597280529 ps
CPU time 39.03 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 04:59:58 PM PDT 24
Peak memory 244852 kb
Host smart-063565eb-5031-4bae-aa75-fb9fbce19a0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3673354712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3673354712
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1777621810
Short name T806
Test name
Test status
Simulation time 130227550 ps
CPU time 4.71 seconds
Started Jun 28 04:59:13 PM PDT 24
Finished Jun 28 04:59:18 PM PDT 24
Peak memory 249828 kb
Host smart-a9898533-6352-4a68-92f3-804c50d98dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1777621810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1777621810
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3426825991
Short name T822
Test name
Test status
Simulation time 14009427029 ps
CPU time 253.92 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 05:03:30 PM PDT 24
Peak memory 240648 kb
Host smart-420b4df2-1505-4816-8231-1ea4120f0de5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3426825991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3426825991
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.309746612
Short name T753
Test name
Test status
Simulation time 4807975875 ps
CPU time 110 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 05:01:04 PM PDT 24
Peak memory 237660 kb
Host smart-e8c3c48f-48ac-42ea-bca7-e1cba797a62e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=309746612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.309746612
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3877393296
Short name T734
Test name
Test status
Simulation time 254539784 ps
CPU time 4.17 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 04:59:20 PM PDT 24
Peak memory 240548 kb
Host smart-6b69f94f-cd02-4ce5-9cb0-4ef98e9594f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3877393296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3877393296
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3747807551
Short name T708
Test name
Test status
Simulation time 520219702 ps
CPU time 8.73 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 04:59:24 PM PDT 24
Peak memory 238312 kb
Host smart-11dec702-5ab0-4aab-8c59-5ead836b56d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747807551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3747807551
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1727390821
Short name T761
Test name
Test status
Simulation time 126104281 ps
CPU time 5.23 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 04:59:22 PM PDT 24
Peak memory 237564 kb
Host smart-80419616-b366-41d1-89d4-f6cc095393bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1727390821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1727390821
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1190155814
Short name T736
Test name
Test status
Simulation time 11189070 ps
CPU time 1.41 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 04:59:20 PM PDT 24
Peak memory 237604 kb
Host smart-b90c9a39-e652-444f-a8f6-653eaf2bd9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190155814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1190155814
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2937180797
Short name T730
Test name
Test status
Simulation time 2740180431 ps
CPU time 46.79 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 05:00:06 PM PDT 24
Peak memory 245772 kb
Host smart-99b7e6f3-0703-4605-82c2-c8289c3d15b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2937180797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2937180797
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3911908709
Short name T121
Test name
Test status
Simulation time 20638046363 ps
CPU time 156.28 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 05:01:52 PM PDT 24
Peak memory 265460 kb
Host smart-65019e01-fa13-41b7-aaf9-5f48353f209a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3911908709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3911908709
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1200769219
Short name T130
Test name
Test status
Simulation time 6386213695 ps
CPU time 476.03 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 05:07:11 PM PDT 24
Peak memory 265420 kb
Host smart-fd243a90-a2b8-42d9-97e1-e1c1a95dba48
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200769219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1200769219
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1080504733
Short name T751
Test name
Test status
Simulation time 118473973 ps
CPU time 8.13 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 04:59:24 PM PDT 24
Peak memory 247260 kb
Host smart-f9e8c998-e4ea-4caa-ac05-4d4ecb830ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1080504733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1080504733
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2878099415
Short name T151
Test name
Test status
Simulation time 5817963625 ps
CPU time 40.16 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 04:59:58 PM PDT 24
Peak memory 240512 kb
Host smart-9180aaaa-dcb8-41e6-9bf3-a70c465df997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2878099415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2878099415
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2576568564
Short name T749
Test name
Test status
Simulation time 484064137 ps
CPU time 11.64 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 04:59:43 PM PDT 24
Peak memory 251872 kb
Host smart-54d9299f-b610-4501-9d58-a58d378fdbd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576568564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2576568564
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1533424518
Short name T176
Test name
Test status
Simulation time 467900155 ps
CPU time 8.83 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 237568 kb
Host smart-28bf9ec8-3a63-4ab4-8090-e7018bbc2060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1533424518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1533424518
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4076620164
Short name T766
Test name
Test status
Simulation time 8493087 ps
CPU time 1.39 seconds
Started Jun 28 04:59:29 PM PDT 24
Finished Jun 28 04:59:32 PM PDT 24
Peak memory 236728 kb
Host smart-60926b9c-3fdb-4138-871b-291bd9097db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4076620164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4076620164
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3773204971
Short name T797
Test name
Test status
Simulation time 331565870 ps
CPU time 23.78 seconds
Started Jun 28 04:59:29 PM PDT 24
Finished Jun 28 04:59:54 PM PDT 24
Peak memory 245796 kb
Host smart-baaefe85-595e-4440-b686-e83f80f132b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3773204971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3773204971
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3709209260
Short name T132
Test name
Test status
Simulation time 7313191447 ps
CPU time 141.14 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:01:51 PM PDT 24
Peak memory 266428 kb
Host smart-30dcb2d8-32e8-4332-ad58-f3e4e20c0395
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3709209260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3709209260
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4170312109
Short name T812
Test name
Test status
Simulation time 83732646 ps
CPU time 7.05 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:37 PM PDT 24
Peak memory 249148 kb
Host smart-856635db-c8c4-4975-965b-25acd0bd84cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170312109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4170312109
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3534002140
Short name T714
Test name
Test status
Simulation time 35081559 ps
CPU time 5.75 seconds
Started Jun 28 04:59:32 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 242188 kb
Host smart-1ec61405-9518-4e1d-9088-14cc00cbba58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534002140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3534002140
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.291604864
Short name T721
Test name
Test status
Simulation time 493923181 ps
CPU time 6.09 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 237572 kb
Host smart-6b3ef7a8-133e-4cdd-a7a5-e6b4da49326c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=291604864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.291604864
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3769838624
Short name T712
Test name
Test status
Simulation time 18962075 ps
CPU time 1.82 seconds
Started Jun 28 04:59:29 PM PDT 24
Finished Jun 28 04:59:33 PM PDT 24
Peak memory 237432 kb
Host smart-1466b878-a819-4d66-bd8b-4c80674eb2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3769838624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3769838624
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2990090491
Short name T768
Test name
Test status
Simulation time 271690039 ps
CPU time 18.68 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 04:59:51 PM PDT 24
Peak memory 244824 kb
Host smart-f195e8e9-a3b1-4757-82e5-4dc9901fc7c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2990090491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2990090491
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2443016300
Short name T728
Test name
Test status
Simulation time 292897312 ps
CPU time 18.94 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 248808 kb
Host smart-84e0eab9-3af1-400d-86e2-3c6db5561f93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2443016300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2443016300
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.946974205
Short name T718
Test name
Test status
Simulation time 120362212 ps
CPU time 6.99 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 04:59:39 PM PDT 24
Peak memory 256976 kb
Host smart-93731b4a-a282-499f-913f-a52ddcbfcfe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946974205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.946974205
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3014452896
Short name T750
Test name
Test status
Simulation time 64365743 ps
CPU time 3.22 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 04:59:36 PM PDT 24
Peak memory 237496 kb
Host smart-9a622754-033c-4b62-9a55-6a34ad39803d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3014452896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3014452896
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4022200843
Short name T144
Test name
Test status
Simulation time 10901792 ps
CPU time 1.31 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 236660 kb
Host smart-d49667cb-d5cc-4c11-98b8-475071346728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4022200843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4022200843
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2282482436
Short name T157
Test name
Test status
Simulation time 980797878 ps
CPU time 13.79 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 248744 kb
Host smart-74c1944a-54fc-4e50-87a2-9a2a7f6c2276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2282482436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2282482436
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.151387720
Short name T117
Test name
Test status
Simulation time 18777781930 ps
CPU time 290.88 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 05:04:23 PM PDT 24
Peak memory 265456 kb
Host smart-28e80629-4894-41fa-817c-57b2d8834b8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=151387720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.151387720
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1240697601
Short name T702
Test name
Test status
Simulation time 175271889 ps
CPU time 13.19 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 248808 kb
Host smart-cb77735b-6caf-4c72-9565-dbfa30430d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1240697601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1240697601
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.208603176
Short name T744
Test name
Test status
Simulation time 118775043 ps
CPU time 5.66 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 251592 kb
Host smart-78462791-0808-415b-8cee-05495c2a8de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208603176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.208603176
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1600364550
Short name T348
Test name
Test status
Simulation time 737597128 ps
CPU time 5.11 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 04:59:42 PM PDT 24
Peak memory 237600 kb
Host smart-12c13ba5-802f-4845-8b84-2c821b4f01f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1600364550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1600364550
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1981505141
Short name T719
Test name
Test status
Simulation time 13870819 ps
CPU time 1.3 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 235592 kb
Host smart-18d58d19-4081-412d-9f22-8ce1e6857b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981505141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1981505141
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2460164416
Short name T774
Test name
Test status
Simulation time 4933163800 ps
CPU time 51.59 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 05:00:26 PM PDT 24
Peak memory 245860 kb
Host smart-94859949-7c23-4316-a2d3-1dd0721edde5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2460164416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2460164416
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1865178229
Short name T747
Test name
Test status
Simulation time 139216328 ps
CPU time 6.39 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 248716 kb
Host smart-75691a27-ef93-4d6d-9c5c-ec368be08ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1865178229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1865178229
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3622020967
Short name T189
Test name
Test status
Simulation time 32283040 ps
CPU time 2.76 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 237596 kb
Host smart-35361ef9-8d54-46fe-8ac5-8d24437a288b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3622020967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3622020967
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3105865368
Short name T709
Test name
Test status
Simulation time 164475291 ps
CPU time 12.06 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 04:59:52 PM PDT 24
Peak memory 248792 kb
Host smart-4dbed9e3-8e61-4f0a-b848-ab9ec8885cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105865368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3105865368
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2607484654
Short name T803
Test name
Test status
Simulation time 94577217 ps
CPU time 4.73 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 236616 kb
Host smart-365ed3d2-02d1-4838-a563-bdf2801f5c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2607484654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2607484654
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.917819220
Short name T772
Test name
Test status
Simulation time 15184930 ps
CPU time 1.83 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 235624 kb
Host smart-a3473bdb-7e8a-4e48-836b-feae0cd42afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=917819220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.917819220
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1012575571
Short name T174
Test name
Test status
Simulation time 7242581907 ps
CPU time 38.95 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 05:00:16 PM PDT 24
Peak memory 245824 kb
Host smart-a5254d92-3704-446e-a2d8-8cdab8bd3169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1012575571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1012575571
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1394508663
Short name T114
Test name
Test status
Simulation time 20888310974 ps
CPU time 356.75 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 05:05:31 PM PDT 24
Peak memory 265672 kb
Host smart-8aea3f56-20c6-47d2-a5dd-16dda671f3d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394508663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1394508663
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2067244857
Short name T821
Test name
Test status
Simulation time 171670346 ps
CPU time 11.9 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 248468 kb
Host smart-7c541405-ca6c-44e6-b76f-a3835a013fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2067244857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2067244857
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.498694167
Short name T794
Test name
Test status
Simulation time 446012183 ps
CPU time 36.59 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 05:00:14 PM PDT 24
Peak memory 240524 kb
Host smart-e5ca2f88-3d5e-4794-b01e-9f49a0e87249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=498694167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.498694167
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.732040335
Short name T783
Test name
Test status
Simulation time 37899090 ps
CPU time 6 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 04:59:41 PM PDT 24
Peak memory 248808 kb
Host smart-6cf5f601-5fad-48ef-a9c7-c5758589f3cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732040335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.732040335
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2664697636
Short name T726
Test name
Test status
Simulation time 499237325 ps
CPU time 8.86 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 04:59:45 PM PDT 24
Peak memory 240448 kb
Host smart-b5ac85f7-44fe-43fa-aeab-838b8a6816a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2664697636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2664697636
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2354721179
Short name T711
Test name
Test status
Simulation time 251479496 ps
CPU time 18.86 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 04:59:55 PM PDT 24
Peak memory 240496 kb
Host smart-f97f9e17-e543-4407-bcc1-33464386d958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2354721179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2354721179
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1499418036
Short name T133
Test name
Test status
Simulation time 50391020357 ps
CPU time 1005.24 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 05:16:20 PM PDT 24
Peak memory 272896 kb
Host smart-9a3312cd-dcf8-4037-8a27-82e5ff8fdc0b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499418036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1499418036
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3663926721
Short name T789
Test name
Test status
Simulation time 713057224 ps
CPU time 14.75 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 254944 kb
Host smart-8c94e0b4-99ce-498b-8f75-454eb4e07087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3663926721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3663926721
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4235665844
Short name T820
Test name
Test status
Simulation time 436905310 ps
CPU time 8.64 seconds
Started Jun 28 04:59:36 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 240992 kb
Host smart-00a12013-2cae-4446-880e-78a809eb71bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235665844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4235665844
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.361654964
Short name T823
Test name
Test status
Simulation time 95053615 ps
CPU time 8.95 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 04:59:44 PM PDT 24
Peak memory 240492 kb
Host smart-4e8fe503-05a4-4bab-b1d4-38c0151cca6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=361654964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.361654964
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.793790875
Short name T754
Test name
Test status
Simulation time 4728772876 ps
CPU time 42.23 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 05:00:16 PM PDT 24
Peak memory 248792 kb
Host smart-1e6eeb69-274c-43c3-9e17-c180cd9d2b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=793790875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.793790875
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4236353631
Short name T793
Test name
Test status
Simulation time 1380423808 ps
CPU time 84.14 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 05:01:04 PM PDT 24
Peak memory 265396 kb
Host smart-05ed18f9-98b0-4dfa-82e7-e2d85cba7302
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236353631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4236353631
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3204863709
Short name T135
Test name
Test status
Simulation time 14673568317 ps
CPU time 1069.38 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 05:17:23 PM PDT 24
Peak memory 265404 kb
Host smart-62260f4a-2662-485a-95c9-59c7c4402d81
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204863709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3204863709
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.228028713
Short name T703
Test name
Test status
Simulation time 806586286 ps
CPU time 19.05 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 04:59:59 PM PDT 24
Peak memory 254552 kb
Host smart-f4a1a195-d39a-42a9-8570-781da01ce596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=228028713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.228028713
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3294981127
Short name T347
Test name
Test status
Simulation time 222443739 ps
CPU time 7.85 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 252116 kb
Host smart-c0877d21-55b0-408b-8602-9d44dffb3964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294981127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3294981127
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1431770347
Short name T800
Test name
Test status
Simulation time 69051153 ps
CPU time 6.08 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 04:59:45 PM PDT 24
Peak memory 237592 kb
Host smart-141343c9-9534-4fca-bf26-f53ac630f8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1431770347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1431770347
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1556382167
Short name T811
Test name
Test status
Simulation time 10491616 ps
CPU time 1.53 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 236736 kb
Host smart-9c84b8c1-6c10-457d-8cdf-b8f15511bc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1556382167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1556382167
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3488379608
Short name T723
Test name
Test status
Simulation time 613490432 ps
CPU time 38.74 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 05:00:16 PM PDT 24
Peak memory 248648 kb
Host smart-3d3bf48a-08e2-4ed5-89d2-c25ef1ceafa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3488379608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3488379608
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4210704415
Short name T138
Test name
Test status
Simulation time 16606774186 ps
CPU time 298.03 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 05:04:34 PM PDT 24
Peak memory 265460 kb
Host smart-e400e11b-108b-4172-8648-0237d8b861f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4210704415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4210704415
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2603633770
Short name T112
Test name
Test status
Simulation time 8827304448 ps
CPU time 311.71 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 05:04:53 PM PDT 24
Peak memory 265364 kb
Host smart-700927b4-0daf-4760-bbe6-11e7630f3130
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603633770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2603633770
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2378053318
Short name T701
Test name
Test status
Simulation time 244521709 ps
CPU time 17.19 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 04:59:55 PM PDT 24
Peak memory 255056 kb
Host smart-7e739730-ed54-41d2-ad70-4d41c6060032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2378053318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2378053318
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4093067699
Short name T810
Test name
Test status
Simulation time 71016685 ps
CPU time 5.45 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 04:59:44 PM PDT 24
Peak memory 256972 kb
Host smart-a725f65a-62e9-447c-84c3-ca0f685ad6db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093067699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4093067699
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2055230663
Short name T731
Test name
Test status
Simulation time 95218124 ps
CPU time 8.35 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 237592 kb
Host smart-db089718-9de3-4d67-877e-3a5febce25f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2055230663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2055230663
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1626352324
Short name T767
Test name
Test status
Simulation time 8585920 ps
CPU time 1.29 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 04:59:41 PM PDT 24
Peak memory 236676 kb
Host smart-7bcd3602-53ea-4fa1-b7a4-55a29bdcd626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1626352324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1626352324
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3355584732
Short name T825
Test name
Test status
Simulation time 344548065 ps
CPU time 27.14 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 05:00:03 PM PDT 24
Peak memory 248724 kb
Host smart-3840a59e-0e40-4c1d-ac06-28728563f3f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355584732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3355584732
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3214100939
Short name T122
Test name
Test status
Simulation time 6907624615 ps
CPU time 194.53 seconds
Started Jun 28 04:59:33 PM PDT 24
Finished Jun 28 05:02:48 PM PDT 24
Peak memory 265428 kb
Host smart-5ce9b883-8a7d-47d5-8597-5262cfbf465a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3214100939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3214100939
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.168695370
Short name T127
Test name
Test status
Simulation time 22743842705 ps
CPU time 470.45 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 05:07:29 PM PDT 24
Peak memory 265456 kb
Host smart-572b3e49-4493-4ef5-9fc9-a308a4355d25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168695370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.168695370
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4180886373
Short name T699
Test name
Test status
Simulation time 896858142 ps
CPU time 15.25 seconds
Started Jun 28 04:59:40 PM PDT 24
Finished Jun 28 04:59:56 PM PDT 24
Peak memory 248736 kb
Host smart-001c8d08-fdc8-4a85-b126-4b9a0bdd2115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4180886373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4180886373
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4173659338
Short name T740
Test name
Test status
Simulation time 77487439 ps
CPU time 8.64 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:53 PM PDT 24
Peak memory 252100 kb
Host smart-64c172e6-6dd8-4a32-b555-50193740e815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173659338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4173659338
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2166824508
Short name T710
Test name
Test status
Simulation time 64724753 ps
CPU time 3.19 seconds
Started Jun 28 04:59:34 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 237592 kb
Host smart-03104db8-89f3-4147-b89b-761722d80c87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2166824508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2166824508
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2807195073
Short name T762
Test name
Test status
Simulation time 19355584 ps
CPU time 1.42 seconds
Started Jun 28 04:59:38 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 237604 kb
Host smart-fc3a00a8-4426-4da5-be21-86dad18b5ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807195073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2807195073
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3372405870
Short name T729
Test name
Test status
Simulation time 492964821 ps
CPU time 19.52 seconds
Started Jun 28 04:59:37 PM PDT 24
Finished Jun 28 04:59:57 PM PDT 24
Peak memory 240520 kb
Host smart-d91d20c9-acce-4e61-a680-f76f5d22c6cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3372405870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3372405870
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3683485829
Short name T108
Test name
Test status
Simulation time 4809402517 ps
CPU time 325.61 seconds
Started Jun 28 04:59:39 PM PDT 24
Finished Jun 28 05:05:05 PM PDT 24
Peak memory 265424 kb
Host smart-806ea9aa-b397-4e9b-b03d-f4fe7b73e582
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3683485829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3683485829
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2848033342
Short name T116
Test name
Test status
Simulation time 3680183888 ps
CPU time 371.07 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 05:05:47 PM PDT 24
Peak memory 265396 kb
Host smart-d6e6face-9159-4092-88c7-108733e773ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848033342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2848033342
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3090348562
Short name T704
Test name
Test status
Simulation time 182607311 ps
CPU time 11.87 seconds
Started Jun 28 04:59:35 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 252592 kb
Host smart-8c0cb0c6-1e50-40d9-a155-552b44a23b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3090348562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3090348562
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2734944854
Short name T780
Test name
Test status
Simulation time 4054211272 ps
CPU time 147.44 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 05:01:41 PM PDT 24
Peak memory 241808 kb
Host smart-47465517-23ba-4e0a-941a-dc24277d6add
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2734944854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2734944854
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2412732131
Short name T798
Test name
Test status
Simulation time 16465695727 ps
CPU time 262.82 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 05:03:41 PM PDT 24
Peak memory 237496 kb
Host smart-22d89e57-400a-4161-8606-a29b3f800079
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2412732131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2412732131
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.478344844
Short name T732
Test name
Test status
Simulation time 22415685 ps
CPU time 3.96 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 04:59:19 PM PDT 24
Peak memory 248700 kb
Host smart-77354acc-781b-46cc-9e26-c5d6b40b0d16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=478344844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.478344844
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1841732340
Short name T758
Test name
Test status
Simulation time 76910489 ps
CPU time 7.18 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 04:59:26 PM PDT 24
Peak memory 239644 kb
Host smart-0a65e847-8743-4916-9e2e-b0c7a94c81ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841732340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1841732340
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1332310789
Short name T796
Test name
Test status
Simulation time 33588880 ps
CPU time 3.2 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 04:59:20 PM PDT 24
Peak memory 236636 kb
Host smart-38f9b646-36c8-4ae5-89b4-af82f745ec9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1332310789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1332310789
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2664419655
Short name T741
Test name
Test status
Simulation time 8437624 ps
CPU time 1.38 seconds
Started Jun 28 04:59:16 PM PDT 24
Finished Jun 28 04:59:19 PM PDT 24
Peak memory 236660 kb
Host smart-6d087f78-18ae-4f66-beb5-641e4ac7beca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664419655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2664419655
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2313550515
Short name T178
Test name
Test status
Simulation time 1004067800 ps
CPU time 21.14 seconds
Started Jun 28 04:59:19 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 245708 kb
Host smart-ca7885aa-9452-4872-8e2d-28a761797ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2313550515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2313550515
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2746795265
Short name T134
Test name
Test status
Simulation time 5712281280 ps
CPU time 197.81 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 05:02:33 PM PDT 24
Peak memory 265636 kb
Host smart-2967ecee-feec-4f6a-8717-59275072db0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2746795265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2746795265
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.6024926
Short name T136
Test name
Test status
Simulation time 2258246600 ps
CPU time 308.53 seconds
Started Jun 28 04:59:15 PM PDT 24
Finished Jun 28 05:04:24 PM PDT 24
Peak memory 265652 kb
Host smart-5d362c0c-497b-4814-b47d-d9f8eb29b1ae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6024926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_shadow_reg_errors_with_csr_rw.6024926
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1039023849
Short name T700
Test name
Test status
Simulation time 346322526 ps
CPU time 25.68 seconds
Started Jun 28 04:59:18 PM PDT 24
Finished Jun 28 04:59:44 PM PDT 24
Peak memory 253512 kb
Host smart-5ccd6b23-e574-447e-b3bb-8330f6565d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1039023849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1039023849
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3978145780
Short name T745
Test name
Test status
Simulation time 12418803 ps
CPU time 1.33 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 237604 kb
Host smart-325240bd-3afd-4b50-8a27-576c5401f306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3978145780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3978145780
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2427330827
Short name T237
Test name
Test status
Simulation time 12106024 ps
CPU time 1.48 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 237608 kb
Host smart-0764e65a-4838-47f7-8799-18f644b95952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2427330827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2427330827
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4112355435
Short name T809
Test name
Test status
Simulation time 11421582 ps
CPU time 1.3 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 237612 kb
Host smart-b5825036-9842-4c7a-841b-dc19ae47d09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4112355435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4112355435
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.748866665
Short name T807
Test name
Test status
Simulation time 6257574 ps
CPU time 1.43 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 236568 kb
Host smart-2baf1bb6-87be-46b2-91a0-3e2e1adff4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=748866665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.748866665
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.627189908
Short name T748
Test name
Test status
Simulation time 11188167 ps
CPU time 1.32 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 235768 kb
Host smart-54e16118-e4a9-491a-b8ba-24203f94e222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=627189908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.627189908
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2004250332
Short name T737
Test name
Test status
Simulation time 9629444 ps
CPU time 1.33 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237604 kb
Host smart-badcde44-0611-4916-b8ec-8bbdeede4748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2004250332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2004250332
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3037455889
Short name T776
Test name
Test status
Simulation time 7478505 ps
CPU time 1.32 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 236672 kb
Host smart-811f8381-fc30-47ea-ab59-bfdddd328983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3037455889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3037455889
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2421406418
Short name T760
Test name
Test status
Simulation time 8067981 ps
CPU time 1.4 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 237612 kb
Host smart-30530164-6d70-47f2-badb-15a20fe315fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2421406418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2421406418
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.410997580
Short name T769
Test name
Test status
Simulation time 11495786 ps
CPU time 1.35 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237604 kb
Host smart-1866bacc-21c3-4229-a7f3-4f407ecce38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410997580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.410997580
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3905371426
Short name T815
Test name
Test status
Simulation time 9289067 ps
CPU time 1.31 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 236660 kb
Host smart-2a490743-423d-4e80-a263-506f325f811e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3905371426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3905371426
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3081270308
Short name T781
Test name
Test status
Simulation time 568402021 ps
CPU time 66.76 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 05:00:34 PM PDT 24
Peak memory 237636 kb
Host smart-92666fd0-0fb0-4cb4-8a84-03515d87e782
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3081270308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3081270308
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3279075250
Short name T792
Test name
Test status
Simulation time 22778687374 ps
CPU time 364.51 seconds
Started Jun 28 04:59:29 PM PDT 24
Finished Jun 28 05:05:35 PM PDT 24
Peak memory 236684 kb
Host smart-dd455e27-a0ba-4d2f-b930-1822c8c9b04f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3279075250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3279075250
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3895543667
Short name T771
Test name
Test status
Simulation time 123165388 ps
CPU time 10.74 seconds
Started Jun 28 04:59:14 PM PDT 24
Finished Jun 28 04:59:26 PM PDT 24
Peak memory 248748 kb
Host smart-e5587339-6d5c-4c30-9926-e343189eeae5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3895543667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3895543667
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3181455258
Short name T716
Test name
Test status
Simulation time 69671114 ps
CPU time 8.7 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:39 PM PDT 24
Peak memory 253016 kb
Host smart-9edf1021-c8a8-4161-a1ee-fcefe80ee85d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181455258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3181455258
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1795503986
Short name T725
Test name
Test status
Simulation time 50444867 ps
CPU time 4.83 seconds
Started Jun 28 04:59:17 PM PDT 24
Finished Jun 28 04:59:23 PM PDT 24
Peak memory 237588 kb
Host smart-ffcf8832-32f0-43f3-854a-dae33d24dce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1795503986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1795503986
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1262550494
Short name T801
Test name
Test status
Simulation time 8265369 ps
CPU time 1.49 seconds
Started Jun 28 04:59:17 PM PDT 24
Finished Jun 28 04:59:19 PM PDT 24
Peak memory 237572 kb
Host smart-55e839ed-c2ab-4230-bf30-f8f99a12058a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1262550494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1262550494
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1607333824
Short name T175
Test name
Test status
Simulation time 2298854598 ps
CPU time 23.98 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:51 PM PDT 24
Peak memory 245844 kb
Host smart-e5b4e1af-3ac3-4c51-a0ec-682cf9ab4f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1607333824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1607333824
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4196316120
Short name T706
Test name
Test status
Simulation time 248926656 ps
CPU time 17.99 seconds
Started Jun 28 04:59:19 PM PDT 24
Finished Jun 28 04:59:37 PM PDT 24
Peak memory 252216 kb
Host smart-95f63d76-a745-4e6d-b131-9fe5f0c81ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4196316120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4196316120
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1032686197
Short name T742
Test name
Test status
Simulation time 21678655 ps
CPU time 1.45 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 237604 kb
Host smart-74ed1019-7217-4c11-940c-f67e0618634a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1032686197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1032686197
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3671981822
Short name T339
Test name
Test status
Simulation time 32428250 ps
CPU time 1.35 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 237604 kb
Host smart-a0bcb7b0-ff5d-4de5-b80c-2cc4f7e0f7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3671981822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3671981822
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3396086072
Short name T752
Test name
Test status
Simulation time 7936368 ps
CPU time 1.45 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 237512 kb
Host smart-ac2bda28-1268-48d1-98ea-b18566d33718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3396086072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3396086072
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1370548111
Short name T738
Test name
Test status
Simulation time 9834855 ps
CPU time 1.66 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 236660 kb
Host smart-be298a80-b2c1-45f8-ad8c-48d178e14808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1370548111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1370548111
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1045306805
Short name T346
Test name
Test status
Simulation time 7398156 ps
CPU time 1.34 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237604 kb
Host smart-11613c9e-966e-4eaa-b56e-ab92a205937d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1045306805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1045306805
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2639647613
Short name T143
Test name
Test status
Simulation time 23665183 ps
CPU time 1.42 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 236616 kb
Host smart-18fbf350-67e4-4c54-a08e-5d785631e067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2639647613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2639647613
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2996804907
Short name T765
Test name
Test status
Simulation time 8607683 ps
CPU time 1.41 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 236660 kb
Host smart-2d75f1a4-ee0f-4540-a639-b4de01c2b418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2996804907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2996804907
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3817706515
Short name T764
Test name
Test status
Simulation time 10625621 ps
CPU time 1.44 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237628 kb
Host smart-af7b80a3-70a1-46c2-9fca-e8a36a24c023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3817706515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3817706515
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.21370176
Short name T757
Test name
Test status
Simulation time 74752450 ps
CPU time 1.39 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 236544 kb
Host smart-c9e6f1b7-5048-4e17-a109-870d8b9b142d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=21370176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.21370176
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.680098112
Short name T775
Test name
Test status
Simulation time 5129343591 ps
CPU time 53.47 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 05:00:19 PM PDT 24
Peak memory 237704 kb
Host smart-77a3f228-cb81-4433-87de-eb015fd15afa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=680098112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.680098112
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.778991617
Short name T735
Test name
Test status
Simulation time 4285798331 ps
CPU time 277.39 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 05:04:04 PM PDT 24
Peak memory 237656 kb
Host smart-2bc9ec3e-54c9-4727-b0b8-530ae020620d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=778991617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.778991617
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.838362713
Short name T795
Test name
Test status
Simulation time 198432090 ps
CPU time 8.92 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 240544 kb
Host smart-e8b2e48f-10af-4617-85e1-81e30850b426
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=838362713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.838362713
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3694139040
Short name T713
Test name
Test status
Simulation time 2048544155 ps
CPU time 12.44 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 251880 kb
Host smart-9f0b5be2-1c45-4641-a5c9-b70c25981e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694139040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3694139040
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2072500641
Short name T824
Test name
Test status
Simulation time 205105661 ps
CPU time 4.85 seconds
Started Jun 28 04:59:29 PM PDT 24
Finished Jun 28 04:59:36 PM PDT 24
Peak memory 236632 kb
Host smart-b269459d-b0fc-4c0b-b1d5-b945bfe3796b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2072500641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2072500641
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4213501236
Short name T805
Test name
Test status
Simulation time 15160791 ps
CPU time 1.48 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 04:59:30 PM PDT 24
Peak memory 236672 kb
Host smart-d717d09f-51d6-4dd8-a900-5657dc8012ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213501236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4213501236
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.580149877
Short name T813
Test name
Test status
Simulation time 2536012130 ps
CPU time 18.67 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 245844 kb
Host smart-ddd7da43-dbd6-4ac8-a14a-4a2ab980c794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=580149877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.580149877
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1347075725
Short name T351
Test name
Test status
Simulation time 24646693337 ps
CPU time 503.03 seconds
Started Jun 28 04:59:23 PM PDT 24
Finished Jun 28 05:07:47 PM PDT 24
Peak memory 265580 kb
Host smart-bd1772fb-1584-494d-ad02-84956e3674b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347075725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1347075725
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1901730882
Short name T770
Test name
Test status
Simulation time 83342775 ps
CPU time 10.76 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 248808 kb
Host smart-7c9559f1-607c-4ec0-8d91-c20feb67068e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1901730882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1901730882
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4175650079
Short name T190
Test name
Test status
Simulation time 52241531 ps
CPU time 3.56 seconds
Started Jun 28 04:59:30 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 237572 kb
Host smart-d4f909d2-1bdc-4b76-9d7e-0501c53afb14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4175650079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4175650079
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2755090349
Short name T743
Test name
Test status
Simulation time 7846775 ps
CPU time 1.43 seconds
Started Jun 28 04:59:48 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 235444 kb
Host smart-eba0f893-d23f-4bb1-8c4e-d72a6d098dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2755090349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2755090349
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3309471481
Short name T802
Test name
Test status
Simulation time 23119481 ps
CPU time 1.37 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 237604 kb
Host smart-26306ebf-a75d-4b19-ad74-c685ceec61cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3309471481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3309471481
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.447059657
Short name T773
Test name
Test status
Simulation time 11518508 ps
CPU time 1.31 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 236628 kb
Host smart-e4f75a69-e79c-4e77-a07f-afda9f8fb21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=447059657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.447059657
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2208196184
Short name T344
Test name
Test status
Simulation time 19450254 ps
CPU time 1.39 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 237604 kb
Host smart-92c255b4-2a13-420f-a5a5-dc8855fb4c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2208196184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2208196184
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1446834363
Short name T756
Test name
Test status
Simulation time 16613386 ps
CPU time 1.83 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 237540 kb
Host smart-9750f763-74ff-4cee-8376-52ac9a9253c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1446834363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1446834363
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.188812559
Short name T340
Test name
Test status
Simulation time 10689591 ps
CPU time 1.32 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 236736 kb
Host smart-29e383e7-3b4d-41e9-8306-cf5ae62df835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=188812559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.188812559
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1506976077
Short name T777
Test name
Test status
Simulation time 42624174 ps
CPU time 1.47 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 236728 kb
Host smart-56d86c41-ef3f-49f8-8732-e3704d8c369d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1506976077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1506976077
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2722333679
Short name T787
Test name
Test status
Simulation time 8274856 ps
CPU time 1.59 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 237628 kb
Host smart-40347669-2943-45a0-8964-d9df45577f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2722333679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2722333679
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3375560338
Short name T746
Test name
Test status
Simulation time 71362352 ps
CPU time 1.45 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:47 PM PDT 24
Peak memory 237436 kb
Host smart-e9d468cf-e554-4552-963d-0fa0c60b8dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3375560338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3375560338
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2202271534
Short name T343
Test name
Test status
Simulation time 8666939 ps
CPU time 1.58 seconds
Started Jun 28 04:59:46 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 237508 kb
Host smart-f2f368cd-20bc-4726-8768-c8163a2a5e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202271534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2202271534
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1014737701
Short name T720
Test name
Test status
Simulation time 73031957 ps
CPU time 5.57 seconds
Started Jun 28 04:59:24 PM PDT 24
Finished Jun 28 04:59:30 PM PDT 24
Peak memory 240596 kb
Host smart-54c77dc0-a46e-405c-9925-6113b393c08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014737701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1014737701
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3389443319
Short name T819
Test name
Test status
Simulation time 174710614 ps
CPU time 3.09 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 04:59:29 PM PDT 24
Peak memory 236444 kb
Host smart-dafc88f7-43ac-433e-a848-4f795808798b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3389443319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3389443319
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1346142339
Short name T755
Test name
Test status
Simulation time 8813759 ps
CPU time 1.63 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:29 PM PDT 24
Peak memory 236740 kb
Host smart-ab97fbc0-93cf-4c1a-93d2-4489f8308166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346142339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1346142339
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.404245874
Short name T782
Test name
Test status
Simulation time 490635763 ps
CPU time 36.93 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 05:00:04 PM PDT 24
Peak memory 245812 kb
Host smart-d7ee1add-6483-4364-8c46-2bb550bb8af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=404245874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.404245874
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4256780736
Short name T705
Test name
Test status
Simulation time 292271623 ps
CPU time 18.39 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:46 PM PDT 24
Peak memory 248524 kb
Host smart-9640feb6-5d3e-4a95-ac4d-2f38379bccf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4256780736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4256780736
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2591525638
Short name T808
Test name
Test status
Simulation time 148507836 ps
CPU time 13.02 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 04:59:42 PM PDT 24
Peak memory 248728 kb
Host smart-299e25d1-0af5-4627-87cd-98e3501fe1c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591525638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2591525638
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3289857181
Short name T779
Test name
Test status
Simulation time 97477695 ps
CPU time 5.25 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 237596 kb
Host smart-9fe1ee37-1a4f-4f76-8ffb-2806392ebb59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3289857181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3289857181
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1699302670
Short name T804
Test name
Test status
Simulation time 24005773 ps
CPU time 1.36 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:31 PM PDT 24
Peak memory 237432 kb
Host smart-693eb1a4-8454-443b-b32d-ab43eb81a0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1699302670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1699302670
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1741168528
Short name T707
Test name
Test status
Simulation time 2186808516 ps
CPU time 32.86 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:00:03 PM PDT 24
Peak memory 244740 kb
Host smart-33c4c80b-4b20-4384-84ca-508556ef0ded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1741168528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1741168528
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1102943312
Short name T115
Test name
Test status
Simulation time 2273825286 ps
CPU time 154.33 seconds
Started Jun 28 04:59:25 PM PDT 24
Finished Jun 28 05:02:00 PM PDT 24
Peak memory 265464 kb
Host smart-2d4d30e8-a444-4a98-a3ea-0d8d6f5668a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1102943312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1102943312
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3758551256
Short name T111
Test name
Test status
Simulation time 4463497496 ps
CPU time 345.26 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 05:05:15 PM PDT 24
Peak memory 265432 kb
Host smart-b84f3b9e-6b98-4ee2-8d2a-4c986e9e32fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758551256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3758551256
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2247339613
Short name T784
Test name
Test status
Simulation time 220666127 ps
CPU time 14 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 04:59:43 PM PDT 24
Peak memory 254588 kb
Host smart-dad96060-6313-407b-a978-b287c0ed620d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2247339613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2247339613
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.464101364
Short name T270
Test name
Test status
Simulation time 199994343 ps
CPU time 24.65 seconds
Started Jun 28 04:59:24 PM PDT 24
Finished Jun 28 04:59:49 PM PDT 24
Peak memory 240420 kb
Host smart-a6d6bd2a-c1dd-496d-89a3-20032e627225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=464101364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.464101364
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2944582601
Short name T759
Test name
Test status
Simulation time 258828994 ps
CPU time 5.39 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:33 PM PDT 24
Peak memory 241512 kb
Host smart-77180f42-0284-4dda-af03-3e54d8d0a222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944582601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2944582601
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.372803377
Short name T817
Test name
Test status
Simulation time 47227228 ps
CPU time 3.69 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:34 PM PDT 24
Peak memory 237416 kb
Host smart-f470a638-0667-41a4-aa45-10a33dc4ce41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=372803377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.372803377
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2786271908
Short name T816
Test name
Test status
Simulation time 26180689 ps
CPU time 1.55 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:30 PM PDT 24
Peak memory 237580 kb
Host smart-9fe864dd-469f-4280-84d3-084c7ab7bc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786271908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2786271908
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3435362597
Short name T814
Test name
Test status
Simulation time 242452718 ps
CPU time 18.35 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 245804 kb
Host smart-ed5e54fd-1332-470a-979c-af5c49982637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3435362597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3435362597
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4237432021
Short name T119
Test name
Test status
Simulation time 12889516757 ps
CPU time 992.06 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 05:16:02 PM PDT 24
Peak memory 265420 kb
Host smart-19f698ef-cf03-4499-9885-3038b32c7080
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237432021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4237432021
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.270547903
Short name T818
Test name
Test status
Simulation time 692175115 ps
CPU time 10.34 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:40 PM PDT 24
Peak memory 252928 kb
Host smart-fb4c4448-9b53-46c3-bc41-b7caef4dfb9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270547903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.270547903
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1679632455
Short name T785
Test name
Test status
Simulation time 32368861 ps
CPU time 5.9 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:35 PM PDT 24
Peak memory 248700 kb
Host smart-4453813a-3f6e-408e-930a-e7f1e10279cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679632455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1679632455
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2529047569
Short name T717
Test name
Test status
Simulation time 142045366 ps
CPU time 11.03 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:39 PM PDT 24
Peak memory 240540 kb
Host smart-9d079ea8-e07f-4553-98d9-24a0052729aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2529047569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2529047569
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2697514047
Short name T788
Test name
Test status
Simulation time 15514316 ps
CPU time 1.36 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 04:59:28 PM PDT 24
Peak memory 235720 kb
Host smart-c6fb23aa-37de-46be-8e29-183bc2d15d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2697514047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2697514047
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.35879814
Short name T778
Test name
Test status
Simulation time 633312259 ps
CPU time 23.3 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:54 PM PDT 24
Peak memory 245780 kb
Host smart-7107d5da-5462-4fb5-8437-4dabeccd6774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=35879814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outst
anding.35879814
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.180233923
Short name T129
Test name
Test status
Simulation time 6726889165 ps
CPU time 97.66 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 05:01:05 PM PDT 24
Peak memory 265296 kb
Host smart-7ec61518-8cd0-4e3f-b683-aeb2466e19d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=180233923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.180233923
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2402241950
Short name T137
Test name
Test status
Simulation time 17382277087 ps
CPU time 642.44 seconds
Started Jun 28 04:59:27 PM PDT 24
Finished Jun 28 05:10:11 PM PDT 24
Peak memory 265352 kb
Host smart-ab3a4b99-136a-4853-b394-72a19a5f0957
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402241950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2402241950
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.902237780
Short name T722
Test name
Test status
Simulation time 95081904 ps
CPU time 12.18 seconds
Started Jun 28 04:59:24 PM PDT 24
Finished Jun 28 04:59:37 PM PDT 24
Peak memory 254772 kb
Host smart-d307b94a-bcf8-4134-98ee-3ae2dc812875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=902237780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.902237780
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3022400626
Short name T733
Test name
Test status
Simulation time 1044635553 ps
CPU time 9.03 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:39 PM PDT 24
Peak memory 252288 kb
Host smart-6cd1c435-217d-4b64-a453-d269a439d565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022400626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3022400626
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2020482040
Short name T763
Test name
Test status
Simulation time 96499196 ps
CPU time 7.61 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:38 PM PDT 24
Peak memory 236636 kb
Host smart-8ba20cd9-3dc3-4ea6-a436-83fc965e9dde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2020482040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2020482040
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1479271433
Short name T142
Test name
Test status
Simulation time 7783583 ps
CPU time 1.36 seconds
Started Jun 28 04:59:32 PM PDT 24
Finished Jun 28 04:59:34 PM PDT 24
Peak memory 235648 kb
Host smart-9e5e7a61-9081-40be-8b23-b3932d9f10a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1479271433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1479271433
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.830937509
Short name T739
Test name
Test status
Simulation time 264841850 ps
CPU time 21.2 seconds
Started Jun 28 04:59:31 PM PDT 24
Finished Jun 28 04:59:53 PM PDT 24
Peak memory 245804 kb
Host smart-18106596-f1e1-4660-a110-cce2bd6ba610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=830937509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.830937509
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2948208051
Short name T349
Test name
Test status
Simulation time 35693670764 ps
CPU time 506.76 seconds
Started Jun 28 04:59:26 PM PDT 24
Finished Jun 28 05:07:54 PM PDT 24
Peak memory 269224 kb
Host smart-13ee17a3-e455-4bbc-a7ad-e2aad435181f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948208051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2948208051
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2898389521
Short name T786
Test name
Test status
Simulation time 1178570458 ps
CPU time 19.54 seconds
Started Jun 28 04:59:28 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 248884 kb
Host smart-cb5cfbe5-97ac-408d-9422-8f2016fb9a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2898389521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2898389521
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3001789992
Short name T626
Test name
Test status
Simulation time 54456203579 ps
CPU time 1568.68 seconds
Started Jun 28 05:19:15 PM PDT 24
Finished Jun 28 05:45:25 PM PDT 24
Peak memory 273768 kb
Host smart-44a5e39c-523c-4586-bd2a-5fb4da67bd8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001789992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3001789992
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3136281468
Short name T573
Test name
Test status
Simulation time 3909313701 ps
CPU time 15.48 seconds
Started Jun 28 05:19:15 PM PDT 24
Finished Jun 28 05:19:32 PM PDT 24
Peak memory 249300 kb
Host smart-fd97c63d-5535-49f6-b056-240c2589aa48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3136281468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3136281468
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3872205821
Short name T421
Test name
Test status
Simulation time 456946287 ps
CPU time 35.65 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:51 PM PDT 24
Peak memory 256816 kb
Host smart-e02bc025-bca6-4fb3-ba27-ad6cdd5eb01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38722
05821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3872205821
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2271669969
Short name T356
Test name
Test status
Simulation time 166730348 ps
CPU time 6.26 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:22 PM PDT 24
Peak memory 249020 kb
Host smart-1aee9354-0692-43e9-bd5a-f7daa739e991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22716
69969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2271669969
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2351704476
Short name T325
Test name
Test status
Simulation time 75627567502 ps
CPU time 2166.64 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:55:23 PM PDT 24
Peak memory 289912 kb
Host smart-fe6cf985-1f5e-4014-b34c-63ff7df12dc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351704476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2351704476
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4209941797
Short name T585
Test name
Test status
Simulation time 29998306235 ps
CPU time 620.47 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 273144 kb
Host smart-a27dce95-d2d0-4015-875b-353583025c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209941797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4209941797
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4069817085
Short name T617
Test name
Test status
Simulation time 7457053855 ps
CPU time 308.36 seconds
Started Jun 28 05:19:12 PM PDT 24
Finished Jun 28 05:24:23 PM PDT 24
Peak memory 249388 kb
Host smart-f2c68239-76d0-4fe4-a066-3a4830ca7da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069817085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4069817085
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3837743909
Short name T369
Test name
Test status
Simulation time 204363957 ps
CPU time 10.64 seconds
Started Jun 28 05:19:18 PM PDT 24
Finished Jun 28 05:19:29 PM PDT 24
Peak memory 255712 kb
Host smart-c7801111-82b2-45e2-ad45-7b6e10d0d067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377
43909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3837743909
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2860829657
Short name T23
Test name
Test status
Simulation time 1615813699 ps
CPU time 47.85 seconds
Started Jun 28 05:19:12 PM PDT 24
Finished Jun 28 05:20:03 PM PDT 24
Peak memory 256984 kb
Host smart-84e3fc1a-5356-4ff6-8971-340c1a39d256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28608
29657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2860829657
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3229428064
Short name T12
Test name
Test status
Simulation time 1725977534 ps
CPU time 22.86 seconds
Started Jun 28 05:19:11 PM PDT 24
Finished Jun 28 05:19:34 PM PDT 24
Peak memory 279132 kb
Host smart-0614a3e1-c5a7-4cf3-84bd-9ae3a1098a97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3229428064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3229428064
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3744024520
Short name T262
Test name
Test status
Simulation time 3698247842 ps
CPU time 55.06 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:20:11 PM PDT 24
Peak memory 249968 kb
Host smart-1aaa15a6-43f5-425b-9100-bf789c334604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37440
24520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3744024520
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2377376856
Short name T171
Test name
Test status
Simulation time 482003191 ps
CPU time 33.73 seconds
Started Jun 28 05:19:18 PM PDT 24
Finished Jun 28 05:19:52 PM PDT 24
Peak memory 257440 kb
Host smart-6a84bd8e-ac9c-4a76-9e98-e52dec7e314c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
76856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2377376856
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.650503092
Short name T497
Test name
Test status
Simulation time 19202635299 ps
CPU time 1121.53 seconds
Started Jun 28 05:19:18 PM PDT 24
Finished Jun 28 05:38:00 PM PDT 24
Peak memory 274008 kb
Host smart-f1ac79bc-3137-4882-b8e0-50e0b700f656
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650503092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.650503092
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3882488566
Short name T277
Test name
Test status
Simulation time 1834824319 ps
CPU time 167.81 seconds
Started Jun 28 05:19:15 PM PDT 24
Finished Jun 28 05:22:05 PM PDT 24
Peak memory 256956 kb
Host smart-8171caba-e77d-44af-b4d2-b0eb01bbdf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38824
88566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3882488566
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3076785180
Short name T442
Test name
Test status
Simulation time 199275272 ps
CPU time 15.5 seconds
Started Jun 28 05:19:17 PM PDT 24
Finished Jun 28 05:19:33 PM PDT 24
Peak memory 249808 kb
Host smart-067be44e-c120-414f-9153-b5a5cb9449ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
85180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3076785180
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1178300482
Short name T292
Test name
Test status
Simulation time 118328862940 ps
CPU time 1522.41 seconds
Started Jun 28 05:19:15 PM PDT 24
Finished Jun 28 05:44:39 PM PDT 24
Peak memory 289880 kb
Host smart-38db9bb4-7eeb-41e8-bc4c-93e23e22d3b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178300482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1178300482
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3669659848
Short name T434
Test name
Test status
Simulation time 543778120327 ps
CPU time 1821.05 seconds
Started Jun 28 05:19:18 PM PDT 24
Finished Jun 28 05:49:40 PM PDT 24
Peak memory 283548 kb
Host smart-6459757a-ad6d-4fc8-b11d-0fa67daf643c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669659848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3669659848
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4015018524
Short name T302
Test name
Test status
Simulation time 7339692789 ps
CPU time 188.05 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:22:24 PM PDT 24
Peak memory 249304 kb
Host smart-9db9f406-7ed3-4cac-acab-03ebddb3fb49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015018524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4015018524
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2428938080
Short name T363
Test name
Test status
Simulation time 294124259 ps
CPU time 7.12 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:22 PM PDT 24
Peak memory 249416 kb
Host smart-3c6ae1cd-8871-4280-90e4-8144a040f444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24289
38080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2428938080
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.498403682
Short name T427
Test name
Test status
Simulation time 234905244 ps
CPU time 9.62 seconds
Started Jun 28 05:19:17 PM PDT 24
Finished Jun 28 05:19:28 PM PDT 24
Peak memory 248800 kb
Host smart-0caefb6e-93d4-4711-8257-d775f43244e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49840
3682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.498403682
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3309956295
Short name T11
Test name
Test status
Simulation time 648183616 ps
CPU time 33.21 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:48 PM PDT 24
Peak memory 271180 kb
Host smart-5937b06e-451a-4f9b-bb6f-334a0f4118b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3309956295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3309956295
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3558914903
Short name T283
Test name
Test status
Simulation time 999889380 ps
CPU time 55.17 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:20:12 PM PDT 24
Peak memory 256812 kb
Host smart-233084f1-e4dc-4012-af55-52033b535f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
14903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3558914903
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1448955366
Short name T418
Test name
Test status
Simulation time 1163083884 ps
CPU time 36.24 seconds
Started Jun 28 05:19:12 PM PDT 24
Finished Jun 28 05:19:49 PM PDT 24
Peak memory 257432 kb
Host smart-b182c513-3e09-49e5-960f-2d1271e43584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
55366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1448955366
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3071865965
Short name T675
Test name
Test status
Simulation time 49908530805 ps
CPU time 1513.05 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:44:29 PM PDT 24
Peak memory 273796 kb
Host smart-61a7c3c6-2cc9-499d-981d-70f76491c64e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071865965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3071865965
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3577645407
Short name T204
Test name
Test status
Simulation time 57005269 ps
CPU time 3.44 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:19:55 PM PDT 24
Peak memory 249516 kb
Host smart-de5f31ad-2451-47d9-9d2c-e90a074b7770
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3577645407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3577645407
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3113668321
Short name T557
Test name
Test status
Simulation time 18195570187 ps
CPU time 1463.32 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:44:00 PM PDT 24
Peak memory 290004 kb
Host smart-514f11df-aec5-42d0-97e1-b72a1d32db89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113668321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3113668321
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3957760603
Short name T408
Test name
Test status
Simulation time 875003727 ps
CPU time 39.66 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:20:19 PM PDT 24
Peak memory 248456 kb
Host smart-1f32acbe-853e-4f34-bee7-60d23284f9da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3957760603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3957760603
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4211166484
Short name T604
Test name
Test status
Simulation time 3170529252 ps
CPU time 65.69 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:20:47 PM PDT 24
Peak memory 256584 kb
Host smart-cf249bc9-15e5-4d58-91e5-b23372357a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
66484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4211166484
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.42400992
Short name T387
Test name
Test status
Simulation time 823042797 ps
CPU time 49.02 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:20:30 PM PDT 24
Peak memory 248796 kb
Host smart-e40619a4-ca52-4729-8bfc-662ac43f2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.42400992
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3237362980
Short name T504
Test name
Test status
Simulation time 4220209315 ps
CPU time 177.37 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:22:36 PM PDT 24
Peak memory 254944 kb
Host smart-b912fec2-a202-4b78-9926-6adceac091bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237362980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3237362980
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3960526022
Short name T402
Test name
Test status
Simulation time 984800932 ps
CPU time 15.8 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:19:57 PM PDT 24
Peak memory 249152 kb
Host smart-b3c0c3be-18e8-4e2c-9ba7-b3be10efab61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
26022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3960526022
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1003067497
Short name T228
Test name
Test status
Simulation time 2166861136 ps
CPU time 15.63 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:19:55 PM PDT 24
Peak memory 248680 kb
Host smart-94a055fe-82c2-48d4-879a-28e6676cd0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10030
67497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1003067497
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4107768409
Short name T2
Test name
Test status
Simulation time 915585437 ps
CPU time 11.85 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:19:49 PM PDT 24
Peak memory 249304 kb
Host smart-936b5d20-4797-40a6-8258-83fc5391c653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41077
68409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4107768409
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4185788946
Short name T218
Test name
Test status
Simulation time 3052767431 ps
CPU time 32.36 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:20:11 PM PDT 24
Peak memory 256672 kb
Host smart-b73b8ccd-bdc5-4143-8155-6c5cd3b268ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41857
88946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4185788946
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1875275095
Short name T691
Test name
Test status
Simulation time 8333134005 ps
CPU time 374.51 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:25:55 PM PDT 24
Peak memory 265732 kb
Host smart-0e27e153-a7b9-4c3b-8dbf-93dec7697072
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875275095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1875275095
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3708269110
Short name T45
Test name
Test status
Simulation time 13629201519 ps
CPU time 1344.89 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:42:15 PM PDT 24
Peak memory 289408 kb
Host smart-1710212c-ec47-485a-8b9f-ba1bc9967e86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708269110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3708269110
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.247892295
Short name T586
Test name
Test status
Simulation time 717493175 ps
CPU time 30.63 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:20:23 PM PDT 24
Peak memory 249304 kb
Host smart-0f69db7b-44eb-4fed-b6c4-07dce4f4e2b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=247892295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.247892295
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1041816440
Short name T475
Test name
Test status
Simulation time 840979480 ps
CPU time 34.06 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:20:26 PM PDT 24
Peak memory 249228 kb
Host smart-f4b19655-658d-4edc-8452-369efcbb2fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
16440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1041816440
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1237836857
Short name T331
Test name
Test status
Simulation time 167012056253 ps
CPU time 2549.88 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 06:02:19 PM PDT 24
Peak memory 290384 kb
Host smart-03c4fce4-5438-489f-aa2d-cb418c6a27f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237836857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1237836857
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.321729250
Short name T78
Test name
Test status
Simulation time 134054003292 ps
CPU time 1171.96 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:39:22 PM PDT 24
Peak memory 285452 kb
Host smart-25b9f426-3cb9-4c3f-b86f-473f444c7c9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321729250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.321729250
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1432969368
Short name T396
Test name
Test status
Simulation time 127466997 ps
CPU time 11.63 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:02 PM PDT 24
Peak memory 255820 kb
Host smart-ed6883d6-31d8-41c5-943d-9dd6f8d1bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14329
69368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1432969368
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1011388126
Short name T355
Test name
Test status
Simulation time 365746162 ps
CPU time 7.41 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:19:58 PM PDT 24
Peak memory 249300 kb
Host smart-fdd313d0-5627-4cdf-9cce-5dd6cbd90a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10113
88126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1011388126
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3175912864
Short name T394
Test name
Test status
Simulation time 995843814 ps
CPU time 19.13 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:20:10 PM PDT 24
Peak memory 248528 kb
Host smart-4e28f29d-5f54-4b1f-88ac-b270964c0305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
12864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3175912864
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4020738334
Short name T467
Test name
Test status
Simulation time 925061960 ps
CPU time 28.75 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:22 PM PDT 24
Peak memory 256360 kb
Host smart-a6c6ff51-579f-43b4-87b3-3cda23d8c678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
38334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4020738334
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3414419554
Short name T453
Test name
Test status
Simulation time 37572373976 ps
CPU time 807.44 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:33:20 PM PDT 24
Peak memory 269812 kb
Host smart-c40957a1-1b14-447c-959a-c2c16861525d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414419554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3414419554
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1699080561
Short name T526
Test name
Test status
Simulation time 1800499191 ps
CPU time 41.01 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:31 PM PDT 24
Peak memory 249444 kb
Host smart-954909ce-3f14-42f2-984c-d6ac170d86e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1699080561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1699080561
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3828253623
Short name T622
Test name
Test status
Simulation time 1373245164 ps
CPU time 117.84 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:21:51 PM PDT 24
Peak memory 256988 kb
Host smart-a74e26d5-24e4-466c-8ebf-97dc1ad23c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38282
53623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3828253623
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2060018847
Short name T465
Test name
Test status
Simulation time 250743252 ps
CPU time 10.9 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:04 PM PDT 24
Peak memory 249204 kb
Host smart-cede7be4-2e5d-44f1-842c-60dc14916f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
18847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2060018847
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.910608748
Short name T554
Test name
Test status
Simulation time 24319800459 ps
CPU time 1077.88 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:37:50 PM PDT 24
Peak memory 273676 kb
Host smart-c734095d-19bd-4048-9f39-81fe47a72f31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910608748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.910608748
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1338987669
Short name T610
Test name
Test status
Simulation time 143189861942 ps
CPU time 2380.57 seconds
Started Jun 28 05:19:53 PM PDT 24
Finished Jun 28 05:59:35 PM PDT 24
Peak memory 289444 kb
Host smart-d87b9825-ea02-4df8-9128-61d74d34a608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338987669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1338987669
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.4284899982
Short name T311
Test name
Test status
Simulation time 51006433693 ps
CPU time 557.82 seconds
Started Jun 28 05:19:48 PM PDT 24
Finished Jun 28 05:29:07 PM PDT 24
Peak memory 256112 kb
Host smart-47285916-6507-4224-84a5-681531263edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284899982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.4284899982
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2749676849
Short name T37
Test name
Test status
Simulation time 51722817 ps
CPU time 2.91 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:19:55 PM PDT 24
Peak memory 240948 kb
Host smart-f6bbc6d4-c540-4e08-97dc-ca8c348cb39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27496
76849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2749676849
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1146382232
Short name T236
Test name
Test status
Simulation time 2107863376 ps
CPU time 65.22 seconds
Started Jun 28 05:19:53 PM PDT 24
Finished Jun 28 05:20:59 PM PDT 24
Peak memory 256864 kb
Host smart-26408348-f146-47c8-a238-24c6ecffe52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
82232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1146382232
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2287150176
Short name T406
Test name
Test status
Simulation time 809925764 ps
CPU time 12.91 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:03 PM PDT 24
Peak memory 249276 kb
Host smart-d6c35b83-f96f-48cd-9d01-6b7c2cb1b585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
50176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2287150176
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.42576515
Short name T607
Test name
Test status
Simulation time 71294720525 ps
CPU time 1017.89 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:36:50 PM PDT 24
Peak memory 273728 kb
Host smart-6774cbf4-c624-4d87-a43d-80133cf2e9d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_hand
ler_stress_all.42576515
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3043663305
Short name T194
Test name
Test status
Simulation time 48063060 ps
CPU time 2.69 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:19:55 PM PDT 24
Peak memory 249544 kb
Host smart-3a2c1bf6-5e7b-4eb6-b218-d2ee8a2d6b8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3043663305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3043663305
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3086846199
Short name T619
Test name
Test status
Simulation time 313823864 ps
CPU time 15.46 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:09 PM PDT 24
Peak memory 249196 kb
Host smart-51d54971-ee39-4a2b-b673-11839dba6bd1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3086846199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3086846199
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1344088035
Short name T362
Test name
Test status
Simulation time 9798269016 ps
CPU time 243.63 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:23:57 PM PDT 24
Peak memory 257532 kb
Host smart-8c3af2b2-8f71-4756-aa82-0c0d62d3cb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
88035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1344088035
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1975845402
Short name T446
Test name
Test status
Simulation time 1291841168 ps
CPU time 39.32 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:32 PM PDT 24
Peak memory 249668 kb
Host smart-e5452775-74d8-4c18-bb2e-461ef8ae3357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
45402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1975845402
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4021642688
Short name T96
Test name
Test status
Simulation time 55895475105 ps
CPU time 1634.96 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:47:06 PM PDT 24
Peak memory 290112 kb
Host smart-72b0433e-5a23-4d05-9672-ef5449bbb80f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021642688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4021642688
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.237091405
Short name T473
Test name
Test status
Simulation time 8468716709 ps
CPU time 345.63 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:25:39 PM PDT 24
Peak memory 249352 kb
Host smart-1b0f484c-145e-4803-9e7f-16c30d0b8e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237091405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.237091405
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.349530554
Short name T441
Test name
Test status
Simulation time 2020027895 ps
CPU time 28.82 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:20:23 PM PDT 24
Peak memory 249224 kb
Host smart-c40bb36d-d0b6-4349-99a8-8a17fdd664d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34953
0554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.349530554
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2425693344
Short name T426
Test name
Test status
Simulation time 1364431901 ps
CPU time 23.19 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:16 PM PDT 24
Peak memory 248844 kb
Host smart-3ac1c34e-dce6-41f2-a842-8b1e4d873c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24256
93344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2425693344
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3027997186
Short name T268
Test name
Test status
Simulation time 2145013344 ps
CPU time 26.05 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:20:20 PM PDT 24
Peak memory 257204 kb
Host smart-2888f128-8c5c-4260-a5d2-7c0051aa69f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
97186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3027997186
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2376076577
Short name T380
Test name
Test status
Simulation time 1054595887 ps
CPU time 55.35 seconds
Started Jun 28 05:19:48 PM PDT 24
Finished Jun 28 05:20:44 PM PDT 24
Peak memory 257356 kb
Host smart-aa7e954f-5f60-42be-88eb-b36d6c9993d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
76577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2376076577
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4149293873
Short name T414
Test name
Test status
Simulation time 7193762482 ps
CPU time 186.43 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:23:00 PM PDT 24
Peak memory 257568 kb
Host smart-ef47f680-88e6-415e-8de0-c5b854c04a72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149293873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4149293873
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3928841810
Short name T160
Test name
Test status
Simulation time 231850405690 ps
CPU time 4892.81 seconds
Started Jun 28 05:19:53 PM PDT 24
Finished Jun 28 06:41:27 PM PDT 24
Peak memory 320152 kb
Host smart-b32f236a-1a2b-46ed-aeb6-3c5ea47fefcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928841810 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3928841810
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2302548341
Short name T199
Test name
Test status
Simulation time 103684162 ps
CPU time 3.2 seconds
Started Jun 28 05:19:56 PM PDT 24
Finished Jun 28 05:20:00 PM PDT 24
Peak memory 249528 kb
Host smart-81c5ceaa-1a81-4c83-9129-88c7f619a071
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2302548341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2302548341
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.231770814
Short name T532
Test name
Test status
Simulation time 133771894573 ps
CPU time 1848.13 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:50:39 PM PDT 24
Peak memory 282512 kb
Host smart-a175c4b7-bc77-4e01-a975-e6cce7d4acfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231770814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.231770814
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2268576212
Short name T399
Test name
Test status
Simulation time 941441453 ps
CPU time 19.29 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:10 PM PDT 24
Peak memory 249268 kb
Host smart-458badcf-e759-4c1d-a9f5-40a2f64c72eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2268576212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2268576212
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.917558502
Short name T449
Test name
Test status
Simulation time 18769903485 ps
CPU time 151.19 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:22:23 PM PDT 24
Peak memory 257532 kb
Host smart-a182e841-4f69-4246-8519-2e8b0f92cfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91755
8502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.917558502
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1210892085
Short name T3
Test name
Test status
Simulation time 621516958 ps
CPU time 15.44 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:05 PM PDT 24
Peak memory 255944 kb
Host smart-5ab74126-b6d3-4aef-ae7a-a8e382dd671b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12108
92085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1210892085
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4060207521
Short name T170
Test name
Test status
Simulation time 163960036308 ps
CPU time 2746.22 seconds
Started Jun 28 05:19:56 PM PDT 24
Finished Jun 28 06:05:43 PM PDT 24
Peak memory 282064 kb
Host smart-f290c40c-9bda-43fd-8458-b30c244554d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060207521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4060207521
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1776072908
Short name T555
Test name
Test status
Simulation time 169659237274 ps
CPU time 1866.89 seconds
Started Jun 28 05:19:53 PM PDT 24
Finished Jun 28 05:51:01 PM PDT 24
Peak memory 273640 kb
Host smart-1aa3d8d5-ee7b-4495-9573-9de7f6e057e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776072908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1776072908
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2115782115
Short name T213
Test name
Test status
Simulation time 4016055865 ps
CPU time 186.7 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:23:00 PM PDT 24
Peak memory 249416 kb
Host smart-57b5313d-f355-4184-be9a-a678e3c2da8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115782115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2115782115
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1373740873
Short name T77
Test name
Test status
Simulation time 898248596 ps
CPU time 54.46 seconds
Started Jun 28 05:19:52 PM PDT 24
Finished Jun 28 05:20:48 PM PDT 24
Peak memory 256608 kb
Host smart-50752a8c-20f5-4dc3-98c2-8c753403f7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13737
40873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1373740873
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.216877711
Short name T692
Test name
Test status
Simulation time 4440010356 ps
CPU time 30.65 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:24 PM PDT 24
Peak memory 257188 kb
Host smart-246f1d93-942a-4342-9923-19c6c39a97d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21687
7711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.216877711
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2373574263
Short name T662
Test name
Test status
Simulation time 2241938406 ps
CPU time 28.31 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:21 PM PDT 24
Peak memory 256944 kb
Host smart-4265a1ee-e18e-4f92-94b3-9b2cc48eb180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23735
74263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2373574263
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1657536983
Short name T513
Test name
Test status
Simulation time 2015979152 ps
CPU time 37.89 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:31 PM PDT 24
Peak memory 249100 kb
Host smart-4ac5e1ef-7514-40d7-93b8-dbe0f6713422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16575
36983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1657536983
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1962804993
Short name T506
Test name
Test status
Simulation time 8634186287 ps
CPU time 287.42 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:24:40 PM PDT 24
Peak memory 257604 kb
Host smart-dc4dc792-7e62-4b42-9224-ccb1a0ceb32f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962804993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1962804993
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.743570178
Short name T193
Test name
Test status
Simulation time 68063309 ps
CPU time 3.87 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:20:08 PM PDT 24
Peak memory 249732 kb
Host smart-4e6d62c3-fc19-467b-9b28-fe2107de16f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=743570178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.743570178
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1388528988
Short name T71
Test name
Test status
Simulation time 105510357212 ps
CPU time 1208.08 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:39:59 PM PDT 24
Peak memory 286508 kb
Host smart-efe780fb-2ced-4d95-ba35-d1c154837441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388528988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1388528988
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1882752439
Short name T689
Test name
Test status
Simulation time 1994758212 ps
CPU time 26.59 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:20:31 PM PDT 24
Peak memory 249224 kb
Host smart-4700eef0-be6a-4e48-85ac-4bb3d811e034
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1882752439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1882752439
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2510939186
Short name T392
Test name
Test status
Simulation time 1500555254 ps
CPU time 125.78 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:21:59 PM PDT 24
Peak memory 257388 kb
Host smart-57fb9329-25ec-4e8e-9d53-f8022f8dee20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
39186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2510939186
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1292299044
Short name T92
Test name
Test status
Simulation time 1759712443 ps
CPU time 24.9 seconds
Started Jun 28 05:19:51 PM PDT 24
Finished Jun 28 05:20:18 PM PDT 24
Peak memory 257484 kb
Host smart-db51e4d4-f8ba-4592-978b-4e2583a639b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
99044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1292299044
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.807624019
Short name T230
Test name
Test status
Simulation time 42786494502 ps
CPU time 1362.56 seconds
Started Jun 28 05:20:00 PM PDT 24
Finished Jun 28 05:42:44 PM PDT 24
Peak memory 273516 kb
Host smart-35dcc65b-982f-4ac1-8a02-f5e0ba853b1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807624019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.807624019
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.505053988
Short name T479
Test name
Test status
Simulation time 2742142738 ps
CPU time 121.95 seconds
Started Jun 28 05:20:00 PM PDT 24
Finished Jun 28 05:22:03 PM PDT 24
Peak memory 249360 kb
Host smart-9ec699ef-c061-4b20-b6c9-00d632d4dbed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505053988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.505053988
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3069146746
Short name T590
Test name
Test status
Simulation time 187655328 ps
CPU time 18.68 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:09 PM PDT 24
Peak memory 249296 kb
Host smart-f3478e5a-7dd4-4fd0-910f-9ff190121fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
46746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3069146746
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2931530232
Short name T518
Test name
Test status
Simulation time 4805374684 ps
CPU time 65.45 seconds
Started Jun 28 05:19:57 PM PDT 24
Finished Jun 28 05:21:02 PM PDT 24
Peak memory 249312 kb
Host smart-5cc805c6-a555-4372-8c0c-a23b5bb1bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
30232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2931530232
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1679915987
Short name T444
Test name
Test status
Simulation time 1903708611 ps
CPU time 25.52 seconds
Started Jun 28 05:19:50 PM PDT 24
Finished Jun 28 05:20:17 PM PDT 24
Peak memory 249308 kb
Host smart-e613b5e2-6ab3-469e-909d-4987473a6a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
15987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1679915987
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1750190824
Short name T219
Test name
Test status
Simulation time 693325894 ps
CPU time 37.81 seconds
Started Jun 28 05:19:49 PM PDT 24
Finished Jun 28 05:20:28 PM PDT 24
Peak memory 256544 kb
Host smart-3299b8be-24c6-4342-a5b9-77bfd45da0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17501
90824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1750190824
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1994684758
Short name T85
Test name
Test status
Simulation time 112870491842 ps
CPU time 8507.34 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 07:41:51 PM PDT 24
Peak memory 365308 kb
Host smart-25affecd-a321-4003-858f-20ff522fe5c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994684758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1994684758
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3213759845
Short name T211
Test name
Test status
Simulation time 23484383 ps
CPU time 2.63 seconds
Started Jun 28 05:19:59 PM PDT 24
Finished Jun 28 05:20:02 PM PDT 24
Peak memory 249468 kb
Host smart-c2e924a0-4aee-4386-9f5e-900da6817126
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3213759845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3213759845
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.719652578
Short name T484
Test name
Test status
Simulation time 104584340498 ps
CPU time 1221.87 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:40:26 PM PDT 24
Peak memory 289140 kb
Host smart-21c63ce7-2bb8-4093-bbbb-e08b1851d2be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719652578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.719652578
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1199717912
Short name T463
Test name
Test status
Simulation time 292581003 ps
CPU time 12.63 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:20:23 PM PDT 24
Peak memory 249268 kb
Host smart-17dd6179-c432-4abc-bf5d-defaf7e07da0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1199717912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1199717912
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2557342074
Short name T535
Test name
Test status
Simulation time 1739881999 ps
CPU time 157.36 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:22:41 PM PDT 24
Peak memory 257008 kb
Host smart-3e001e87-9769-4012-a94a-14b88c2fc228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25573
42074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2557342074
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1925573964
Short name T452
Test name
Test status
Simulation time 104068485 ps
CPU time 11 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:20:16 PM PDT 24
Peak memory 249168 kb
Host smart-868a1bf3-18a7-4a7d-9a50-fb79f096a2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
73964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1925573964
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2974515949
Short name T52
Test name
Test status
Simulation time 35479267419 ps
CPU time 1376.84 seconds
Started Jun 28 05:20:00 PM PDT 24
Finished Jun 28 05:42:58 PM PDT 24
Peak memory 287952 kb
Host smart-8cf0432a-b4f0-4e66-9361-a80e76779306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974515949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2974515949
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2888101540
Short name T192
Test name
Test status
Simulation time 146741389229 ps
CPU time 2559.84 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 06:02:43 PM PDT 24
Peak memory 289580 kb
Host smart-57fb9dd5-0b0f-4822-9c68-65edae329940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888101540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2888101540
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1165775558
Short name T182
Test name
Test status
Simulation time 37861167999 ps
CPU time 344.97 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:25:50 PM PDT 24
Peak memory 255992 kb
Host smart-3e12682f-ec78-4fb0-9804-8a328c0b8846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165775558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1165775558
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1627715418
Short name T598
Test name
Test status
Simulation time 360735236 ps
CPU time 17.05 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:20 PM PDT 24
Peak memory 255736 kb
Host smart-2f4aec97-43c0-4f62-98bd-d4e3fd69a441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
15418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1627715418
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.264432072
Short name T50
Test name
Test status
Simulation time 2419154949 ps
CPU time 38.44 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:20:49 PM PDT 24
Peak memory 257412 kb
Host smart-9fd56fde-f0d1-48af-9201-50bec82f88fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26443
2072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.264432072
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2435594361
Short name T489
Test name
Test status
Simulation time 3281017961 ps
CPU time 47.46 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:50 PM PDT 24
Peak memory 257528 kb
Host smart-07620a3a-b4b5-4161-9939-cb2886a766dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24355
94361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2435594361
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1667740701
Short name T10
Test name
Test status
Simulation time 11977036369 ps
CPU time 136.57 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:22:19 PM PDT 24
Peak memory 257564 kb
Host smart-50643378-b237-4db2-b3b5-b08ff51ca5c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667740701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1667740701
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1680420178
Short name T201
Test name
Test status
Simulation time 41751526 ps
CPU time 2.75 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:20:13 PM PDT 24
Peak memory 249564 kb
Host smart-bd806a7e-9138-4b89-977a-1e13fe4c1e17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1680420178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1680420178
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1354835802
Short name T75
Test name
Test status
Simulation time 46187110831 ps
CPU time 2623.67 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 06:03:47 PM PDT 24
Peak memory 290220 kb
Host smart-e45780cd-4e22-4a1d-adc3-49fa746b23dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354835802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1354835802
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3846093133
Short name T459
Test name
Test status
Simulation time 389288008 ps
CPU time 19.31 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:20:23 PM PDT 24
Peak memory 249268 kb
Host smart-70b611da-904a-4c52-bc89-e7ccf159a6d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3846093133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3846093133
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1291552169
Short name T492
Test name
Test status
Simulation time 7745852671 ps
CPU time 158.9 seconds
Started Jun 28 05:20:08 PM PDT 24
Finished Jun 28 05:22:47 PM PDT 24
Peak memory 252420 kb
Host smart-35b937a3-8957-4ba9-be06-6ebf9eba0593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12915
52169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1291552169
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2670475009
Short name T697
Test name
Test status
Simulation time 177678630 ps
CPU time 9.02 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:20:11 PM PDT 24
Peak memory 248892 kb
Host smart-a1ec4726-ebc1-4699-ba91-1a05fef7b371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26704
75009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2670475009
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2846548548
Short name T641
Test name
Test status
Simulation time 33988472072 ps
CPU time 778.1 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 271856 kb
Host smart-496c9698-9832-4749-9950-8076b33d01a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846548548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2846548548
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.787000196
Short name T592
Test name
Test status
Simulation time 30858380796 ps
CPU time 1837.56 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:50:42 PM PDT 24
Peak memory 272896 kb
Host smart-36bcb44b-6280-4206-8be7-f550c68920cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787000196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.787000196
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.235418639
Short name T318
Test name
Test status
Simulation time 7868700467 ps
CPU time 295.56 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:25:06 PM PDT 24
Peak memory 257180 kb
Host smart-4286e522-9546-4d41-9b42-25ba182d9802
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235418639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.235418639
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2445247352
Short name T595
Test name
Test status
Simulation time 801730880 ps
CPU time 26.77 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:20:31 PM PDT 24
Peak memory 249260 kb
Host smart-a618a413-f8a2-4aff-87c5-aa9ff5c72713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
47352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2445247352
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3887607559
Short name T358
Test name
Test status
Simulation time 2473360514 ps
CPU time 62.19 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:21:12 PM PDT 24
Peak memory 249152 kb
Host smart-d3022271-4db4-485d-a487-0aec14312406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
07559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3887607559
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1382674680
Short name T511
Test name
Test status
Simulation time 501200405 ps
CPU time 9.27 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:13 PM PDT 24
Peak memory 257464 kb
Host smart-074ed7c7-14e4-44c5-a4ef-4ad39b37a595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13826
74680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1382674680
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3478485687
Short name T242
Test name
Test status
Simulation time 426013365 ps
CPU time 11.11 seconds
Started Jun 28 05:20:00 PM PDT 24
Finished Jun 28 05:20:12 PM PDT 24
Peak memory 255924 kb
Host smart-97b296e9-bdb1-4927-8376-9abcf8e51b0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478485687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3478485687
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1026749323
Short name T208
Test name
Test status
Simulation time 32235749 ps
CPU time 3.17 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:20:08 PM PDT 24
Peak memory 249488 kb
Host smart-cf82b8ca-e9a4-4113-9203-1c50e96bf81d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1026749323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1026749323
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3447633159
Short name T534
Test name
Test status
Simulation time 55755766487 ps
CPU time 1168.31 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:39:33 PM PDT 24
Peak memory 289156 kb
Host smart-5cd8cb6f-2446-4a89-9b43-652dc4d6e20d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447633159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3447633159
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1469150458
Short name T215
Test name
Test status
Simulation time 586894813 ps
CPU time 26.14 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:30 PM PDT 24
Peak memory 249268 kb
Host smart-72667682-3f03-42db-88b8-c10bac538c22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1469150458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1469150458
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.87112352
Short name T428
Test name
Test status
Simulation time 2153143517 ps
CPU time 13.98 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:20:19 PM PDT 24
Peak memory 255096 kb
Host smart-7163064e-5062-46e4-ab27-d11f0672712a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87112
352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.87112352
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.184151601
Short name T66
Test name
Test status
Simulation time 5388444427 ps
CPU time 80.57 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:21:24 PM PDT 24
Peak memory 257528 kb
Host smart-b8caff2b-5fa8-4799-8d55-eb3b729b5989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18415
1601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.184151601
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.113365341
Short name T621
Test name
Test status
Simulation time 58074119505 ps
CPU time 1070.12 seconds
Started Jun 28 05:20:03 PM PDT 24
Finished Jun 28 05:37:54 PM PDT 24
Peak memory 270912 kb
Host smart-6a4269cf-dcd9-4585-be5e-2b99d3d99904
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113365341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.113365341
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4034271708
Short name T323
Test name
Test status
Simulation time 6472429896 ps
CPU time 251.64 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:24:14 PM PDT 24
Peak memory 249408 kb
Host smart-258cf494-118f-4af0-96a1-4bee8c9e3b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034271708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4034271708
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3737344267
Short name T417
Test name
Test status
Simulation time 1448393280 ps
CPU time 23.46 seconds
Started Jun 28 05:20:04 PM PDT 24
Finished Jun 28 05:20:28 PM PDT 24
Peak memory 256660 kb
Host smart-d13a0981-c6d8-4e83-b3f3-478da8d8d021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
44267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3737344267
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2726739363
Short name T16
Test name
Test status
Simulation time 1851893761 ps
CPU time 51.49 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:20:54 PM PDT 24
Peak memory 256844 kb
Host smart-c66eb610-1b2b-4ec6-b649-85a5db906700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27267
39363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2726739363
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3829262752
Short name T634
Test name
Test status
Simulation time 231227595 ps
CPU time 23.66 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:27 PM PDT 24
Peak memory 256952 kb
Host smart-96a0bc77-b7d5-40fe-8a97-c5aa276e6259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
62752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3829262752
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2399037066
Short name T422
Test name
Test status
Simulation time 1440308859 ps
CPU time 18.72 seconds
Started Jun 28 05:20:09 PM PDT 24
Finished Jun 28 05:20:29 PM PDT 24
Peak memory 249208 kb
Host smart-8b072b39-2039-4eca-967d-afaa62357ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
37066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2399037066
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.803974288
Short name T251
Test name
Test status
Simulation time 200674305427 ps
CPU time 2144.67 seconds
Started Jun 28 05:20:05 PM PDT 24
Finished Jun 28 05:55:50 PM PDT 24
Peak memory 273876 kb
Host smart-d1bceeb0-b871-4970-a474-34972794c60c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803974288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.803974288
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3095139745
Short name T162
Test name
Test status
Simulation time 98105058149 ps
CPU time 1409.02 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:43:33 PM PDT 24
Peak memory 306048 kb
Host smart-21685495-a8be-4bc3-a0e7-3394e5c17020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095139745 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3095139745
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1258670421
Short name T197
Test name
Test status
Simulation time 38388603 ps
CPU time 3.34 seconds
Started Jun 28 05:20:13 PM PDT 24
Finished Jun 28 05:20:17 PM PDT 24
Peak memory 249436 kb
Host smart-7c858b84-e2f3-4474-9e04-6f78984e44ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1258670421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1258670421
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1432388169
Short name T286
Test name
Test status
Simulation time 183537830101 ps
CPU time 2870.11 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 06:08:05 PM PDT 24
Peak memory 287036 kb
Host smart-cc52f91b-1983-43aa-9008-e82c47830341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432388169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1432388169
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3515560803
Short name T470
Test name
Test status
Simulation time 1177580412 ps
CPU time 29.23 seconds
Started Jun 28 05:20:15 PM PDT 24
Finished Jun 28 05:20:44 PM PDT 24
Peak memory 249196 kb
Host smart-d9e8bbcc-3a33-424e-a28b-8b14c2478f6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3515560803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3515560803
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2799495476
Short name T693
Test name
Test status
Simulation time 939809698 ps
CPU time 21.49 seconds
Started Jun 28 05:20:13 PM PDT 24
Finished Jun 28 05:20:35 PM PDT 24
Peak memory 256812 kb
Host smart-bf4bbe93-e368-43be-b9a9-ac2b3ed47229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
95476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2799495476
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3313461628
Short name T5
Test name
Test status
Simulation time 326536845 ps
CPU time 8.14 seconds
Started Jun 28 05:20:13 PM PDT 24
Finished Jun 28 05:20:21 PM PDT 24
Peak memory 249012 kb
Host smart-6e04d882-daba-4925-b582-d9d43f6acb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
61628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3313461628
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2759599458
Short name T644
Test name
Test status
Simulation time 43607393985 ps
CPU time 1312.85 seconds
Started Jun 28 05:20:13 PM PDT 24
Finished Jun 28 05:42:06 PM PDT 24
Peak memory 266820 kb
Host smart-807fa0b4-fb7f-40c5-ab6a-4cd6e0b27978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759599458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2759599458
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2587033771
Short name T166
Test name
Test status
Simulation time 74432725 ps
CPU time 5.1 seconds
Started Jun 28 05:20:02 PM PDT 24
Finished Jun 28 05:20:08 PM PDT 24
Peak memory 249252 kb
Host smart-ae198ba2-8458-4a51-b5f6-3446f41a7f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
33771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2587033771
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3886395373
Short name T234
Test name
Test status
Simulation time 187310056 ps
CPU time 9.15 seconds
Started Jun 28 05:20:15 PM PDT 24
Finished Jun 28 05:20:24 PM PDT 24
Peak memory 249300 kb
Host smart-2b10051b-55c6-4b20-b0d6-078cd5dfcc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
95373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3886395373
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2150836750
Short name T272
Test name
Test status
Simulation time 1522470271 ps
CPU time 56.3 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 05:21:11 PM PDT 24
Peak memory 249152 kb
Host smart-9d818d85-111b-4966-ae1b-185a1fe5297d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21508
36750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2150836750
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1801111908
Short name T374
Test name
Test status
Simulation time 1755896332 ps
CPU time 32.83 seconds
Started Jun 28 05:20:01 PM PDT 24
Finished Jun 28 05:20:35 PM PDT 24
Peak memory 257420 kb
Host smart-d27fa446-3486-4a3d-a978-6f112ee26859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011
11908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1801111908
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2965907803
Short name T205
Test name
Test status
Simulation time 124105452 ps
CPU time 2.68 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:19:27 PM PDT 24
Peak memory 249564 kb
Host smart-5e6197bd-9965-4995-8005-42fd3c4d371e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2965907803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2965907803
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.246372956
Short name T59
Test name
Test status
Simulation time 26258599810 ps
CPU time 1088.1 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:37:33 PM PDT 24
Peak memory 282664 kb
Host smart-dafa4976-5071-464b-b699-722f16ed7407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246372956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.246372956
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3897131886
Short name T543
Test name
Test status
Simulation time 199041190 ps
CPU time 12.42 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:19:40 PM PDT 24
Peak memory 249280 kb
Host smart-ca0e69c6-f8ad-4df0-80c1-810842a1515e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3897131886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3897131886
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4120822278
Short name T233
Test name
Test status
Simulation time 2512915421 ps
CPU time 104.94 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 257088 kb
Host smart-43ab4ecf-a063-475d-b16e-4ea256f64256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208
22278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4120822278
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.608783099
Short name T481
Test name
Test status
Simulation time 4723540047 ps
CPU time 80.91 seconds
Started Jun 28 05:19:15 PM PDT 24
Finished Jun 28 05:20:38 PM PDT 24
Peak memory 257532 kb
Host smart-0b402a62-f61b-4377-b712-61dec1283500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60878
3099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.608783099
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.780646870
Short name T669
Test name
Test status
Simulation time 8470196406 ps
CPU time 788.36 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 273848 kb
Host smart-a98e342e-0ee4-4b09-87fd-272955cd2091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780646870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.780646870
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3320589917
Short name T531
Test name
Test status
Simulation time 9930508668 ps
CPU time 828.26 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 274108 kb
Host smart-64d33845-4892-4ac0-bf75-a6b069a158d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320589917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3320589917
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3091074501
Short name T315
Test name
Test status
Simulation time 51594630261 ps
CPU time 577.76 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:29:03 PM PDT 24
Peak memory 256028 kb
Host smart-9196018e-c1d4-47a1-bcd3-5c966ac44699
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091074501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3091074501
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1489470369
Short name T40
Test name
Test status
Simulation time 1173634405 ps
CPU time 67.08 seconds
Started Jun 28 05:19:14 PM PDT 24
Finished Jun 28 05:20:23 PM PDT 24
Peak memory 249228 kb
Host smart-bcd78994-5b44-4509-95fe-d55f0f091807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14894
70369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1489470369
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2622255126
Short name T471
Test name
Test status
Simulation time 208613329 ps
CPU time 19.34 seconds
Started Jun 28 05:19:13 PM PDT 24
Finished Jun 28 05:19:35 PM PDT 24
Peak memory 256136 kb
Host smart-af77d20a-1beb-464a-8aea-976a1f4f22a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
55126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2622255126
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.955528548
Short name T24
Test name
Test status
Simulation time 1609833460 ps
CPU time 26.11 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:19:53 PM PDT 24
Peak memory 270388 kb
Host smart-2ece80f7-3cb7-4db9-8550-686f257ba082
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=955528548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.955528548
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.638514075
Short name T480
Test name
Test status
Simulation time 383602817 ps
CPU time 8.41 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:33 PM PDT 24
Peak memory 254232 kb
Host smart-ab187194-86b2-44e7-bce4-e631a32aaaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63851
4075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.638514075
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2646038882
Short name T564
Test name
Test status
Simulation time 456655281 ps
CPU time 28.59 seconds
Started Jun 28 05:19:12 PM PDT 24
Finished Jun 28 05:19:41 PM PDT 24
Peak memory 256492 kb
Host smart-a9ea15fe-694c-4883-870b-e7dd5e03be86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
38882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2646038882
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.4076611344
Short name T483
Test name
Test status
Simulation time 12338770345 ps
CPU time 1439.91 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:43:23 PM PDT 24
Peak memory 290184 kb
Host smart-11cac6cb-54be-4f4c-af16-262f26671044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076611344 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.4076611344
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1062675911
Short name T491
Test name
Test status
Simulation time 48485583642 ps
CPU time 2648.05 seconds
Started Jun 28 05:20:16 PM PDT 24
Finished Jun 28 06:04:24 PM PDT 24
Peak memory 289744 kb
Host smart-7f61c0b9-b0d1-4161-b40d-d060b5a0211b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062675911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1062675911
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3656627042
Short name T246
Test name
Test status
Simulation time 3314060365 ps
CPU time 161.85 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 05:22:57 PM PDT 24
Peak memory 257528 kb
Host smart-1f020b59-4cfd-4f70-9449-d0fd41d3622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566
27042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3656627042
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1694059413
Short name T515
Test name
Test status
Simulation time 2484483060 ps
CPU time 51.93 seconds
Started Jun 28 05:20:15 PM PDT 24
Finished Jun 28 05:21:07 PM PDT 24
Peak memory 257604 kb
Host smart-3f4a1d98-84cc-4dd9-aa3d-aad068d9c2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
59413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1694059413
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2063217809
Short name T235
Test name
Test status
Simulation time 12178733249 ps
CPU time 1169.6 seconds
Started Jun 28 05:20:33 PM PDT 24
Finished Jun 28 05:40:03 PM PDT 24
Peak memory 282088 kb
Host smart-3a294a87-0053-4339-851b-432133cd98de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063217809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2063217809
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3010147453
Short name T572
Test name
Test status
Simulation time 6492503637 ps
CPU time 732.18 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 273364 kb
Host smart-06b91e33-33b9-4a9a-a872-3cde1e0782c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010147453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3010147453
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3098147593
Short name T503
Test name
Test status
Simulation time 4572141566 ps
CPU time 100.16 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 05:21:54 PM PDT 24
Peak memory 254192 kb
Host smart-99dd36a8-0732-475b-9547-b385c1ed6a14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098147593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3098147593
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.930969037
Short name T500
Test name
Test status
Simulation time 4005677600 ps
CPU time 57.94 seconds
Started Jun 28 05:20:17 PM PDT 24
Finished Jun 28 05:21:15 PM PDT 24
Peak memory 257172 kb
Host smart-b5246f5c-3a99-43df-bf71-559dd90b7b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93096
9037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.930969037
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3554595938
Short name T659
Test name
Test status
Simulation time 411475479 ps
CPU time 38.21 seconds
Started Jun 28 05:20:14 PM PDT 24
Finished Jun 28 05:20:52 PM PDT 24
Peak memory 249180 kb
Host smart-3637e8c2-ebf0-4c9f-bf41-5b188a925186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
95938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3554595938
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3055000671
Short name T64
Test name
Test status
Simulation time 3286450080 ps
CPU time 227.92 seconds
Started Jun 28 05:20:36 PM PDT 24
Finished Jun 28 05:24:25 PM PDT 24
Peak memory 257524 kb
Host smart-0fab775b-b8e4-4b3d-8c77-e69ed49471a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055000671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3055000671
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3290173743
Short name T159
Test name
Test status
Simulation time 69343051696 ps
CPU time 4103.52 seconds
Started Jun 28 05:20:36 PM PDT 24
Finished Jun 28 06:29:01 PM PDT 24
Peak memory 298196 kb
Host smart-8d1b506c-cf87-4b22-824c-0e15480a9980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290173743 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3290173743
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2731559064
Short name T9
Test name
Test status
Simulation time 61001061772 ps
CPU time 3385.47 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 06:17:02 PM PDT 24
Peak memory 289912 kb
Host smart-0bc7b74b-6d21-4140-914c-de0476b34ddf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731559064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2731559064
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.100019963
Short name T375
Test name
Test status
Simulation time 11138964200 ps
CPU time 190.93 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:23:48 PM PDT 24
Peak memory 251468 kb
Host smart-198ea1fd-d991-4c3d-8b18-85aea363c915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10001
9963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.100019963
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3547836182
Short name T656
Test name
Test status
Simulation time 25450165 ps
CPU time 3.23 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:20:38 PM PDT 24
Peak memory 241028 kb
Host smart-f4c6f1e2-36ab-4b3e-b4c7-ea966f8630d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
36182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3547836182
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3476630112
Short name T633
Test name
Test status
Simulation time 26341993508 ps
CPU time 1476.12 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:45:12 PM PDT 24
Peak memory 272896 kb
Host smart-911107ac-7d13-499a-b19a-39ff59eb45cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476630112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3476630112
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1089670064
Short name T359
Test name
Test status
Simulation time 7164262489 ps
CPU time 884.15 seconds
Started Jun 28 05:20:37 PM PDT 24
Finished Jun 28 05:35:22 PM PDT 24
Peak memory 273732 kb
Host smart-f3e79c4a-e0b1-4af9-a2f0-0d256be2af50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089670064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1089670064
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2994853872
Short name T416
Test name
Test status
Simulation time 330499571 ps
CPU time 13.53 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:20:50 PM PDT 24
Peak memory 249148 kb
Host smart-0bbb7e21-1552-43e9-8700-fff3f9f5a512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29948
53872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2994853872
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.942581434
Short name T353
Test name
Test status
Simulation time 45904049 ps
CPU time 3.57 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:20:38 PM PDT 24
Peak memory 241104 kb
Host smart-698b11ce-e540-4fd5-8941-4b68f41d3ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94258
1434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.942581434
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.221980638
Short name T525
Test name
Test status
Simulation time 684477484 ps
CPU time 54.73 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:21:31 PM PDT 24
Peak memory 250336 kb
Host smart-56709574-f38e-4d91-bc5c-beb8370c5c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22198
0638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.221980638
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1920333209
Short name T679
Test name
Test status
Simulation time 495329865 ps
CPU time 8.81 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:20:45 PM PDT 24
Peak memory 257440 kb
Host smart-f062ca1e-8196-4f61-a9db-de7c61c2526d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
33209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1920333209
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2599303799
Short name T42
Test name
Test status
Simulation time 96551560527 ps
CPU time 3274.07 seconds
Started Jun 28 05:20:36 PM PDT 24
Finished Jun 28 06:15:12 PM PDT 24
Peak memory 302596 kb
Host smart-8576dbbb-9baa-4e1a-a0f8-3ebfba4a5e19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599303799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2599303799
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1728425832
Short name T628
Test name
Test status
Simulation time 37977241215 ps
CPU time 840.74 seconds
Started Jun 28 05:20:37 PM PDT 24
Finished Jun 28 05:34:38 PM PDT 24
Peak memory 273964 kb
Host smart-965112fd-96ee-4bc9-b199-49459aefe13d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728425832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1728425832
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.647169256
Short name T186
Test name
Test status
Simulation time 1404821686 ps
CPU time 53.83 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:21:29 PM PDT 24
Peak memory 256944 kb
Host smart-a56708e2-527f-4841-9347-030d46318b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64716
9256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.647169256
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2458108051
Short name T62
Test name
Test status
Simulation time 54854203 ps
CPU time 5.93 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:20:43 PM PDT 24
Peak memory 249300 kb
Host smart-7fe38ac0-fe42-4673-a1ad-ae7252a76aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581
08051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2458108051
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2334244697
Short name T552
Test name
Test status
Simulation time 39154170873 ps
CPU time 2393.31 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 06:00:29 PM PDT 24
Peak memory 289768 kb
Host smart-b359f825-ad45-4495-8b12-300268ac66ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334244697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2334244697
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4126526205
Short name T304
Test name
Test status
Simulation time 49162843508 ps
CPU time 286.57 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:25:22 PM PDT 24
Peak memory 249200 kb
Host smart-b86467fd-1877-4438-8651-a6d5658154b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126526205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4126526205
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.417180654
Short name T225
Test name
Test status
Simulation time 1167745717 ps
CPU time 36.58 seconds
Started Jun 28 05:20:33 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 256776 kb
Host smart-58f2960e-ae72-40bb-a23b-74a298f233ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41718
0654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.417180654
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2412045924
Short name T665
Test name
Test status
Simulation time 4252357373 ps
CPU time 63.39 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:21:40 PM PDT 24
Peak memory 257508 kb
Host smart-739c21af-42ff-49fa-aacd-6a9a253d53c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
45924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2412045924
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.321432092
Short name T478
Test name
Test status
Simulation time 1286944085 ps
CPU time 26.44 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:21:02 PM PDT 24
Peak memory 248548 kb
Host smart-950dce31-3864-481a-bc8d-ec03446a5f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
2092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.321432092
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3390518640
Short name T485
Test name
Test status
Simulation time 326907308 ps
CPU time 30.06 seconds
Started Jun 28 05:20:34 PM PDT 24
Finished Jun 28 05:21:05 PM PDT 24
Peak memory 256900 kb
Host smart-8ab9391b-6f07-453b-b337-b7e9e293a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905
18640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3390518640
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1460931955
Short name T502
Test name
Test status
Simulation time 75531532385 ps
CPU time 1513.67 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:45:50 PM PDT 24
Peak memory 290008 kb
Host smart-e836e6f8-411e-418f-90d1-495f8bfb4551
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460931955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1460931955
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.667763292
Short name T469
Test name
Test status
Simulation time 70781966825 ps
CPU time 1243.99 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:41:32 PM PDT 24
Peak memory 273588 kb
Host smart-4c6d032a-ca31-43b8-8d0a-85fa821cb014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667763292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.667763292
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2028232088
Short name T32
Test name
Test status
Simulation time 3701243692 ps
CPU time 149.68 seconds
Started Jun 28 05:20:53 PM PDT 24
Finished Jun 28 05:23:23 PM PDT 24
Peak memory 257060 kb
Host smart-ed94cbab-441a-4254-b888-a0b50228357f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282
32088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2028232088
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1030736199
Short name T608
Test name
Test status
Simulation time 422680404 ps
CPU time 30.13 seconds
Started Jun 28 05:20:46 PM PDT 24
Finished Jun 28 05:21:17 PM PDT 24
Peak memory 249280 kb
Host smart-a7ab674d-6fc8-45b4-8305-bf56d85e3fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10307
36199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1030736199
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1516190547
Short name T605
Test name
Test status
Simulation time 41773182725 ps
CPU time 2333.22 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:59:44 PM PDT 24
Peak memory 289312 kb
Host smart-bd75176f-f117-4fd0-8657-6fc7fb44b6e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516190547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1516190547
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.40741609
Short name T688
Test name
Test status
Simulation time 55082304225 ps
CPU time 1543.99 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:46:34 PM PDT 24
Peak memory 273408 kb
Host smart-425cf778-c558-4c0e-b96c-661fc8ff2624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40741609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.40741609
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.632779057
Short name T313
Test name
Test status
Simulation time 8823012105 ps
CPU time 373.94 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:27:02 PM PDT 24
Peak memory 249360 kb
Host smart-bd93e603-5091-41fd-a4d7-794b9cc2eefc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632779057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.632779057
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2675051039
Short name T651
Test name
Test status
Simulation time 8302043947 ps
CPU time 48.33 seconds
Started Jun 28 05:20:36 PM PDT 24
Finished Jun 28 05:21:26 PM PDT 24
Peak memory 256848 kb
Host smart-9707e473-0656-4e9a-8aa5-a92fbf48d63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26750
51039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2675051039
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2708358752
Short name T214
Test name
Test status
Simulation time 1988914280 ps
CPU time 34.01 seconds
Started Jun 28 05:20:35 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 249280 kb
Host smart-ae1f1f95-5665-403c-9885-6fd360e52e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
58752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2708358752
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4285644130
Short name T645
Test name
Test status
Simulation time 141564173538 ps
CPU time 2311.32 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:59:23 PM PDT 24
Peak memory 289784 kb
Host smart-1110bf9d-ef4d-4dbc-8f9d-6912aec8db37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285644130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4285644130
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.323637066
Short name T240
Test name
Test status
Simulation time 63504817561 ps
CPU time 1010 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:37:39 PM PDT 24
Peak memory 273028 kb
Host smart-fb4487a2-c244-4b04-b680-06dc5c96616f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323637066 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.323637066
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.402472960
Short name T460
Test name
Test status
Simulation time 35751413 ps
CPU time 2.86 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:20:55 PM PDT 24
Peak memory 240376 kb
Host smart-867702a7-2beb-4d48-915b-a94bc8ad12ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40247
2960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.402472960
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1134973978
Short name T561
Test name
Test status
Simulation time 286882569 ps
CPU time 16.43 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:21:05 PM PDT 24
Peak memory 255764 kb
Host smart-7efc9413-8b8e-4872-920e-d51aa0c3694a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11349
73978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1134973978
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3554794975
Short name T329
Test name
Test status
Simulation time 36006234566 ps
CPU time 1423.78 seconds
Started Jun 28 05:20:52 PM PDT 24
Finished Jun 28 05:44:37 PM PDT 24
Peak memory 286788 kb
Host smart-e0fdab0c-8ff1-441a-a26f-45090864d680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554794975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3554794975
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3592322765
Short name T226
Test name
Test status
Simulation time 24349181933 ps
CPU time 741.24 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 273888 kb
Host smart-595a4ee6-628f-4b94-bae6-98213d91cc27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592322765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3592322765
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3608888640
Short name T664
Test name
Test status
Simulation time 27191939810 ps
CPU time 549.18 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:29:58 PM PDT 24
Peak memory 248228 kb
Host smart-1796d81e-37d5-4842-8b35-ab915521822a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608888640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3608888640
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3332840905
Short name T578
Test name
Test status
Simulation time 10511301530 ps
CPU time 84.66 seconds
Started Jun 28 05:20:54 PM PDT 24
Finished Jun 28 05:22:19 PM PDT 24
Peak memory 256600 kb
Host smart-1b998f37-8656-4b43-b75d-e9c8d72fb6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328
40905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3332840905
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1407423069
Short name T507
Test name
Test status
Simulation time 643617907 ps
CPU time 29.21 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:21:18 PM PDT 24
Peak memory 256788 kb
Host smart-c3758a2b-e626-4662-8a5e-88f1af2a1b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
23069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1407423069
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2403470248
Short name T508
Test name
Test status
Simulation time 228970088 ps
CPU time 22.41 seconds
Started Jun 28 05:20:46 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 256716 kb
Host smart-63572dec-afb5-41a1-b6a1-a2f96762c70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24034
70248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2403470248
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.205769023
Short name T516
Test name
Test status
Simulation time 2320291244 ps
CPU time 39.46 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:21:30 PM PDT 24
Peak memory 256780 kb
Host smart-88af2414-fb1a-4fe7-a547-8deccdb3886f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20576
9023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.205769023
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.271798411
Short name T224
Test name
Test status
Simulation time 85765452546 ps
CPU time 2510.43 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 06:02:41 PM PDT 24
Peak memory 282336 kb
Host smart-b1b35355-8246-4ffb-9745-39f8d263fdbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271798411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.271798411
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.172309311
Short name T38
Test name
Test status
Simulation time 25009969059 ps
CPU time 1478.07 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:45:30 PM PDT 24
Peak memory 283920 kb
Host smart-9422c83c-fd15-42d6-89ee-78c3c52da354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172309311 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.172309311
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.186281594
Short name T639
Test name
Test status
Simulation time 63365935787 ps
CPU time 1074.92 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:38:44 PM PDT 24
Peak memory 273580 kb
Host smart-96c348e7-ffac-4993-abc9-48ab7b843aeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186281594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.186281594
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1393310103
Short name T102
Test name
Test status
Simulation time 247352711 ps
CPU time 5.08 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:20:53 PM PDT 24
Peak memory 240584 kb
Host smart-2209a941-59a3-4b91-b143-b9b2da0fd8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13933
10103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1393310103
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4087908490
Short name T566
Test name
Test status
Simulation time 548836234 ps
CPU time 28.12 seconds
Started Jun 28 05:20:55 PM PDT 24
Finished Jun 28 05:21:23 PM PDT 24
Peak memory 256984 kb
Host smart-1e0ead51-e54e-4c38-abb3-126aefbf2efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40879
08490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4087908490
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2181890436
Short name T328
Test name
Test status
Simulation time 149177310287 ps
CPU time 971.07 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:36:59 PM PDT 24
Peak memory 273968 kb
Host smart-94e5ca25-3b95-47d2-a557-f9e261920b80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181890436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2181890436
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.642551944
Short name T366
Test name
Test status
Simulation time 172782700056 ps
CPU time 2539.26 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 06:03:10 PM PDT 24
Peak memory 290108 kb
Host smart-839784a4-6b8c-4afe-be43-e653ef03ca58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642551944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.642551944
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.632255785
Short name T306
Test name
Test status
Simulation time 203503073338 ps
CPU time 487.65 seconds
Started Jun 28 05:20:54 PM PDT 24
Finished Jun 28 05:29:02 PM PDT 24
Peak memory 249284 kb
Host smart-4b91e07e-c151-4a10-8379-25f385c48542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632255785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.632255785
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3217792703
Short name T606
Test name
Test status
Simulation time 700216690 ps
CPU time 14.73 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:21:04 PM PDT 24
Peak memory 256864 kb
Host smart-07267d2b-c2f6-4021-8ab9-2b41f1f9ecdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32177
92703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3217792703
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2826981918
Short name T548
Test name
Test status
Simulation time 3811012903 ps
CPU time 55.51 seconds
Started Jun 28 05:20:46 PM PDT 24
Finished Jun 28 05:21:43 PM PDT 24
Peak memory 249344 kb
Host smart-ecb01c3f-0b81-46f0-a028-b8630e3be9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28269
81918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2826981918
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2022731091
Short name T61
Test name
Test status
Simulation time 1129703423 ps
CPU time 17.17 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:21:05 PM PDT 24
Peak memory 248432 kb
Host smart-6d69f6b8-3eaf-4713-85af-d25b4a986368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20227
31091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2022731091
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3459255978
Short name T599
Test name
Test status
Simulation time 1276434586 ps
CPU time 30.83 seconds
Started Jun 28 05:20:45 PM PDT 24
Finished Jun 28 05:21:16 PM PDT 24
Peak memory 249212 kb
Host smart-67f83a03-104c-48ec-b51d-47d8bfc4b995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34592
55978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3459255978
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1722812334
Short name T68
Test name
Test status
Simulation time 154614607097 ps
CPU time 2422.76 seconds
Started Jun 28 05:20:45 PM PDT 24
Finished Jun 28 06:01:08 PM PDT 24
Peak memory 290196 kb
Host smart-527bd3bc-3593-4375-a489-8066f12a986b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722812334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1722812334
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3053355611
Short name T482
Test name
Test status
Simulation time 52071511919 ps
CPU time 1706.46 seconds
Started Jun 28 05:20:53 PM PDT 24
Finished Jun 28 05:49:20 PM PDT 24
Peak memory 273812 kb
Host smart-69480c5c-51bb-4897-9719-2a1e31a3789c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053355611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3053355611
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4217063492
Short name T372
Test name
Test status
Simulation time 2111698499 ps
CPU time 119.61 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:22:52 PM PDT 24
Peak memory 256860 kb
Host smart-4742bfd0-2544-4216-b798-e4b3e14f8b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42170
63492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4217063492
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2002218262
Short name T472
Test name
Test status
Simulation time 1380440037 ps
CPU time 27.08 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:21:15 PM PDT 24
Peak memory 257012 kb
Host smart-7e269e36-85e0-4d7d-b290-96243691797a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20022
18262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2002218262
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1937074760
Short name T314
Test name
Test status
Simulation time 326396368394 ps
CPU time 1303.67 seconds
Started Jun 28 05:20:46 PM PDT 24
Finished Jun 28 05:42:31 PM PDT 24
Peak memory 273848 kb
Host smart-f8ed7c56-8817-446f-856d-90e091e49a3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937074760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1937074760
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.289018951
Short name T643
Test name
Test status
Simulation time 74197800661 ps
CPU time 2106.37 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:55:58 PM PDT 24
Peak memory 273976 kb
Host smart-597c9f4b-d741-41a1-a916-16f56a42ecc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289018951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.289018951
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3002454720
Short name T650
Test name
Test status
Simulation time 6006126344 ps
CPU time 261.75 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:25:11 PM PDT 24
Peak memory 248248 kb
Host smart-edb0fa4b-e0d1-4047-8676-ba8f62f2fe34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002454720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3002454720
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2751823434
Short name T432
Test name
Test status
Simulation time 93654864 ps
CPU time 9.21 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:21:01 PM PDT 24
Peak memory 249244 kb
Host smart-97276458-0072-4b36-965c-5bcaa768ff70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
23434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2751823434
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.801150158
Short name T486
Test name
Test status
Simulation time 1454829191 ps
CPU time 28.32 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:21:18 PM PDT 24
Peak memory 249228 kb
Host smart-9bafc231-9ab3-44ad-a862-df7a34b52ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80115
0158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.801150158
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.732086142
Short name T423
Test name
Test status
Simulation time 900478996 ps
CPU time 27.27 seconds
Started Jun 28 05:20:52 PM PDT 24
Finished Jun 28 05:21:20 PM PDT 24
Peak memory 249160 kb
Host smart-344a76e3-62ef-4002-9c1c-0efc1790b200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73208
6142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.732086142
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.647181393
Short name T601
Test name
Test status
Simulation time 1197252506 ps
CPU time 42.23 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:21:33 PM PDT 24
Peak memory 257464 kb
Host smart-4224faac-9638-48ae-a02f-5a023912de5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64718
1393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.647181393
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1097725987
Short name T602
Test name
Test status
Simulation time 35407081228 ps
CPU time 1608.13 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:47:39 PM PDT 24
Peak memory 289524 kb
Host smart-afa9f951-975d-4665-8ff4-dbcf385defc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097725987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1097725987
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.230654217
Short name T89
Test name
Test status
Simulation time 2942672786 ps
CPU time 172.4 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:23:41 PM PDT 24
Peak memory 257608 kb
Host smart-a4342d58-e8f9-4a49-9e7d-ea9eca3fde46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23065
4217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.230654217
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1107468775
Short name T458
Test name
Test status
Simulation time 2132806288 ps
CPU time 57.92 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:21:50 PM PDT 24
Peak memory 249192 kb
Host smart-2c7631c6-b151-4cab-84da-61f17fcfc0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
68775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1107468775
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.756311490
Short name T333
Test name
Test status
Simulation time 143594281614 ps
CPU time 1269.29 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:41:58 PM PDT 24
Peak memory 288572 kb
Host smart-3fb572fd-d4ab-4df3-b000-e722dca1f57b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756311490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.756311490
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.947938716
Short name T180
Test name
Test status
Simulation time 35250660393 ps
CPU time 1197.18 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 266824 kb
Host smart-d3ea6104-11fe-4cd6-be32-7231addb029a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947938716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.947938716
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1296478843
Short name T305
Test name
Test status
Simulation time 13086142764 ps
CPU time 547.98 seconds
Started Jun 28 05:20:51 PM PDT 24
Finished Jun 28 05:30:00 PM PDT 24
Peak memory 256044 kb
Host smart-e764abb1-0bfd-4b6f-92c1-3d27a09636b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296478843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1296478843
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3095504890
Short name T430
Test name
Test status
Simulation time 168844383 ps
CPU time 12.9 seconds
Started Jun 28 05:20:48 PM PDT 24
Finished Jun 28 05:21:02 PM PDT 24
Peak memory 249456 kb
Host smart-555dc36b-5296-44a4-855f-f5afa53638b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30955
04890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3095504890
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2912937459
Short name T95
Test name
Test status
Simulation time 460274887 ps
CPU time 31.7 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:21:23 PM PDT 24
Peak memory 248656 kb
Host smart-68cee2ae-041c-4b16-8866-221537d7c775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29129
37459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2912937459
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2132998604
Short name T539
Test name
Test status
Simulation time 701016562 ps
CPU time 41.11 seconds
Started Jun 28 05:20:47 PM PDT 24
Finished Jun 28 05:21:29 PM PDT 24
Peak memory 249328 kb
Host smart-433c28fc-d6df-4d34-8398-b795f2e15218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21329
98604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2132998604
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3548402279
Short name T512
Test name
Test status
Simulation time 1039192814 ps
CPU time 25.53 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:21:15 PM PDT 24
Peak memory 256688 kb
Host smart-521fd204-3e0e-4279-a727-bf974e1c56b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35484
02279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3548402279
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3581285348
Short name T390
Test name
Test status
Simulation time 18976907780 ps
CPU time 1719.28 seconds
Started Jun 28 05:20:52 PM PDT 24
Finished Jun 28 05:49:32 PM PDT 24
Peak memory 290236 kb
Host smart-ece4b1bb-a301-4491-9698-e5af05781bc3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581285348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3581285348
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1359232747
Short name T667
Test name
Test status
Simulation time 22634755616 ps
CPU time 662.64 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:31:54 PM PDT 24
Peak memory 284392 kb
Host smart-db5cebb8-9107-4a07-a13f-8ee47c1b46df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359232747 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1359232747
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2044895573
Short name T46
Test name
Test status
Simulation time 25683821331 ps
CPU time 1600.91 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:47:41 PM PDT 24
Peak memory 273900 kb
Host smart-817ac599-5e61-4805-aead-38a9abed3008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044895573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2044895573
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1549201604
Short name T530
Test name
Test status
Simulation time 7829564714 ps
CPU time 99.24 seconds
Started Jun 28 05:21:01 PM PDT 24
Finished Jun 28 05:22:41 PM PDT 24
Peak memory 256884 kb
Host smart-435b7538-67d9-4d1c-a2f1-21cf7bd50933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
01604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1549201604
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.761396481
Short name T553
Test name
Test status
Simulation time 297008527 ps
CPU time 19.84 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:20 PM PDT 24
Peak memory 248792 kb
Host smart-96e76b18-6cd8-493c-9367-a2d0afefe148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76139
6481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.761396481
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.823213443
Short name T591
Test name
Test status
Simulation time 140105400866 ps
CPU time 2430.52 seconds
Started Jun 28 05:21:03 PM PDT 24
Finished Jun 28 06:01:35 PM PDT 24
Peak memory 282152 kb
Host smart-831fcc61-0be2-4e55-9a52-2ae8c0ad7557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823213443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.823213443
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.184440686
Short name T558
Test name
Test status
Simulation time 24577215522 ps
CPU time 1521.13 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:46:22 PM PDT 24
Peak memory 273448 kb
Host smart-d9e12880-9249-4834-bad5-1f1cdce250de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184440686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.184440686
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3080873090
Short name T81
Test name
Test status
Simulation time 5305627699 ps
CPU time 110.37 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:22:50 PM PDT 24
Peak memory 249388 kb
Host smart-5cc7beb7-f4ad-41fe-9def-b9de725aee72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080873090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3080873090
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1706420579
Short name T391
Test name
Test status
Simulation time 1135441240 ps
CPU time 22.56 seconds
Started Jun 28 05:20:49 PM PDT 24
Finished Jun 28 05:21:12 PM PDT 24
Peak memory 256544 kb
Host smart-1da50963-dcac-4f6e-a387-7f28a36f8406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
20579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1706420579
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2580786455
Short name T436
Test name
Test status
Simulation time 48118867 ps
CPU time 4.72 seconds
Started Jun 28 05:21:00 PM PDT 24
Finished Jun 28 05:21:06 PM PDT 24
Peak memory 252020 kb
Host smart-8a362fe5-1451-43db-8c2e-b61c976770eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25807
86455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2580786455
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3538768414
Short name T419
Test name
Test status
Simulation time 1823007027 ps
CPU time 31.4 seconds
Started Jun 28 05:20:50 PM PDT 24
Finished Jun 28 05:21:22 PM PDT 24
Peak memory 256540 kb
Host smart-52ccab78-ce6f-4317-ad3a-471fec6a99e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
68414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3538768414
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3136656631
Short name T612
Test name
Test status
Simulation time 47623709951 ps
CPU time 1285.15 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:42:24 PM PDT 24
Peak memory 289880 kb
Host smart-2141e04a-41b0-4e06-873b-4dc98959ab56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136656631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3136656631
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.121710966
Short name T550
Test name
Test status
Simulation time 15314305862 ps
CPU time 1272.77 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:42:14 PM PDT 24
Peak memory 290148 kb
Host smart-a7c4ac80-a10b-4726-8e09-eaec92b11ea4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121710966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.121710966
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1720682019
Short name T456
Test name
Test status
Simulation time 2811729719 ps
CPU time 79.27 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:22:18 PM PDT 24
Peak memory 256884 kb
Host smart-c4535b00-f375-4b53-8043-c6c67a122986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
82019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1720682019
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3623135022
Short name T361
Test name
Test status
Simulation time 2203755089 ps
CPU time 11.07 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 254432 kb
Host smart-e10c0777-8bce-42cd-8d8b-d5e52467f1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36231
35022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3623135022
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3755614049
Short name T221
Test name
Test status
Simulation time 143708954319 ps
CPU time 2250.96 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:58:32 PM PDT 24
Peak memory 286468 kb
Host smart-76265389-c7f6-4247-be97-46a307946261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755614049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3755614049
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3311061206
Short name T290
Test name
Test status
Simulation time 37276321016 ps
CPU time 2287.46 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:59:07 PM PDT 24
Peak memory 289348 kb
Host smart-3e47ec40-eafc-410a-ba82-40da2c4d3787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311061206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3311061206
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3769439491
Short name T696
Test name
Test status
Simulation time 18903422290 ps
CPU time 219.5 seconds
Started Jun 28 05:21:00 PM PDT 24
Finished Jun 28 05:24:41 PM PDT 24
Peak memory 254964 kb
Host smart-ac2fbb54-7560-49c5-8ab5-3d700dff6110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769439491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3769439491
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.282412601
Short name T466
Test name
Test status
Simulation time 68542232 ps
CPU time 3.57 seconds
Started Jun 28 05:21:03 PM PDT 24
Finished Jun 28 05:21:08 PM PDT 24
Peak memory 241032 kb
Host smart-4305334b-9c42-485b-898e-f2ec6fe7363a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
2601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.282412601
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.218772453
Short name T17
Test name
Test status
Simulation time 8086732237 ps
CPU time 36.91 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:38 PM PDT 24
Peak memory 256560 kb
Host smart-41b66d2f-1444-4223-89fc-54e1befe7622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21877
2453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.218772453
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1835219340
Short name T184
Test name
Test status
Simulation time 199523414 ps
CPU time 12.25 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:12 PM PDT 24
Peak memory 248532 kb
Host smart-7b012e68-5f5e-4258-a5ab-5cdb067162c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
19340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1835219340
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1127503503
Short name T4
Test name
Test status
Simulation time 2938248141 ps
CPU time 43.45 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:45 PM PDT 24
Peak memory 257116 kb
Host smart-beb5a331-08f3-4164-b337-7c40bf1c63e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11275
03503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1127503503
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2318763181
Short name T648
Test name
Test status
Simulation time 67934560803 ps
CPU time 2031.55 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:54:50 PM PDT 24
Peak memory 306544 kb
Host smart-808d743a-07aa-4682-a4ed-24066663493e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318763181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2318763181
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3330279213
Short name T241
Test name
Test status
Simulation time 21113307860 ps
CPU time 1256.22 seconds
Started Jun 28 05:21:04 PM PDT 24
Finished Jun 28 05:42:00 PM PDT 24
Peak memory 274152 kb
Host smart-ce2a1d23-7f24-4bf2-a0f0-383c9de67540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330279213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3330279213
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.252440337
Short name T196
Test name
Test status
Simulation time 31372379 ps
CPU time 3.1 seconds
Started Jun 28 05:19:22 PM PDT 24
Finished Jun 28 05:19:25 PM PDT 24
Peak memory 249548 kb
Host smart-d0e3ae30-c0aa-455f-bea2-60c75b49d1e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=252440337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.252440337
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.143021546
Short name T382
Test name
Test status
Simulation time 141573408215 ps
CPU time 2218.22 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:56:25 PM PDT 24
Peak memory 289400 kb
Host smart-901e577b-9d6b-43cf-bc8d-e632d8c3c729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143021546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.143021546
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3343877964
Short name T569
Test name
Test status
Simulation time 281028520 ps
CPU time 10.08 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:19:38 PM PDT 24
Peak memory 249180 kb
Host smart-2d8f7571-b14f-4283-ad65-a2fe9cd24612
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3343877964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3343877964
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1864909341
Short name T90
Test name
Test status
Simulation time 3824693869 ps
CPU time 187.68 seconds
Started Jun 28 05:19:22 PM PDT 24
Finished Jun 28 05:22:30 PM PDT 24
Peak memory 257140 kb
Host smart-244e32f1-5af7-4d4b-a7ee-56860fabb86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
09341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1864909341
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3825685660
Short name T510
Test name
Test status
Simulation time 730686315 ps
CPU time 36.54 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:20:01 PM PDT 24
Peak memory 249300 kb
Host smart-e12b7622-93fb-4c29-b9ec-fc912b687590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
85660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3825685660
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1707961486
Short name T327
Test name
Test status
Simulation time 30637169293 ps
CPU time 967.86 seconds
Started Jun 28 05:19:22 PM PDT 24
Finished Jun 28 05:35:30 PM PDT 24
Peak memory 273932 kb
Host smart-b0e8dac1-8fed-4521-bc82-d426f87570f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707961486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1707961486
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1885646143
Short name T413
Test name
Test status
Simulation time 374393447434 ps
CPU time 2130.7 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:54:56 PM PDT 24
Peak memory 287948 kb
Host smart-ce167bc1-68c1-42d2-b4c1-97d4dc94848f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885646143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1885646143
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1940568237
Short name T412
Test name
Test status
Simulation time 379090560 ps
CPU time 22.83 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:48 PM PDT 24
Peak memory 256820 kb
Host smart-51147206-ff1d-403b-bd7a-5861a8de87b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
68237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1940568237
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4249924486
Short name T576
Test name
Test status
Simulation time 727928635 ps
CPU time 22.16 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:48 PM PDT 24
Peak memory 249224 kb
Host smart-9af536e7-84b5-484c-a744-61e451e453fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
24486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4249924486
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3624694360
Short name T13
Test name
Test status
Simulation time 300743735 ps
CPU time 17.11 seconds
Started Jun 28 05:19:26 PM PDT 24
Finished Jun 28 05:19:45 PM PDT 24
Peak memory 271408 kb
Host smart-4dbb2c9a-6626-434a-87b0-c79d7037b115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3624694360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3624694360
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.86527674
Short name T389
Test name
Test status
Simulation time 130008791 ps
CPU time 10.93 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:37 PM PDT 24
Peak memory 248808 kb
Host smart-d470d5d5-7cfb-4624-992e-daa0f88f92da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86527
674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.86527674
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2599483516
Short name T533
Test name
Test status
Simulation time 1724667217 ps
CPU time 27.22 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:52 PM PDT 24
Peak memory 256412 kb
Host smart-fefd2d13-883b-4264-a40b-a3b6c0714b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
83516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2599483516
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3837768577
Short name T18
Test name
Test status
Simulation time 28902562254 ps
CPU time 1485.1 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:44:10 PM PDT 24
Peak memory 274024 kb
Host smart-616948a5-02e5-4f14-913e-1f44223e25d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837768577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3837768577
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1519201591
Short name T562
Test name
Test status
Simulation time 57270583117 ps
CPU time 1979.05 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:54:00 PM PDT 24
Peak memory 273864 kb
Host smart-fb4f5536-64cc-4fe5-90a9-7fb8859a76cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519201591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1519201591
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3673820358
Short name T164
Test name
Test status
Simulation time 2721629135 ps
CPU time 73.36 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:22:13 PM PDT 24
Peak memory 257540 kb
Host smart-3c834135-acc0-41eb-b6c0-2f9937936f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
20358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3673820358
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3100874620
Short name T653
Test name
Test status
Simulation time 1721416402 ps
CPU time 19.36 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:21:19 PM PDT 24
Peak memory 249804 kb
Host smart-7c1c09d0-6472-455c-a34b-6d2652bcf0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
74620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3100874620
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1076217459
Short name T282
Test name
Test status
Simulation time 48445515899 ps
CPU time 877.85 seconds
Started Jun 28 05:20:57 PM PDT 24
Finished Jun 28 05:35:36 PM PDT 24
Peak memory 273928 kb
Host smart-6213235b-0fb8-49b9-9c17-706a3593619f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076217459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1076217459
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3035825382
Short name T501
Test name
Test status
Simulation time 35765348451 ps
CPU time 664.9 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:32:04 PM PDT 24
Peak memory 265780 kb
Host smart-f7e63ca6-83dc-404c-94f2-6081a13d7846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035825382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3035825382
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1608886997
Short name T320
Test name
Test status
Simulation time 32605888217 ps
CPU time 310.28 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:26:11 PM PDT 24
Peak memory 255988 kb
Host smart-2f7aa491-7245-43b3-b1aa-78648227b7ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608886997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1608886997
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1777200965
Short name T181
Test name
Test status
Simulation time 1070033184 ps
CPU time 70 seconds
Started Jun 28 05:21:03 PM PDT 24
Finished Jun 28 05:22:13 PM PDT 24
Peak memory 256664 kb
Host smart-44fa3d2a-87fb-45d4-835d-8a2132a063f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17772
00965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1777200965
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.547013383
Short name T403
Test name
Test status
Simulation time 2146454062 ps
CPU time 40.01 seconds
Started Jun 28 05:21:01 PM PDT 24
Finished Jun 28 05:21:42 PM PDT 24
Peak memory 249268 kb
Host smart-517ef95a-1b30-4d28-adcf-8142c0f73ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54701
3383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.547013383
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1949546686
Short name T623
Test name
Test status
Simulation time 804038414 ps
CPU time 34.65 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:21:33 PM PDT 24
Peak memory 256976 kb
Host smart-df0a41a3-e5e1-4c1e-8c5a-7ef0890a7403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
46686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1949546686
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1122006411
Short name T686
Test name
Test status
Simulation time 3134269501 ps
CPU time 16.69 seconds
Started Jun 28 05:20:58 PM PDT 24
Finished Jun 28 05:21:15 PM PDT 24
Peak memory 257524 kb
Host smart-e72aa65c-25fd-4f69-ad89-4415e2de7cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
06411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1122006411
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4112446342
Short name T28
Test name
Test status
Simulation time 16505876782 ps
CPU time 1247.44 seconds
Started Jun 28 05:21:00 PM PDT 24
Finished Jun 28 05:41:49 PM PDT 24
Peak memory 289792 kb
Host smart-b64e2b16-9fbc-4854-b73e-59998a1d49a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112446342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4112446342
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.973452610
Short name T683
Test name
Test status
Simulation time 179041713638 ps
CPU time 4292.29 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 06:32:34 PM PDT 24
Peak memory 355968 kb
Host smart-6599c765-cd61-4bca-99d8-519e2cca6af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973452610 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.973452610
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1224943747
Short name T82
Test name
Test status
Simulation time 60436751929 ps
CPU time 461.24 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:28:53 PM PDT 24
Peak memory 265732 kb
Host smart-cc8215b6-59ad-4e4a-9c03-1e239b7d0771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224943747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1224943747
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1589633341
Short name T682
Test name
Test status
Simulation time 2643346812 ps
CPU time 130.21 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 05:23:34 PM PDT 24
Peak memory 250444 kb
Host smart-9752f841-e122-47e2-84bb-ae4628f1ca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
33341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1589633341
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4117587996
Short name T266
Test name
Test status
Simulation time 1782026387 ps
CPU time 28.16 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:29 PM PDT 24
Peak memory 256568 kb
Host smart-d658eb8e-d679-4319-8064-6ec442e089a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41175
87996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4117587996
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.860763061
Short name T658
Test name
Test status
Simulation time 12347488289 ps
CPU time 1403.61 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:44:35 PM PDT 24
Peak memory 282216 kb
Host smart-0f510c0d-533d-4e17-94ad-b9d48e6c68c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860763061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.860763061
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2116391755
Short name T698
Test name
Test status
Simulation time 138999585 ps
CPU time 14.35 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:15 PM PDT 24
Peak memory 256720 kb
Host smart-3a55ea60-12aa-4f6b-8e09-9183cbcf19e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21163
91755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2116391755
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1562372960
Short name T611
Test name
Test status
Simulation time 8452241598 ps
CPU time 72.97 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:22:14 PM PDT 24
Peak memory 249148 kb
Host smart-9ffa4291-2577-44ed-940f-56ad64dd0a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
72960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1562372960
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2684413772
Short name T51
Test name
Test status
Simulation time 3421390983 ps
CPU time 58.03 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:22:09 PM PDT 24
Peak memory 256724 kb
Host smart-0ddd0190-d94d-44e2-8c4a-0c3327d6cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26844
13772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2684413772
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.604271973
Short name T443
Test name
Test status
Simulation time 948599829 ps
CPU time 57.16 seconds
Started Jun 28 05:20:59 PM PDT 24
Finished Jun 28 05:21:58 PM PDT 24
Peak memory 257464 kb
Host smart-4cc50ba1-1328-46ce-866c-5dfe8774c138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60427
1973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.604271973
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2745121201
Short name T247
Test name
Test status
Simulation time 76743707475 ps
CPU time 3478.26 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 06:19:10 PM PDT 24
Peak memory 323076 kb
Host smart-fa57c8f4-b0af-4e73-ba13-3b6e0ce4fe34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745121201 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2745121201
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.636592390
Short name T415
Test name
Test status
Simulation time 104492167440 ps
CPU time 2406.41 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 06:01:29 PM PDT 24
Peak memory 282164 kb
Host smart-003daf58-2821-449e-963f-bf4c2c91fdc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636592390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.636592390
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1903719607
Short name T678
Test name
Test status
Simulation time 3981397014 ps
CPU time 73.4 seconds
Started Jun 28 05:21:13 PM PDT 24
Finished Jun 28 05:22:27 PM PDT 24
Peak memory 256896 kb
Host smart-529c5773-4269-4dfa-b7d2-da89dcf4fae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
19607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1903719607
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1760077652
Short name T457
Test name
Test status
Simulation time 1638362881 ps
CPU time 36.01 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:21:47 PM PDT 24
Peak memory 256580 kb
Host smart-3a8c5eb8-e869-4b52-a22e-bc89bbf3044e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17600
77652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1760077652
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1572801868
Short name T376
Test name
Test status
Simulation time 119598752360 ps
CPU time 1867.66 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:52:21 PM PDT 24
Peak memory 273916 kb
Host smart-747c4167-44e4-4b34-8703-c2bca55c2bab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572801868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1572801868
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.278674693
Short name T536
Test name
Test status
Simulation time 2910854776 ps
CPU time 67.54 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:22:19 PM PDT 24
Peak memory 256728 kb
Host smart-bbb1c587-3a83-4fe6-9853-ec931042f774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278674693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.278674693
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3986405126
Short name T462
Test name
Test status
Simulation time 924232277 ps
CPU time 52.33 seconds
Started Jun 28 05:21:09 PM PDT 24
Finished Jun 28 05:22:02 PM PDT 24
Peak memory 256684 kb
Host smart-8c433035-ea43-474f-b886-46df70a3d2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
05126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3986405126
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2606363846
Short name T556
Test name
Test status
Simulation time 606981868 ps
CPU time 33.66 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:21:46 PM PDT 24
Peak memory 256972 kb
Host smart-4efc402c-7c74-46a9-9ce5-a4557d76d0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26063
63846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2606363846
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.467545983
Short name T267
Test name
Test status
Simulation time 155219734 ps
CPU time 20.99 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:21:32 PM PDT 24
Peak memory 248688 kb
Host smart-c5c6a1d7-14ee-40b1-8e7f-5dca8bed58d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46754
5983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.467545983
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3068145459
Short name T632
Test name
Test status
Simulation time 994825365 ps
CPU time 62.17 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 249460 kb
Host smart-2bed488d-1e5e-40e8-85a8-d0900bde66a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
45459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3068145459
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1377988698
Short name T244
Test name
Test status
Simulation time 23067627269 ps
CPU time 1652.31 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:48:44 PM PDT 24
Peak memory 289680 kb
Host smart-1af07a73-f4ed-4f6c-8d0a-fe5cd899f0cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377988698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1377988698
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3281022609
Short name T98
Test name
Test status
Simulation time 23649193873 ps
CPU time 1541.17 seconds
Started Jun 28 05:21:14 PM PDT 24
Finished Jun 28 05:46:55 PM PDT 24
Peak memory 273772 kb
Host smart-0762e5ce-78fc-4202-b030-2cc54749c92b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281022609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3281022609
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.366972521
Short name T560
Test name
Test status
Simulation time 7451043861 ps
CPU time 60.05 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:22:11 PM PDT 24
Peak memory 257600 kb
Host smart-e08342ce-19ff-422e-aabb-3e6c4c9e1457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36697
2521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.366972521
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2621988711
Short name T261
Test name
Test status
Simulation time 192058577 ps
CPU time 4.77 seconds
Started Jun 28 05:21:09 PM PDT 24
Finished Jun 28 05:21:14 PM PDT 24
Peak memory 241032 kb
Host smart-e4a46368-2fe4-4d3b-889c-62f3c475be46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219
88711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2621988711
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.776590041
Short name T179
Test name
Test status
Simulation time 139026782242 ps
CPU time 1939.44 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:53:32 PM PDT 24
Peak memory 273980 kb
Host smart-e3742a6b-dad1-4dd2-ba64-0771ed98f0a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776590041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.776590041
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3739218593
Short name T668
Test name
Test status
Simulation time 15310946840 ps
CPU time 296 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:26:09 PM PDT 24
Peak memory 249344 kb
Host smart-368ff8b2-1356-49cd-b416-e04c45c6674d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739218593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3739218593
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1242823188
Short name T493
Test name
Test status
Simulation time 1453433856 ps
CPU time 35.51 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:21:47 PM PDT 24
Peak memory 256892 kb
Host smart-14e33b86-d261-4200-b69f-d4396bc9e6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12428
23188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1242823188
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3705501821
Short name T279
Test name
Test status
Simulation time 1168298023 ps
CPU time 65.25 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:22:18 PM PDT 24
Peak memory 257672 kb
Host smart-9aea3ff0-c1c5-4bbb-ac99-0f94f573f120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
01821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3705501821
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3428235502
Short name T522
Test name
Test status
Simulation time 151474257 ps
CPU time 22 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 05:21:44 PM PDT 24
Peak memory 256184 kb
Host smart-f188dd5e-4e55-4f9d-832d-7cdd00cd332f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282
35502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3428235502
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2417694733
Short name T451
Test name
Test status
Simulation time 356752557 ps
CPU time 36.69 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:21:48 PM PDT 24
Peak memory 249288 kb
Host smart-284f654c-616f-4652-b571-f7cb5d26beaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24176
94733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2417694733
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2029908944
Short name T243
Test name
Test status
Simulation time 253477208096 ps
CPU time 3499.68 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 06:19:33 PM PDT 24
Peak memory 300160 kb
Host smart-fbf2e9af-ee95-4904-862e-a5ba3f5ada28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029908944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2029908944
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3155682839
Short name T43
Test name
Test status
Simulation time 28141786216 ps
CPU time 2416.04 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 06:01:38 PM PDT 24
Peak memory 306408 kb
Host smart-7bdca5a7-4ff5-4a2b-8621-34312cb4c9fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155682839 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3155682839
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.64743199
Short name T542
Test name
Test status
Simulation time 11641319586 ps
CPU time 1265.23 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 05:42:29 PM PDT 24
Peak memory 285264 kb
Host smart-516c7b22-c527-4f3a-a2dd-fb3fbc829425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64743199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.64743199
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.539378527
Short name T168
Test name
Test status
Simulation time 903736439 ps
CPU time 74.67 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:22:28 PM PDT 24
Peak memory 257180 kb
Host smart-5038cea1-c1ef-492d-9470-3f573b67af92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53937
8527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.539378527
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2030599757
Short name T523
Test name
Test status
Simulation time 1108317359 ps
CPU time 37.1 seconds
Started Jun 28 05:21:11 PM PDT 24
Finished Jun 28 05:21:49 PM PDT 24
Peak memory 256968 kb
Host smart-08c6a590-c88f-458a-969f-efc0b701bb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
99757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2030599757
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.929714820
Short name T670
Test name
Test status
Simulation time 40988701260 ps
CPU time 986.16 seconds
Started Jun 28 05:21:24 PM PDT 24
Finished Jun 28 05:37:51 PM PDT 24
Peak memory 272592 kb
Host smart-f67ffd0a-6562-479c-8af7-a55137458780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929714820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.929714820
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3696532954
Short name T319
Test name
Test status
Simulation time 12568959818 ps
CPU time 482.2 seconds
Started Jun 28 05:21:24 PM PDT 24
Finished Jun 28 05:29:27 PM PDT 24
Peak memory 249308 kb
Host smart-dca5f7be-1fc3-4bcb-8090-3dedf53fae6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696532954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3696532954
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2616732590
Short name T354
Test name
Test status
Simulation time 665764803 ps
CPU time 26.33 seconds
Started Jun 28 05:21:12 PM PDT 24
Finished Jun 28 05:21:39 PM PDT 24
Peak memory 256716 kb
Host smart-0c86f496-b0fd-4baf-b54d-9523e3790e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
32590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2616732590
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3184256876
Short name T405
Test name
Test status
Simulation time 50718275 ps
CPU time 3.8 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:21:26 PM PDT 24
Peak memory 240388 kb
Host smart-5da1c73d-29cf-44b3-9996-713f4f62a7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31842
56876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3184256876
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3025459676
Short name T571
Test name
Test status
Simulation time 1804859826 ps
CPU time 21.41 seconds
Started Jun 28 05:21:25 PM PDT 24
Finished Jun 28 05:21:47 PM PDT 24
Peak memory 256700 kb
Host smart-8fcd9d5b-5987-4f6d-b936-3ebb9720e45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30254
59676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3025459676
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3099393882
Short name T431
Test name
Test status
Simulation time 179956670 ps
CPU time 8.75 seconds
Started Jun 28 05:21:10 PM PDT 24
Finished Jun 28 05:21:20 PM PDT 24
Peak memory 257364 kb
Host smart-91e8cd64-61b7-452f-adf9-4a894cedb2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30993
93882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3099393882
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.646878750
Short name T393
Test name
Test status
Simulation time 47998007379 ps
CPU time 933.44 seconds
Started Jun 28 05:21:25 PM PDT 24
Finished Jun 28 05:36:59 PM PDT 24
Peak memory 282184 kb
Host smart-2b9f343b-1a63-4150-8a79-b28871502560
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646878750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.646878750
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3182462651
Short name T44
Test name
Test status
Simulation time 354365830656 ps
CPU time 8036.14 seconds
Started Jun 28 05:21:24 PM PDT 24
Finished Jun 28 07:35:22 PM PDT 24
Peak memory 355028 kb
Host smart-23bfddd2-49b8-475d-b073-141132f9b7a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182462651 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3182462651
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3172654238
Short name T185
Test name
Test status
Simulation time 10483912887 ps
CPU time 314.79 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 05:26:37 PM PDT 24
Peak memory 257120 kb
Host smart-8e148fdd-2ada-4741-b2a8-5c7070f05b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31726
54238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3172654238
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3409863794
Short name T231
Test name
Test status
Simulation time 537872154 ps
CPU time 26.04 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:21:48 PM PDT 24
Peak memory 249300 kb
Host smart-8774bfaf-f6a1-4d84-8596-81757a0a5da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34098
63794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3409863794
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.577000215
Short name T631
Test name
Test status
Simulation time 54679352035 ps
CPU time 1306.01 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 05:43:10 PM PDT 24
Peak memory 290360 kb
Host smart-1964f4c5-c114-4b90-baae-c43cf34613f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577000215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.577000215
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.728070522
Short name T498
Test name
Test status
Simulation time 491143359630 ps
CPU time 2326.87 seconds
Started Jun 28 05:21:25 PM PDT 24
Finished Jun 28 06:00:12 PM PDT 24
Peak memory 282100 kb
Host smart-dcf5cfba-ed79-4851-a5bb-082269a8ec32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728070522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.728070522
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3746147514
Short name T188
Test name
Test status
Simulation time 10106541247 ps
CPU time 400.78 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:28:03 PM PDT 24
Peak memory 249368 kb
Host smart-bde433e2-7404-4764-88be-ca07f69d5801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746147514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3746147514
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3069077847
Short name T439
Test name
Test status
Simulation time 2007021981 ps
CPU time 61.09 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 05:22:22 PM PDT 24
Peak memory 257256 kb
Host smart-ec96c83a-f677-4f28-8d8d-70ff9e9adf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30690
77847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3069077847
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1837232608
Short name T637
Test name
Test status
Simulation time 1095758770 ps
CPU time 37.75 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 05:22:00 PM PDT 24
Peak memory 256700 kb
Host smart-4ba25e81-ae9a-4c56-8ef0-e912a87cd5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
32608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1837232608
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1583977025
Short name T265
Test name
Test status
Simulation time 2919930823 ps
CPU time 53.64 seconds
Started Jun 28 05:21:22 PM PDT 24
Finished Jun 28 05:22:17 PM PDT 24
Peak memory 257376 kb
Host smart-00e119b3-5e26-48de-8756-2cc461df0da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
77025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1583977025
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.4129189212
Short name T373
Test name
Test status
Simulation time 3933204489 ps
CPU time 38.55 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 05:22:02 PM PDT 24
Peak memory 257552 kb
Host smart-51f85c56-afd2-4a7c-8250-ccc1d7104eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41291
89212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4129189212
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2129454170
Short name T101
Test name
Test status
Simulation time 30029782344 ps
CPU time 2031.52 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:55:29 PM PDT 24
Peak memory 287012 kb
Host smart-e3fb19b3-67fe-4fb2-8740-a19ebc147523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129454170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2129454170
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3053671466
Short name T400
Test name
Test status
Simulation time 2621008378 ps
CPU time 164.91 seconds
Started Jun 28 05:21:21 PM PDT 24
Finished Jun 28 05:24:06 PM PDT 24
Peak memory 256820 kb
Host smart-b5e4996c-a7d6-4386-bf3d-0202650b4093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30536
71466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3053671466
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2825560279
Short name T377
Test name
Test status
Simulation time 44301013 ps
CPU time 8.05 seconds
Started Jun 28 05:21:24 PM PDT 24
Finished Jun 28 05:21:33 PM PDT 24
Peak memory 253748 kb
Host smart-68bc4b24-bfb4-4445-9d16-78c50d6bcfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28255
60279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2825560279
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3107526169
Short name T437
Test name
Test status
Simulation time 50068589253 ps
CPU time 746.91 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 273660 kb
Host smart-4414fff3-5ee7-4a86-943a-3330c6325093
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107526169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3107526169
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3306802227
Short name T642
Test name
Test status
Simulation time 11665447531 ps
CPU time 1043.34 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:39:01 PM PDT 24
Peak memory 284800 kb
Host smart-c6e95c40-fe93-4d0f-b778-20ea3ca18853
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306802227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3306802227
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.178281940
Short name T464
Test name
Test status
Simulation time 1888448020 ps
CPU time 28.7 seconds
Started Jun 28 05:21:25 PM PDT 24
Finished Jun 28 05:21:54 PM PDT 24
Peak memory 257348 kb
Host smart-0e7ba8b6-8afe-40f9-a54e-c717e10075d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17828
1940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.178281940
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4028383646
Short name T488
Test name
Test status
Simulation time 472331942 ps
CPU time 43.38 seconds
Started Jun 28 05:21:23 PM PDT 24
Finished Jun 28 05:22:07 PM PDT 24
Peak memory 257000 kb
Host smart-671c363c-e824-45bb-9605-ba3d14ff11ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40283
83646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4028383646
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3871175118
Short name T495
Test name
Test status
Simulation time 1050385854 ps
CPU time 27.88 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:22:05 PM PDT 24
Peak memory 249300 kb
Host smart-631e5ed3-77ad-4a63-ac64-0e5811e44818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
75118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3871175118
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3974850002
Short name T411
Test name
Test status
Simulation time 734230697 ps
CPU time 48.42 seconds
Started Jun 28 05:21:26 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 257172 kb
Host smart-a54db1ca-0f06-4a01-b5e8-84cfb06917d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39748
50002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3974850002
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.889847824
Short name T167
Test name
Test status
Simulation time 220359632060 ps
CPU time 3533.39 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 06:20:31 PM PDT 24
Peak memory 289468 kb
Host smart-ffba102a-cbfd-43a0-b303-ab92132a267a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889847824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.889847824
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.72058825
Short name T172
Test name
Test status
Simulation time 370444352847 ps
CPU time 4308.08 seconds
Started Jun 28 05:21:37 PM PDT 24
Finished Jun 28 06:33:26 PM PDT 24
Peak memory 338800 kb
Host smart-d01bb90f-2060-4908-9a90-d67d47da5166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72058825 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.72058825
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2459391191
Short name T409
Test name
Test status
Simulation time 14821275462 ps
CPU time 177.79 seconds
Started Jun 28 05:21:37 PM PDT 24
Finished Jun 28 05:24:36 PM PDT 24
Peak memory 257508 kb
Host smart-968c0ab0-4852-4eea-82b3-3cf0d6a4245c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24593
91191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2459391191
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1603136806
Short name T517
Test name
Test status
Simulation time 68508810 ps
CPU time 7.35 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:21:43 PM PDT 24
Peak memory 254604 kb
Host smart-08297954-3ae5-492a-a718-9f6b98bd78c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
36806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1603136806
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1471801824
Short name T291
Test name
Test status
Simulation time 223203036172 ps
CPU time 1198.92 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:41:35 PM PDT 24
Peak memory 285572 kb
Host smart-a49e3ed0-6997-4c9c-8120-589c672f4fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471801824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1471801824
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1247874870
Short name T677
Test name
Test status
Simulation time 116919075962 ps
CPU time 1751.7 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:50:49 PM PDT 24
Peak memory 273956 kb
Host smart-b850a2be-ad6a-4000-bf6e-331b6ecbb42d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247874870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1247874870
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.307867029
Short name T680
Test name
Test status
Simulation time 44904094907 ps
CPU time 464.43 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:29:21 PM PDT 24
Peak memory 249360 kb
Host smart-fa3ffcd3-11f4-4fd8-a16b-7c2f31ff436e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307867029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.307867029
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4196036193
Short name T435
Test name
Test status
Simulation time 3530099691 ps
CPU time 56.51 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:22:33 PM PDT 24
Peak memory 257244 kb
Host smart-719d4539-a912-45dd-b1b4-8be5df65cfb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41960
36193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4196036193
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.128293132
Short name T620
Test name
Test status
Simulation time 69337636 ps
CPU time 6.77 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:21:43 PM PDT 24
Peak memory 255512 kb
Host smart-1cc14428-513d-4d8e-9875-1ffd6edfd71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12829
3132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.128293132
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1949898823
Short name T652
Test name
Test status
Simulation time 545882613 ps
CPU time 36.9 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:22:13 PM PDT 24
Peak memory 248388 kb
Host smart-d6d7927e-e40c-4571-a4ed-cc0dd711bd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19498
98823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1949898823
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3409793503
Short name T39
Test name
Test status
Simulation time 1747406259 ps
CPU time 34.35 seconds
Started Jun 28 05:21:37 PM PDT 24
Finished Jun 28 05:22:12 PM PDT 24
Peak memory 256436 kb
Host smart-2ed1f703-3fc4-4426-86ec-862dbdcbf643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
93503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3409793503
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2274577582
Short name T563
Test name
Test status
Simulation time 7196100346 ps
CPU time 421.52 seconds
Started Jun 28 05:21:37 PM PDT 24
Finished Jun 28 05:28:39 PM PDT 24
Peak memory 265804 kb
Host smart-9c99e9c2-34cc-4765-ab7d-ee1bd835e852
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274577582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2274577582
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.933526589
Short name T577
Test name
Test status
Simulation time 305109597538 ps
CPU time 2277.68 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 05:59:45 PM PDT 24
Peak memory 290236 kb
Host smart-f8660361-c164-4d59-ba32-da0b3594e7d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933526589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.933526589
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3387448536
Short name T603
Test name
Test status
Simulation time 22177082206 ps
CPU time 280.24 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 05:26:28 PM PDT 24
Peak memory 257128 kb
Host smart-7e8c16b5-9595-46c8-a050-644f8da16a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33874
48536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3387448536
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3019338677
Short name T232
Test name
Test status
Simulation time 1133052841 ps
CPU time 28.57 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:22:18 PM PDT 24
Peak memory 249040 kb
Host smart-2247b4bb-6ecc-4115-adfc-bd7c236370ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30193
38677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3019338677
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3575137685
Short name T326
Test name
Test status
Simulation time 119666857542 ps
CPU time 1650.11 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:49:19 PM PDT 24
Peak memory 288884 kb
Host smart-1fa6ca29-f94a-4769-9758-111f13170bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575137685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3575137685
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2405047441
Short name T685
Test name
Test status
Simulation time 11942591063 ps
CPU time 882.61 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 05:36:31 PM PDT 24
Peak memory 273692 kb
Host smart-0b337199-8703-4e8c-ab37-72a0468c2b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405047441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2405047441
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3092942298
Short name T299
Test name
Test status
Simulation time 13703720681 ps
CPU time 519.67 seconds
Started Jun 28 05:21:49 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 248984 kb
Host smart-3d37eb56-c843-4f38-876e-9a9ded0cc809
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092942298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3092942298
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.659586965
Short name T455
Test name
Test status
Simulation time 377882272 ps
CPU time 29.77 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:22:07 PM PDT 24
Peak memory 249332 kb
Host smart-5b8c4a8e-8120-42de-829c-1f78e756fbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65958
6965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.659586965
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2600722495
Short name T570
Test name
Test status
Simulation time 44279433 ps
CPU time 4.73 seconds
Started Jun 28 05:21:35 PM PDT 24
Finished Jun 28 05:21:41 PM PDT 24
Peak memory 251800 kb
Host smart-206b43db-ece0-4255-81d1-d52f871ffa09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26007
22495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2600722495
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3796820536
Short name T252
Test name
Test status
Simulation time 2520276131 ps
CPU time 40.72 seconds
Started Jun 28 05:21:49 PM PDT 24
Finished Jun 28 05:22:31 PM PDT 24
Peak memory 249392 kb
Host smart-6050b7ab-42b8-46cf-bf0a-5cacfc6b882b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
20536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3796820536
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3830367947
Short name T666
Test name
Test status
Simulation time 4390904610 ps
CPU time 71.39 seconds
Started Jun 28 05:21:36 PM PDT 24
Finished Jun 28 05:22:49 PM PDT 24
Peak memory 257476 kb
Host smart-1c745e2a-5752-4fa7-bf10-3ffab9dfd62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
67947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3830367947
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2314168040
Short name T597
Test name
Test status
Simulation time 2996446111 ps
CPU time 293.73 seconds
Started Jun 28 05:21:46 PM PDT 24
Finished Jun 28 05:26:40 PM PDT 24
Peak memory 257548 kb
Host smart-baf1bdc5-463b-4f55-9f2d-b28b247cab6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314168040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2314168040
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3297778046
Short name T173
Test name
Test status
Simulation time 265880254609 ps
CPU time 4066.87 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 06:29:36 PM PDT 24
Peak memory 306260 kb
Host smart-fb052a0c-e688-4123-8400-8d22503bb53a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297778046 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3297778046
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2771459937
Short name T529
Test name
Test status
Simulation time 29588877336 ps
CPU time 1569.08 seconds
Started Jun 28 05:21:49 PM PDT 24
Finished Jun 28 05:47:59 PM PDT 24
Peak memory 289864 kb
Host smart-d75a9de3-f924-4e8b-befe-78d9cecf633d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771459937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2771459937
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2816150842
Short name T567
Test name
Test status
Simulation time 17312105773 ps
CPU time 189.78 seconds
Started Jun 28 05:21:52 PM PDT 24
Finished Jun 28 05:25:02 PM PDT 24
Peak memory 257128 kb
Host smart-338ca370-ceec-4bf5-8d30-3444d377e491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161
50842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2816150842
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3995142185
Short name T474
Test name
Test status
Simulation time 2781553799 ps
CPU time 47.46 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:22:36 PM PDT 24
Peak memory 249352 kb
Host smart-1d9650bd-7d86-412d-baaf-b65b0601f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39951
42185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3995142185
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2253232005
Short name T322
Test name
Test status
Simulation time 24612721734 ps
CPU time 942.33 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:37:31 PM PDT 24
Peak memory 273136 kb
Host smart-0956eab1-a7c6-4ab4-90f6-66269785f27d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253232005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2253232005
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.855620123
Short name T370
Test name
Test status
Simulation time 92824765990 ps
CPU time 1658.11 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:49:27 PM PDT 24
Peak memory 273980 kb
Host smart-d88b8a0e-b372-4737-a462-8774f497a71b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855620123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.855620123
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.289762552
Short name T310
Test name
Test status
Simulation time 3781779708 ps
CPU time 143.47 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 05:24:12 PM PDT 24
Peak memory 249408 kb
Host smart-c85e2291-3900-4a7d-83cb-d8c4010e47b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289762552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.289762552
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4042556683
Short name T546
Test name
Test status
Simulation time 800464780 ps
CPU time 41.47 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:22:31 PM PDT 24
Peak memory 256520 kb
Host smart-392f6ed0-e203-41f0-b359-e135b7350c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40425
56683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4042556683
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2910804089
Short name T357
Test name
Test status
Simulation time 1070822490 ps
CPU time 19.88 seconds
Started Jun 28 05:21:49 PM PDT 24
Finished Jun 28 05:22:10 PM PDT 24
Peak memory 248728 kb
Host smart-81ff4f5c-643c-4567-817c-4f609a2429f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
04089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2910804089
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3439915219
Short name T183
Test name
Test status
Simulation time 1996008566 ps
CPU time 23.81 seconds
Started Jun 28 05:21:49 PM PDT 24
Finished Jun 28 05:22:14 PM PDT 24
Peak memory 256892 kb
Host smart-d865849f-069e-47cc-8b7d-af7daccbd921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
15219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3439915219
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.326740823
Short name T371
Test name
Test status
Simulation time 798019309 ps
CPU time 25.89 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 257620 kb
Host smart-47e6d47b-0327-4d0b-a272-4bd842d6a85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
0823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.326740823
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2340979174
Short name T401
Test name
Test status
Simulation time 4009114268 ps
CPU time 340.41 seconds
Started Jun 28 05:21:47 PM PDT 24
Finished Jun 28 05:27:28 PM PDT 24
Peak memory 257608 kb
Host smart-594246b6-af4f-48f9-b00b-af16854b5901
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340979174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2340979174
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.739651224
Short name T203
Test name
Test status
Simulation time 23724601 ps
CPU time 2.25 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:19:29 PM PDT 24
Peak memory 249580 kb
Host smart-703185db-1f91-4d29-a51d-f9d0027b9cbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=739651224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.739651224
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2113944841
Short name T447
Test name
Test status
Simulation time 21928592688 ps
CPU time 1526.22 seconds
Started Jun 28 05:19:28 PM PDT 24
Finished Jun 28 05:44:55 PM PDT 24
Peak memory 273792 kb
Host smart-b771525d-2c7e-46d1-ac54-d2a56ad37c5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113944841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2113944841
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2780010112
Short name T72
Test name
Test status
Simulation time 177893162 ps
CPU time 10.91 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:19:36 PM PDT 24
Peak memory 249260 kb
Host smart-9742730f-1360-4af6-825a-154713c4e16d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2780010112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2780010112
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.669361303
Short name T26
Test name
Test status
Simulation time 2645679025 ps
CPU time 41.31 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:20:07 PM PDT 24
Peak memory 257044 kb
Host smart-0da1abb9-779d-43c5-8337-09e52b3ec57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66936
1303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.669361303
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1098283377
Short name T165
Test name
Test status
Simulation time 435207134 ps
CPU time 27.58 seconds
Started Jun 28 05:19:28 PM PDT 24
Finished Jun 28 05:19:57 PM PDT 24
Peak memory 249652 kb
Host smart-08847772-9eaa-402a-9912-86dc4565938b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982
83377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1098283377
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1963953307
Short name T33
Test name
Test status
Simulation time 68838355317 ps
CPU time 1838.97 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:50:06 PM PDT 24
Peak memory 273356 kb
Host smart-0edd2c79-9762-4b54-9446-5b479c59627b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963953307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1963953307
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2501924958
Short name T687
Test name
Test status
Simulation time 27802795774 ps
CPU time 783.62 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:32:30 PM PDT 24
Peak memory 271500 kb
Host smart-822feb1b-904d-42fa-badc-ac8e0588bab9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501924958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2501924958
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.42856118
Short name T365
Test name
Test status
Simulation time 2126039891 ps
CPU time 58.2 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:20:25 PM PDT 24
Peak memory 249316 kb
Host smart-d163b0a1-6b3b-47f7-a8cf-fb426e4b7cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42856
118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.42856118
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1828346679
Short name T57
Test name
Test status
Simulation time 816619479 ps
CPU time 49.14 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:20:16 PM PDT 24
Peak memory 256612 kb
Host smart-9330cba4-b8d7-4067-8828-afdc9aecf7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18283
46679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1828346679
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3365261738
Short name T545
Test name
Test status
Simulation time 158243234 ps
CPU time 15.22 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:19:42 PM PDT 24
Peak memory 249224 kb
Host smart-22651292-7a02-4ad8-8d62-bf44971887fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
61738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3365261738
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2611474688
Short name T397
Test name
Test status
Simulation time 894738826 ps
CPU time 11.67 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:19:38 PM PDT 24
Peak memory 254880 kb
Host smart-d945cf4e-a752-4baa-9572-770261fe48f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
74688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2611474688
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.464808345
Short name T60
Test name
Test status
Simulation time 38616614439 ps
CPU time 2483.87 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 06:00:47 PM PDT 24
Peak memory 290340 kb
Host smart-f18ad49e-e5fa-4f1f-9e2e-46dd2707f18b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464808345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.464808345
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.704732181
Short name T671
Test name
Test status
Simulation time 21275602692 ps
CPU time 1296.87 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:43:37 PM PDT 24
Peak memory 273972 kb
Host smart-31d732d8-36d9-4f41-84ab-7c78b90a5dbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704732181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.704732181
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1942222756
Short name T169
Test name
Test status
Simulation time 4072817273 ps
CPU time 261.79 seconds
Started Jun 28 05:21:58 PM PDT 24
Finished Jun 28 05:26:21 PM PDT 24
Peak memory 256992 kb
Host smart-30abc38c-5529-4ac9-8a74-4e44edd393ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19422
22756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1942222756
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.110171622
Short name T187
Test name
Test status
Simulation time 704862235 ps
CPU time 13.83 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 248828 kb
Host smart-f246d9a4-0098-40be-96ba-ba856d7af8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
1622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.110171622
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4013733616
Short name T216
Test name
Test status
Simulation time 27842757128 ps
CPU time 1452.11 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:46:13 PM PDT 24
Peak memory 273892 kb
Host smart-f8dd6e4f-c666-444f-9959-71a477d0ca29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013733616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4013733616
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3804721775
Short name T574
Test name
Test status
Simulation time 10403875102 ps
CPU time 893.76 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:36:53 PM PDT 24
Peak memory 273968 kb
Host smart-baffdd64-99ea-4285-a8a5-92122f46d7e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804721775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3804721775
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4273115991
Short name T547
Test name
Test status
Simulation time 54578418697 ps
CPU time 561.75 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:31:23 PM PDT 24
Peak memory 255212 kb
Host smart-9cf5fb96-d692-49e9-acc0-a8746f5d32f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273115991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4273115991
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1111486061
Short name T582
Test name
Test status
Simulation time 2201379810 ps
CPU time 37.31 seconds
Started Jun 28 05:21:58 PM PDT 24
Finished Jun 28 05:22:36 PM PDT 24
Peak memory 257264 kb
Host smart-aa132759-f973-457a-b8cd-09d31aa53c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11114
86061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1111486061
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1331771803
Short name T673
Test name
Test status
Simulation time 762026775 ps
CPU time 50.64 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:22:50 PM PDT 24
Peak memory 249304 kb
Host smart-8c288bd9-ab57-4ac3-81cb-613d1a922fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13317
71803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1331771803
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3462252026
Short name T398
Test name
Test status
Simulation time 1131983647 ps
CPU time 33.04 seconds
Started Jun 28 05:21:58 PM PDT 24
Finished Jun 28 05:22:31 PM PDT 24
Peak memory 248732 kb
Host smart-a7d58d51-7be7-4c9d-9ad2-02f5f882b48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34622
52026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3462252026
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1839707420
Short name T360
Test name
Test status
Simulation time 987912022 ps
CPU time 58.1 seconds
Started Jun 28 05:21:48 PM PDT 24
Finished Jun 28 05:22:47 PM PDT 24
Peak memory 249188 kb
Host smart-b64c204a-117f-4fa8-874e-16e30f5ce593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18397
07420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1839707420
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.445302454
Short name T84
Test name
Test status
Simulation time 13517711216 ps
CPU time 241.46 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:26:01 PM PDT 24
Peak memory 257612 kb
Host smart-5b0520bd-80e1-4881-a336-3747398504b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445302454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.445302454
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.685797386
Short name T368
Test name
Test status
Simulation time 214205096777 ps
CPU time 2432.18 seconds
Started Jun 28 05:21:57 PM PDT 24
Finished Jun 28 06:02:31 PM PDT 24
Peak memory 290300 kb
Host smart-229a596d-2a0b-461b-a5b8-8b949fec8178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685797386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.685797386
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.229131008
Short name T672
Test name
Test status
Simulation time 2013621837 ps
CPU time 62.24 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:23:03 PM PDT 24
Peak memory 257004 kb
Host smart-986cddb4-90c7-472d-88f4-ee400acc4c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913
1008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.229131008
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.756092152
Short name T487
Test name
Test status
Simulation time 1676546204 ps
CPU time 24.12 seconds
Started Jun 28 05:21:57 PM PDT 24
Finished Jun 28 05:22:23 PM PDT 24
Peak memory 257300 kb
Host smart-6e110d5b-26ed-49b9-b5f2-03394e7dd966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75609
2152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.756092152
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4004120105
Short name T324
Test name
Test status
Simulation time 109122484073 ps
CPU time 2847.69 seconds
Started Jun 28 05:22:01 PM PDT 24
Finished Jun 28 06:09:30 PM PDT 24
Peak memory 290316 kb
Host smart-cba4a47d-38b0-4537-9489-283b11ef27d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004120105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4004120105
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.4234648911
Short name T278
Test name
Test status
Simulation time 42494529927 ps
CPU time 891.68 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:36:53 PM PDT 24
Peak memory 284216 kb
Host smart-addaeea4-cee8-4b9c-81e9-673fcd395dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234648911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.4234648911
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1816969207
Short name T657
Test name
Test status
Simulation time 292801454 ps
CPU time 21.27 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:22:21 PM PDT 24
Peak memory 257072 kb
Host smart-5b9f6558-3733-416f-997f-b8fef490c9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
69207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1816969207
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3944307675
Short name T521
Test name
Test status
Simulation time 356418065 ps
CPU time 11.69 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:22:13 PM PDT 24
Peak memory 256340 kb
Host smart-56465eb0-1bf2-4196-871d-7a656a362864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
07675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3944307675
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3225278853
Short name T1
Test name
Test status
Simulation time 3893851694 ps
CPU time 80.68 seconds
Started Jun 28 05:21:57 PM PDT 24
Finished Jun 28 05:23:19 PM PDT 24
Peak memory 250248 kb
Host smart-85eacb40-6eea-45fb-a729-8ab8dd6ac3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
78853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3225278853
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1155107687
Short name T468
Test name
Test status
Simulation time 42954949 ps
CPU time 4.4 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:22:05 PM PDT 24
Peak memory 251448 kb
Host smart-532a7191-9d65-40bd-8480-3954581cb888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11551
07687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1155107687
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2226471515
Short name T87
Test name
Test status
Simulation time 135667253244 ps
CPU time 2266.56 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:59:47 PM PDT 24
Peak memory 290180 kb
Host smart-5195ccaf-68ab-4208-8a22-1ce447f2434a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226471515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2226471515
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1452863450
Short name T477
Test name
Test status
Simulation time 50526769366 ps
CPU time 1558.63 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:48:00 PM PDT 24
Peak memory 273640 kb
Host smart-5d83a076-ec23-42c4-86bd-0d9c4cc7c871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452863450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1452863450
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3838366729
Short name T378
Test name
Test status
Simulation time 1859362844 ps
CPU time 28.56 seconds
Started Jun 28 05:21:57 PM PDT 24
Finished Jun 28 05:22:27 PM PDT 24
Peak memory 248832 kb
Host smart-c09df782-fa01-434e-ae0a-f929488bbba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38383
66729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3838366729
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1845553204
Short name T36
Test name
Test status
Simulation time 522202627 ps
CPU time 32.13 seconds
Started Jun 28 05:21:58 PM PDT 24
Finished Jun 28 05:22:31 PM PDT 24
Peak memory 249200 kb
Host smart-d8188e50-5692-4d39-8bc8-ae1778e73e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
53204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1845553204
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2890522985
Short name T312
Test name
Test status
Simulation time 80874022069 ps
CPU time 1423.67 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:45:53 PM PDT 24
Peak memory 282060 kb
Host smart-45d8a1ec-2654-4a30-9dc4-be31de7d9bbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890522985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2890522985
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.381071336
Short name T273
Test name
Test status
Simulation time 85841947962 ps
CPU time 2689.14 seconds
Started Jun 28 05:22:08 PM PDT 24
Finished Jun 28 06:06:58 PM PDT 24
Peak memory 286092 kb
Host smart-8097b440-76d5-4abb-8e4b-d65b577e14e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381071336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.381071336
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.795923149
Short name T316
Test name
Test status
Simulation time 24967508451 ps
CPU time 511.89 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 249384 kb
Host smart-42f0c18d-b46b-40cc-8bfb-30856030c9d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795923149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.795923149
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1894479324
Short name T74
Test name
Test status
Simulation time 446008852 ps
CPU time 15.3 seconds
Started Jun 28 05:21:56 PM PDT 24
Finished Jun 28 05:22:12 PM PDT 24
Peak memory 249272 kb
Host smart-cd2e1f05-9cb4-49be-8e49-2928b29efe17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18944
79324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1894479324
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2363987805
Short name T568
Test name
Test status
Simulation time 93310541 ps
CPU time 7.9 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:22:08 PM PDT 24
Peak memory 255140 kb
Host smart-30a42669-4502-4f92-bdf3-e11b58bab2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23639
87805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2363987805
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3177939559
Short name T91
Test name
Test status
Simulation time 1572510644 ps
CPU time 35.89 seconds
Started Jun 28 05:22:00 PM PDT 24
Finished Jun 28 05:22:37 PM PDT 24
Peak memory 249688 kb
Host smart-800a8d2b-e677-48cf-a481-9bf573f45bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31779
39559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3177939559
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2078784536
Short name T540
Test name
Test status
Simulation time 1927969761 ps
CPU time 65.71 seconds
Started Jun 28 05:21:59 PM PDT 24
Finished Jun 28 05:23:06 PM PDT 24
Peak memory 249284 kb
Host smart-dda9fd1b-c515-432f-b26a-bad87f8b26d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20787
84536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2078784536
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1394357090
Short name T245
Test name
Test status
Simulation time 441113260502 ps
CPU time 2138.5 seconds
Started Jun 28 05:22:11 PM PDT 24
Finished Jun 28 05:57:50 PM PDT 24
Peak memory 289960 kb
Host smart-6232eda5-add3-4720-864b-295ff63642b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394357090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1394357090
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.135113710
Short name T636
Test name
Test status
Simulation time 15619523706 ps
CPU time 1438.94 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:46:09 PM PDT 24
Peak memory 282168 kb
Host smart-fd5999c0-245c-4d9e-a5ea-32c26794904e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135113710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.135113710
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3954696421
Short name T674
Test name
Test status
Simulation time 4264122218 ps
CPU time 152.73 seconds
Started Jun 28 05:22:08 PM PDT 24
Finished Jun 28 05:24:41 PM PDT 24
Peak memory 257128 kb
Host smart-1cd9a3b4-a06e-42f7-a9bf-9b0a7ab13916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
96421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3954696421
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2656798080
Short name T31
Test name
Test status
Simulation time 184013001 ps
CPU time 12.49 seconds
Started Jun 28 05:22:11 PM PDT 24
Finished Jun 28 05:22:24 PM PDT 24
Peak memory 248644 kb
Host smart-0cbbd3c6-e339-449b-965d-473f4dbe2bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26567
98080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2656798080
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1171218356
Short name T239
Test name
Test status
Simulation time 50236019794 ps
CPU time 1593.94 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:48:44 PM PDT 24
Peak memory 274060 kb
Host smart-76c0a250-32db-4fc9-8d21-3dd8d185a6b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171218356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1171218356
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.756566848
Short name T308
Test name
Test status
Simulation time 8172135043 ps
CPU time 324.19 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:27:34 PM PDT 24
Peak memory 249388 kb
Host smart-a6cded0f-c191-4369-a6c6-2a9fa917ba89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756566848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.756566848
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1642582736
Short name T579
Test name
Test status
Simulation time 169839915 ps
CPU time 15.73 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:22:25 PM PDT 24
Peak memory 257388 kb
Host smart-d6f824f1-1fb9-4ee6-94ec-2e3dd6cc2846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
82736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1642582736
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3851963827
Short name T551
Test name
Test status
Simulation time 550499469 ps
CPU time 33.12 seconds
Started Jun 28 05:22:10 PM PDT 24
Finished Jun 28 05:22:44 PM PDT 24
Peak memory 249300 kb
Host smart-4c14083e-f90e-4d31-aa41-2ab648111b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
63827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3851963827
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1720259892
Short name T618
Test name
Test status
Simulation time 3317825803 ps
CPU time 41.17 seconds
Started Jun 28 05:22:10 PM PDT 24
Finished Jun 28 05:22:52 PM PDT 24
Peak memory 249400 kb
Host smart-12aa0a58-51a1-43fe-a894-be1bf08e6637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17202
59892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1720259892
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2555249491
Short name T445
Test name
Test status
Simulation time 4241484844 ps
CPU time 51.26 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:23:01 PM PDT 24
Peak memory 257512 kb
Host smart-82ce0393-c340-4abc-8978-5d7b3730142c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
49491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2555249491
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1370515794
Short name T276
Test name
Test status
Simulation time 63815126124 ps
CPU time 3876.25 seconds
Started Jun 28 05:22:08 PM PDT 24
Finished Jun 28 06:26:45 PM PDT 24
Peak memory 305624 kb
Host smart-4ad2948b-4ba7-49bd-926f-feb16194e525
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370515794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1370515794
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.687882953
Short name T80
Test name
Test status
Simulation time 70888576875 ps
CPU time 1960.14 seconds
Started Jun 28 05:22:08 PM PDT 24
Finished Jun 28 05:54:50 PM PDT 24
Peak memory 306604 kb
Host smart-950c269d-fc53-431e-a4fb-a256248567ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687882953 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.687882953
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2334909195
Short name T454
Test name
Test status
Simulation time 9981904169 ps
CPU time 854.06 seconds
Started Jun 28 05:22:24 PM PDT 24
Finished Jun 28 05:36:39 PM PDT 24
Peak memory 273944 kb
Host smart-5c4bb0be-ef44-4a37-9676-ccafc5728646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334909195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2334909195
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1659004381
Short name T494
Test name
Test status
Simulation time 2025015755 ps
CPU time 72.89 seconds
Started Jun 28 05:22:21 PM PDT 24
Finished Jun 28 05:23:34 PM PDT 24
Peak memory 256996 kb
Host smart-dedd6b85-ccfb-407f-9cfa-438b84c4b4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
04381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1659004381
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1346769626
Short name T438
Test name
Test status
Simulation time 896065857 ps
CPU time 27.63 seconds
Started Jun 28 05:22:22 PM PDT 24
Finished Jun 28 05:22:50 PM PDT 24
Peak memory 256976 kb
Host smart-dd79bf0c-b945-4324-b292-e62e961f211a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13467
69626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1346769626
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3925113200
Short name T288
Test name
Test status
Simulation time 127201238977 ps
CPU time 2234.91 seconds
Started Jun 28 05:22:22 PM PDT 24
Finished Jun 28 05:59:38 PM PDT 24
Peak memory 289592 kb
Host smart-7516a360-71dc-40f1-b722-89f524fc0757
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925113200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3925113200
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2073237921
Short name T440
Test name
Test status
Simulation time 100785924158 ps
CPU time 3567.72 seconds
Started Jun 28 05:22:24 PM PDT 24
Finished Jun 28 06:21:52 PM PDT 24
Peak memory 289908 kb
Host smart-554c13ac-c4c1-4411-b033-a0d781d78d88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073237921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2073237921
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2765561130
Short name T303
Test name
Test status
Simulation time 23881668956 ps
CPU time 255.16 seconds
Started Jun 28 05:22:23 PM PDT 24
Finished Jun 28 05:26:39 PM PDT 24
Peak memory 256040 kb
Host smart-3e4930fa-5d5c-49b2-931e-e778d8611dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765561130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2765561130
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1685384626
Short name T537
Test name
Test status
Simulation time 49879362 ps
CPU time 5.09 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 240920 kb
Host smart-bea8fe56-a145-4699-8274-a618ac9b88e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
84626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1685384626
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2975059065
Short name T83
Test name
Test status
Simulation time 16924052792 ps
CPU time 67.22 seconds
Started Jun 28 05:22:10 PM PDT 24
Finished Jun 28 05:23:18 PM PDT 24
Peak memory 256980 kb
Host smart-aec3a61a-f976-4efc-9c5d-e6eceadda869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29750
59065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2975059065
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.252178384
Short name T424
Test name
Test status
Simulation time 1544798268 ps
CPU time 50.36 seconds
Started Jun 28 05:22:24 PM PDT 24
Finished Jun 28 05:23:16 PM PDT 24
Peak memory 249208 kb
Host smart-15e76f5e-9002-4776-b3e4-1117a78b1b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25217
8384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.252178384
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4276277110
Short name T217
Test name
Test status
Simulation time 287113028 ps
CPU time 6.61 seconds
Started Jun 28 05:22:09 PM PDT 24
Finished Jun 28 05:22:16 PM PDT 24
Peak memory 251984 kb
Host smart-35b2c623-3c3b-4cd4-8891-ab501c8969ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42762
77110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4276277110
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3442971220
Short name T583
Test name
Test status
Simulation time 7348638212 ps
CPU time 773.28 seconds
Started Jun 28 05:22:20 PM PDT 24
Finished Jun 28 05:35:14 PM PDT 24
Peak memory 283132 kb
Host smart-4ec6257a-2ffa-451c-8458-68abdf39a4e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442971220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3442971220
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3799005642
Short name T161
Test name
Test status
Simulation time 61128163228 ps
CPU time 2161.61 seconds
Started Jun 28 05:22:21 PM PDT 24
Finished Jun 28 05:58:23 PM PDT 24
Peak memory 290400 kb
Host smart-38bc740d-8122-462f-82b1-7521499384b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799005642 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3799005642
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.555059261
Short name T274
Test name
Test status
Simulation time 7814148644 ps
CPU time 728.2 seconds
Started Jun 28 05:22:23 PM PDT 24
Finished Jun 28 05:34:31 PM PDT 24
Peak memory 268824 kb
Host smart-d9da0300-cc94-4433-8676-4720fffffde0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555059261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.555059261
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.501400962
Short name T624
Test name
Test status
Simulation time 14266000601 ps
CPU time 164.53 seconds
Started Jun 28 05:22:23 PM PDT 24
Finished Jun 28 05:25:08 PM PDT 24
Peak memory 256916 kb
Host smart-697a3924-10c6-4101-a625-74ee318000ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50140
0962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.501400962
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1561180603
Short name T264
Test name
Test status
Simulation time 1755477976 ps
CPU time 34.82 seconds
Started Jun 28 05:22:22 PM PDT 24
Finished Jun 28 05:22:57 PM PDT 24
Peak memory 257024 kb
Host smart-7099a7ad-93a1-4933-a9f7-681ba762aaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15611
80603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1561180603
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1519118243
Short name T407
Test name
Test status
Simulation time 50761621250 ps
CPU time 3092.91 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 06:14:15 PM PDT 24
Peak memory 290144 kb
Host smart-1fbf4517-ed2a-48b0-a663-b015afad9bb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519118243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1519118243
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2304571027
Short name T301
Test name
Test status
Simulation time 8924011542 ps
CPU time 191 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:25:53 PM PDT 24
Peak memory 249388 kb
Host smart-10ad7ec6-0154-43a2-a673-18300c6d8902
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304571027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2304571027
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3692486844
Short name T54
Test name
Test status
Simulation time 949465920 ps
CPU time 28.97 seconds
Started Jun 28 05:22:25 PM PDT 24
Finished Jun 28 05:22:55 PM PDT 24
Peak memory 256704 kb
Host smart-17fc3ad6-2494-4d2d-ac04-60716e48e452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
86844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3692486844
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3507260963
Short name T385
Test name
Test status
Simulation time 453971261 ps
CPU time 32.01 seconds
Started Jun 28 05:22:23 PM PDT 24
Finished Jun 28 05:22:55 PM PDT 24
Peak memory 249308 kb
Host smart-43733f0b-04fa-4026-97fd-43c72713573c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
60963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3507260963
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1525459884
Short name T352
Test name
Test status
Simulation time 603876443 ps
CPU time 50.88 seconds
Started Jun 28 05:22:20 PM PDT 24
Finished Jun 28 05:23:11 PM PDT 24
Peak memory 257344 kb
Host smart-d335cb2c-4f9f-4b58-96b4-dd9b00f788e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15254
59884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1525459884
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1448280220
Short name T410
Test name
Test status
Simulation time 2523417614 ps
CPU time 35.44 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:17 PM PDT 24
Peak memory 257604 kb
Host smart-ad235bcb-e700-4843-8d07-374b4277436c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448280220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1448280220
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.254609797
Short name T520
Test name
Test status
Simulation time 55406744089 ps
CPU time 3381.12 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 290288 kb
Host smart-9a2b2425-0dd3-453a-9c3c-694b0149d753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254609797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.254609797
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1026068067
Short name T614
Test name
Test status
Simulation time 3486049530 ps
CPU time 176.07 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:25:38 PM PDT 24
Peak memory 257608 kb
Host smart-e10f83a8-c523-49b6-a4d0-62e2ebc87453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
68067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1026068067
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1762236691
Short name T505
Test name
Test status
Simulation time 1518605497 ps
CPU time 40.7 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:22 PM PDT 24
Peak memory 249060 kb
Host smart-68b534df-7233-4f1c-a02a-e6ab0cfb7d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17622
36691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1762236691
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2140626650
Short name T655
Test name
Test status
Simulation time 43922161959 ps
CPU time 1407.37 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:46:09 PM PDT 24
Peak memory 273220 kb
Host smart-0bfdd881-57e3-4e62-a2ae-2ba8064ec53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140626650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2140626650
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4243743448
Short name T287
Test name
Test status
Simulation time 78938134641 ps
CPU time 2317.73 seconds
Started Jun 28 05:22:42 PM PDT 24
Finished Jun 28 06:01:21 PM PDT 24
Peak memory 273884 kb
Host smart-a8aa1fe7-2803-4247-8f40-10b34f87c524
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243743448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4243743448
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2245356834
Short name T661
Test name
Test status
Simulation time 8024338900 ps
CPU time 361.27 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:28:42 PM PDT 24
Peak memory 256244 kb
Host smart-4bd4b3f8-f40f-44d5-a4d5-fdf21fc95571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245356834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2245356834
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3018324239
Short name T490
Test name
Test status
Simulation time 1113591565 ps
CPU time 68.57 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:23:50 PM PDT 24
Peak memory 256788 kb
Host smart-482d029e-7818-4f50-80f5-d21e1d4fb46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30183
24239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3018324239
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3098373887
Short name T388
Test name
Test status
Simulation time 1728669006 ps
CPU time 55.77 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:23:37 PM PDT 24
Peak memory 248828 kb
Host smart-5bba84e7-2344-47ed-b9d3-9a1550b55793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
73887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3098373887
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.861199577
Short name T34
Test name
Test status
Simulation time 808921059 ps
CPU time 11.88 seconds
Started Jun 28 05:22:42 PM PDT 24
Finished Jun 28 05:22:55 PM PDT 24
Peak memory 248644 kb
Host smart-3b72e7d2-b287-4a5c-9a2c-e32fd28dd4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86119
9577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.861199577
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2071376582
Short name T640
Test name
Test status
Simulation time 283172075 ps
CPU time 20.23 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:03 PM PDT 24
Peak memory 257404 kb
Host smart-3c5859b4-0af3-4e2c-b80d-2f6223374fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20713
76582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2071376582
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1572241070
Short name T364
Test name
Test status
Simulation time 301741852 ps
CPU time 23.88 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:06 PM PDT 24
Peak memory 257396 kb
Host smart-b08512ca-9f03-4140-8455-83a610bebfec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572241070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1572241070
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2154130093
Short name T593
Test name
Test status
Simulation time 20608504721 ps
CPU time 1232.9 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:43:27 PM PDT 24
Peak memory 290348 kb
Host smart-315748fe-ab34-48e1-b9ed-e8996100f7ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154130093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2154130093
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2611901015
Short name T476
Test name
Test status
Simulation time 548654735 ps
CPU time 26.42 seconds
Started Jun 28 05:22:40 PM PDT 24
Finished Jun 28 05:23:08 PM PDT 24
Peak memory 248960 kb
Host smart-405eab11-1037-431c-9fc2-52e3c3bd2712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26119
01015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2611901015
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1153292676
Short name T70
Test name
Test status
Simulation time 187546104 ps
CPU time 10.85 seconds
Started Jun 28 05:22:39 PM PDT 24
Finished Jun 28 05:22:51 PM PDT 24
Peak memory 256312 kb
Host smart-108ab72f-2c75-4567-92ef-9446e9cff042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
92676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1153292676
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1646676977
Short name T336
Test name
Test status
Simulation time 14275570764 ps
CPU time 1314.04 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:44:47 PM PDT 24
Peak memory 289928 kb
Host smart-314e360a-248b-432b-ac34-c2cf21881eb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646676977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1646676977
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2537027697
Short name T35
Test name
Test status
Simulation time 187211157236 ps
CPU time 2675.9 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 06:07:30 PM PDT 24
Peak memory 289980 kb
Host smart-a35db28c-ed1f-4461-831d-f881189afdd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537027697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2537027697
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2310079030
Short name T509
Test name
Test status
Simulation time 72899941411 ps
CPU time 617.68 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:33:11 PM PDT 24
Peak memory 248212 kb
Host smart-81920817-2cf3-4674-ad5d-7c90b5ca0806
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310079030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2310079030
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3794501055
Short name T461
Test name
Test status
Simulation time 318176453 ps
CPU time 22.09 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:04 PM PDT 24
Peak memory 249300 kb
Host smart-dff896ca-0824-4bdb-9e1e-b208c320f9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37945
01055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3794501055
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1053003962
Short name T588
Test name
Test status
Simulation time 1554693239 ps
CPU time 42.35 seconds
Started Jun 28 05:22:41 PM PDT 24
Finished Jun 28 05:23:25 PM PDT 24
Peak memory 248756 kb
Host smart-a17399b6-aa10-4832-97ca-b5a30d07e37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
03962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1053003962
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2211903350
Short name T220
Test name
Test status
Simulation time 442237344 ps
CPU time 16.85 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:23:11 PM PDT 24
Peak memory 249296 kb
Host smart-24d1e739-64e3-4b36-9617-224821960e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22119
03350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2211903350
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3390884424
Short name T559
Test name
Test status
Simulation time 239576774 ps
CPU time 14.54 seconds
Started Jun 28 05:22:39 PM PDT 24
Finished Jun 28 05:22:55 PM PDT 24
Peak memory 254100 kb
Host smart-400f1813-74e0-4d89-b486-ee4be00c8221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
84424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3390884424
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1669018604
Short name T289
Test name
Test status
Simulation time 109263786331 ps
CPU time 1708.35 seconds
Started Jun 28 05:22:51 PM PDT 24
Finished Jun 28 05:51:21 PM PDT 24
Peak memory 290300 kb
Host smart-c8a7a9a0-c457-4509-88ae-7267e8842506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669018604 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1669018604
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3131798631
Short name T581
Test name
Test status
Simulation time 13727100730 ps
CPU time 648.29 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 273956 kb
Host smart-3781e863-0125-4712-a026-cea71977ff4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131798631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3131798631
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3423869745
Short name T690
Test name
Test status
Simulation time 13465743441 ps
CPU time 70.09 seconds
Started Jun 28 05:22:55 PM PDT 24
Finished Jun 28 05:24:05 PM PDT 24
Peak memory 257068 kb
Host smart-0f7df6c6-1ec3-4f58-af0e-e928a6c287ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34238
69745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3423869745
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.692009566
Short name T433
Test name
Test status
Simulation time 867935647 ps
CPU time 13.09 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:23:07 PM PDT 24
Peak memory 249304 kb
Host smart-ebea4970-74a0-45c5-8f44-55539c6a706d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69200
9566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.692009566
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1609208356
Short name T580
Test name
Test status
Simulation time 16204749829 ps
CPU time 1281.9 seconds
Started Jun 28 05:22:51 PM PDT 24
Finished Jun 28 05:44:14 PM PDT 24
Peak memory 273324 kb
Host smart-9e651ce2-46b4-4df3-b680-3caa1a0b288a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609208356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1609208356
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1644671173
Short name T630
Test name
Test status
Simulation time 35610225791 ps
CPU time 2019.46 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:56:32 PM PDT 24
Peak memory 289896 kb
Host smart-f4010b0c-14ef-45bc-bc4a-033dfef7ef6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644671173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1644671173
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4283147911
Short name T297
Test name
Test status
Simulation time 18735817322 ps
CPU time 403.16 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 249388 kb
Host smart-82765888-6cc3-4636-bd14-467fae8ad7b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283147911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4283147911
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.400212169
Short name T663
Test name
Test status
Simulation time 4270852820 ps
CPU time 28.96 seconds
Started Jun 28 05:22:51 PM PDT 24
Finished Jun 28 05:23:21 PM PDT 24
Peak memory 249424 kb
Host smart-712422f3-71cc-47f0-a0fe-868b161f76d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40021
2169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.400212169
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1042112560
Short name T594
Test name
Test status
Simulation time 2927826246 ps
CPU time 43.28 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:23:37 PM PDT 24
Peak memory 249420 kb
Host smart-8cf7aff9-d43c-4eef-bcec-744a2ac0373a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10421
12560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1042112560
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.110959181
Short name T600
Test name
Test status
Simulation time 1001661134 ps
CPU time 8.49 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:23:03 PM PDT 24
Peak memory 253116 kb
Host smart-bd20ee8f-03f0-4962-a30a-57ebe15899a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095
9181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.110959181
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4111245343
Short name T609
Test name
Test status
Simulation time 561955687 ps
CPU time 32.76 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:23:27 PM PDT 24
Peak memory 257440 kb
Host smart-7fa5dd55-087b-45ab-85df-c4f9422af36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41112
45343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4111245343
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4284554934
Short name T65
Test name
Test status
Simulation time 49195261860 ps
CPU time 2665.96 seconds
Started Jun 28 05:22:54 PM PDT 24
Finished Jun 28 06:07:21 PM PDT 24
Peak memory 289904 kb
Host smart-1efee5a7-efc7-43f8-aeb5-fddd0905e175
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284554934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4284554934
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1163247009
Short name T587
Test name
Test status
Simulation time 54151561702 ps
CPU time 2007.68 seconds
Started Jun 28 05:23:05 PM PDT 24
Finished Jun 28 05:56:34 PM PDT 24
Peak memory 286292 kb
Host smart-7859d506-98b8-4f6b-a752-2608845a952c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163247009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1163247009
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1058753084
Short name T285
Test name
Test status
Simulation time 6813727291 ps
CPU time 161.77 seconds
Started Jun 28 05:22:50 PM PDT 24
Finished Jun 28 05:25:33 PM PDT 24
Peak memory 257600 kb
Host smart-6f0537f2-c86a-458f-8772-8d01aa163d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10587
53084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1058753084
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1594080783
Short name T420
Test name
Test status
Simulation time 179596364 ps
CPU time 4.26 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:22:58 PM PDT 24
Peak memory 240596 kb
Host smart-df99be30-de1c-442e-a34a-2eb2ce995815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
80783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1594080783
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2657061294
Short name T335
Test name
Test status
Simulation time 30927405647 ps
CPU time 1816.15 seconds
Started Jun 28 05:23:07 PM PDT 24
Finished Jun 28 05:53:24 PM PDT 24
Peak memory 273484 kb
Host smart-a9d37d58-2db6-4078-a925-e74214651873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657061294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2657061294
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3714204760
Short name T684
Test name
Test status
Simulation time 342106244 ps
CPU time 11.15 seconds
Started Jun 28 05:22:55 PM PDT 24
Finished Jun 28 05:23:07 PM PDT 24
Peak memory 249272 kb
Host smart-5ef854b2-d732-47fd-b35f-c287d3711281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
04760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3714204760
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2107617619
Short name T596
Test name
Test status
Simulation time 249294199 ps
CPU time 15.44 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:23:09 PM PDT 24
Peak memory 248928 kb
Host smart-ad2b1a6f-8430-487f-8304-8452552de175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21076
17619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2107617619
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3735310848
Short name T647
Test name
Test status
Simulation time 2523442445 ps
CPU time 47.87 seconds
Started Jun 28 05:22:52 PM PDT 24
Finished Jun 28 05:23:41 PM PDT 24
Peak memory 249420 kb
Host smart-c01804bb-17a4-402d-a1ce-c3cbb7ee040d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
10848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3735310848
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1435753881
Short name T384
Test name
Test status
Simulation time 1074393700 ps
CPU time 25.18 seconds
Started Jun 28 05:22:53 PM PDT 24
Finished Jun 28 05:23:19 PM PDT 24
Peak memory 257152 kb
Host smart-3b7b5749-ff40-4b90-bb33-a5d6806110a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357
53881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1435753881
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2228530396
Short name T99
Test name
Test status
Simulation time 51388883278 ps
CPU time 5321.32 seconds
Started Jun 28 05:23:03 PM PDT 24
Finished Jun 28 06:51:46 PM PDT 24
Peak memory 354996 kb
Host smart-1b9c4ef9-b5e2-4c82-816f-fa1f854d89e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228530396 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2228530396
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1427787190
Short name T206
Test name
Test status
Simulation time 43061022 ps
CPU time 3.94 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:19:32 PM PDT 24
Peak memory 249524 kb
Host smart-488e20b1-44e9-43fd-a7de-14c90b778416
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427787190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1427787190
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3079147621
Short name T627
Test name
Test status
Simulation time 23334692906 ps
CPU time 1544.85 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:45:13 PM PDT 24
Peak memory 272872 kb
Host smart-e8ccfe71-73db-45f4-af0e-fb596af63448
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079147621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3079147621
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2822254897
Short name T238
Test name
Test status
Simulation time 175032159 ps
CPU time 10.16 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:19:34 PM PDT 24
Peak memory 249196 kb
Host smart-1af07b97-bab7-40f7-a3fb-fdfdab4864cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2822254897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2822254897
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1562340228
Short name T281
Test name
Test status
Simulation time 17283566265 ps
CPU time 97.93 seconds
Started Jun 28 05:19:28 PM PDT 24
Finished Jun 28 05:21:07 PM PDT 24
Peak memory 257116 kb
Host smart-8667342d-7eba-4739-89f8-bb719666c5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
40228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1562340228
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2440286298
Short name T524
Test name
Test status
Simulation time 213147992 ps
CPU time 21.53 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:19:48 PM PDT 24
Peak memory 248768 kb
Host smart-d203bc8f-9418-47c1-995d-ba86f2233684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
86298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2440286298
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.484735158
Short name T293
Test name
Test status
Simulation time 125696137840 ps
CPU time 1378.02 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:42:21 PM PDT 24
Peak memory 273108 kb
Host smart-03f43333-aa76-4b86-bdfd-6ad8aaf123f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484735158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.484735158
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2047242050
Short name T425
Test name
Test status
Simulation time 90651304920 ps
CPU time 1472.05 seconds
Started Jun 28 05:19:26 PM PDT 24
Finished Jun 28 05:44:00 PM PDT 24
Peak memory 273008 kb
Host smart-c9f9c5fb-2184-44c8-ab0f-73698307f52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047242050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2047242050
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1619656338
Short name T307
Test name
Test status
Simulation time 29552526759 ps
CPU time 314.23 seconds
Started Jun 28 05:19:24 PM PDT 24
Finished Jun 28 05:24:40 PM PDT 24
Peak memory 249488 kb
Host smart-128fdcb6-4ef8-4a33-9734-4db5f4ed0441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619656338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1619656338
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1794104242
Short name T514
Test name
Test status
Simulation time 1012049154 ps
CPU time 34.38 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:20:01 PM PDT 24
Peak memory 256844 kb
Host smart-d34514b0-e107-4c63-a973-bf9297c8a4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17941
04242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1794104242
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2224280516
Short name T589
Test name
Test status
Simulation time 784069049 ps
CPU time 44.86 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:20:09 PM PDT 24
Peak memory 248808 kb
Host smart-311c35f8-40b6-460b-a3f6-b3854293b7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
80516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2224280516
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3308953834
Short name T565
Test name
Test status
Simulation time 357370403 ps
CPU time 33.5 seconds
Started Jun 28 05:19:23 PM PDT 24
Finished Jun 28 05:19:57 PM PDT 24
Peak memory 256816 kb
Host smart-54c90fea-f6f0-4dd5-a76f-2e4ed0e8ec97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33089
53834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3308953834
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1138720279
Short name T538
Test name
Test status
Simulation time 46999338795 ps
CPU time 2502.25 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 06:01:11 PM PDT 24
Peak memory 288088 kb
Host smart-f3ed2f5e-9b13-4550-bff6-5bcd3ce85797
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138720279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1138720279
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.753373013
Short name T210
Test name
Test status
Simulation time 37171889 ps
CPU time 3.15 seconds
Started Jun 28 05:19:30 PM PDT 24
Finished Jun 28 05:19:33 PM PDT 24
Peak memory 249508 kb
Host smart-c59bf339-6897-466b-a41b-138e50936c3c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=753373013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.753373013
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.82710005
Short name T676
Test name
Test status
Simulation time 48254044083 ps
CPU time 2775.91 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 06:05:44 PM PDT 24
Peak memory 289356 kb
Host smart-1bb4212b-1fdb-4203-92b2-6be6353e921c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82710005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.82710005
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1852903453
Short name T654
Test name
Test status
Simulation time 1030955694 ps
CPU time 11.15 seconds
Started Jun 28 05:19:30 PM PDT 24
Finished Jun 28 05:19:42 PM PDT 24
Peak memory 249196 kb
Host smart-26380ac8-a017-40bc-b624-fb7dceac8143
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1852903453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1852903453
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3561897264
Short name T528
Test name
Test status
Simulation time 352703846 ps
CPU time 6.19 seconds
Started Jun 28 05:19:26 PM PDT 24
Finished Jun 28 05:19:34 PM PDT 24
Peak memory 255108 kb
Host smart-d5ddc832-fbbe-4093-834d-618a72e09160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35618
97264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3561897264
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.839980705
Short name T544
Test name
Test status
Simulation time 1996133583 ps
CPU time 28.33 seconds
Started Jun 28 05:19:30 PM PDT 24
Finished Jun 28 05:19:59 PM PDT 24
Peak memory 256828 kb
Host smart-08ee465c-6d99-4c4f-b1d3-80761c988a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83998
0705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.839980705
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1249102224
Short name T296
Test name
Test status
Simulation time 143731207093 ps
CPU time 2162.78 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:55:30 PM PDT 24
Peak memory 273324 kb
Host smart-63e85729-160f-4ed6-92e0-a77259a038f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249102224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1249102224
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1790106223
Short name T695
Test name
Test status
Simulation time 85128411796 ps
CPU time 1599.56 seconds
Started Jun 28 05:19:30 PM PDT 24
Finished Jun 28 05:46:10 PM PDT 24
Peak memory 290104 kb
Host smart-87a2ab6a-426c-47c6-8834-ce3927aae2cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790106223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1790106223
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1084030798
Short name T317
Test name
Test status
Simulation time 1360401247 ps
CPU time 56.93 seconds
Started Jun 28 05:19:25 PM PDT 24
Finished Jun 28 05:20:24 PM PDT 24
Peak memory 253904 kb
Host smart-d8652314-bcda-4af2-ae97-ffb22af7362e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084030798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1084030798
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1677489449
Short name T404
Test name
Test status
Simulation time 877535151 ps
CPU time 20.44 seconds
Started Jun 28 05:19:26 PM PDT 24
Finished Jun 28 05:19:48 PM PDT 24
Peak memory 257364 kb
Host smart-a7e9fe8f-3a3a-45c8-9092-28ed73cdd2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16774
89449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1677489449
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3335213748
Short name T649
Test name
Test status
Simulation time 941172345 ps
CPU time 21.18 seconds
Started Jun 28 05:19:28 PM PDT 24
Finished Jun 28 05:19:50 PM PDT 24
Peak memory 257428 kb
Host smart-29de5abd-f425-4183-9a48-fbfb1b7e79a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33352
13748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3335213748
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1800631787
Short name T256
Test name
Test status
Simulation time 622553620 ps
CPU time 37.87 seconds
Started Jun 28 05:19:26 PM PDT 24
Finished Jun 28 05:20:05 PM PDT 24
Peak memory 249548 kb
Host smart-5779211f-461b-47bd-988d-12a45888eb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
31787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1800631787
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.950323366
Short name T638
Test name
Test status
Simulation time 2054056477 ps
CPU time 22.09 seconds
Started Jun 28 05:19:27 PM PDT 24
Finished Jun 28 05:19:50 PM PDT 24
Peak memory 257380 kb
Host smart-2c16f703-9ef6-491a-a953-f79ae095154f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95032
3366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.950323366
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3362809203
Short name T69
Test name
Test status
Simulation time 276617404250 ps
CPU time 5840.97 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 06:57:00 PM PDT 24
Peak memory 322604 kb
Host smart-0b4233bd-e34a-4a40-a38d-e23b8041bd4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362809203 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3362809203
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3708741577
Short name T209
Test name
Test status
Simulation time 48782984 ps
CPU time 3.85 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:19:44 PM PDT 24
Peak memory 249564 kb
Host smart-4179ece1-8927-4e06-bb57-1510641fa909
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3708741577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3708741577
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1747851889
Short name T94
Test name
Test status
Simulation time 27225294920 ps
CPU time 1092.97 seconds
Started Jun 28 05:19:44 PM PDT 24
Finished Jun 28 05:37:57 PM PDT 24
Peak memory 282948 kb
Host smart-ff424a83-5158-487b-93bc-06c03526eb96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747851889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1747851889
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3722535720
Short name T496
Test name
Test status
Simulation time 3289799465 ps
CPU time 48.55 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:20:27 PM PDT 24
Peak memory 249324 kb
Host smart-106121d5-f306-4e04-ba6b-0239f437729b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3722535720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3722535720
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3348860013
Short name T584
Test name
Test status
Simulation time 9180810942 ps
CPU time 134.12 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:21:55 PM PDT 24
Peak memory 257280 kb
Host smart-bb4daa5b-368b-41d7-95eb-70c1c4cbc39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488
60013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3348860013
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3859081903
Short name T616
Test name
Test status
Simulation time 116570157 ps
CPU time 9.71 seconds
Started Jun 28 05:19:42 PM PDT 24
Finished Jun 28 05:19:53 PM PDT 24
Peak memory 249144 kb
Host smart-96384b49-0a05-4baa-8e01-a524210512d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
81903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3859081903
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2059101374
Short name T527
Test name
Test status
Simulation time 45073535257 ps
CPU time 1147.89 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:38:49 PM PDT 24
Peak memory 270916 kb
Host smart-d41b73ee-1297-4cc1-82c9-336d1be59ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059101374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2059101374
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2819235611
Short name T660
Test name
Test status
Simulation time 10522840467 ps
CPU time 422.02 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:26:43 PM PDT 24
Peak memory 248256 kb
Host smart-f76c112b-02a0-4a5c-8b83-55083cda5958
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819235611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2819235611
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3265053761
Short name T395
Test name
Test status
Simulation time 424770955 ps
CPU time 26.69 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:20:05 PM PDT 24
Peak memory 249300 kb
Host smart-431410db-b304-49de-9b66-0faa22e5239a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32650
53761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3265053761
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.350336884
Short name T635
Test name
Test status
Simulation time 658415400 ps
CPU time 34.19 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:20:12 PM PDT 24
Peak memory 248808 kb
Host smart-a9df146e-14d3-42ac-8e35-bb8f2b83dafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
6884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.350336884
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2124692148
Short name T386
Test name
Test status
Simulation time 1433346408 ps
CPU time 37.52 seconds
Started Jun 28 05:19:43 PM PDT 24
Finished Jun 28 05:20:21 PM PDT 24
Peak memory 257080 kb
Host smart-473b61a6-7f6f-4d29-b23b-f9ddbf2bb2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21246
92148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2124692148
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4151869214
Short name T383
Test name
Test status
Simulation time 340495332 ps
CPU time 6.26 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:19:47 PM PDT 24
Peak memory 249244 kb
Host smart-ebfe2f0d-231a-44fa-b80e-cebfdec3ebed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518
69214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4151869214
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2261003996
Short name T260
Test name
Test status
Simulation time 402382949569 ps
CPU time 5083.25 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 06:44:24 PM PDT 24
Peak memory 322264 kb
Host smart-25938ea7-30fc-4a3b-8916-92db2e36c97f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261003996 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2261003996
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2463762371
Short name T198
Test name
Test status
Simulation time 44900173 ps
CPU time 2.23 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:19:43 PM PDT 24
Peak memory 249520 kb
Host smart-f5995af5-85ab-49d7-8d9a-44568fcc89fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2463762371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2463762371
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3957525471
Short name T429
Test name
Test status
Simulation time 2967168637 ps
CPU time 28.93 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:20:07 PM PDT 24
Peak memory 249332 kb
Host smart-300d9d17-1dd3-44c6-a9f9-ab40f29e6593
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3957525471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3957525471
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1988200819
Short name T541
Test name
Test status
Simulation time 1142174781 ps
CPU time 108.63 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:21:26 PM PDT 24
Peak memory 257484 kb
Host smart-084d43fb-ac4b-4452-b958-70263e09c6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19882
00819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1988200819
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.4238092942
Short name T549
Test name
Test status
Simulation time 2290460643 ps
CPU time 34.94 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:20:14 PM PDT 24
Peak memory 249348 kb
Host smart-cc904256-b798-4ec5-96ac-97d2dbfaccae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
92942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.4238092942
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.235776331
Short name T575
Test name
Test status
Simulation time 28552151618 ps
CPU time 573.09 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:29:13 PM PDT 24
Peak memory 273656 kb
Host smart-602a461d-c167-4463-b46d-d24b7ab8116a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235776331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.235776331
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3569449863
Short name T163
Test name
Test status
Simulation time 43535229761 ps
CPU time 2391.68 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:59:31 PM PDT 24
Peak memory 290284 kb
Host smart-08b785a3-7a51-4a90-a4cd-2673ab009e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569449863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3569449863
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4096646328
Short name T379
Test name
Test status
Simulation time 2045066480 ps
CPU time 33.27 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:20:14 PM PDT 24
Peak memory 257368 kb
Host smart-3c4ad8c5-56b8-4964-b08a-15c03be55f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40966
46328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4096646328
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2744509492
Short name T55
Test name
Test status
Simulation time 4420252781 ps
CPU time 59.26 seconds
Started Jun 28 05:19:42 PM PDT 24
Finished Jun 28 05:20:42 PM PDT 24
Peak memory 256632 kb
Host smart-ba5be27d-2078-4001-8866-d17014be6f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27445
09492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2744509492
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.942391348
Short name T625
Test name
Test status
Simulation time 370334975 ps
CPU time 27.26 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:20:05 PM PDT 24
Peak memory 248812 kb
Host smart-ec42d3b2-f4d2-4200-a55e-7881c14c6b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94239
1348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.942391348
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3837492236
Short name T381
Test name
Test status
Simulation time 4872804066 ps
CPU time 59.91 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:20:39 PM PDT 24
Peak memory 257388 kb
Host smart-3ebed91e-5209-4e13-a365-907bc27be63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38374
92236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3837492236
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2753292811
Short name T255
Test name
Test status
Simulation time 52025497252 ps
CPU time 2893.99 seconds
Started Jun 28 05:19:43 PM PDT 24
Finished Jun 28 06:07:58 PM PDT 24
Peak memory 290224 kb
Host smart-dae6d634-798d-4ee4-89f4-d60ef3c9b8ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753292811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2753292811
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4217155283
Short name T207
Test name
Test status
Simulation time 35076046 ps
CPU time 2.1 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:19:39 PM PDT 24
Peak memory 249508 kb
Host smart-4ea2b1ea-c1f6-4a9b-9d8c-c3f7f2e3125c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4217155283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4217155283
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2632925874
Short name T448
Test name
Test status
Simulation time 7359082265 ps
CPU time 681.35 seconds
Started Jun 28 05:19:40 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 273928 kb
Host smart-021870d0-876b-42e5-97d5-630e0543f728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632925874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2632925874
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.680382308
Short name T519
Test name
Test status
Simulation time 5523235553 ps
CPU time 17.04 seconds
Started Jun 28 05:19:36 PM PDT 24
Finished Jun 28 05:19:53 PM PDT 24
Peak memory 249400 kb
Host smart-a0d4a1b4-245c-4936-a88c-f0f84a727e4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=680382308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.680382308
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3109436595
Short name T367
Test name
Test status
Simulation time 3888614117 ps
CPU time 91.51 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:21:10 PM PDT 24
Peak memory 256652 kb
Host smart-62c84021-af28-45e6-90b1-887bf94922f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
36595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3109436595
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1347377977
Short name T646
Test name
Test status
Simulation time 482627020 ps
CPU time 18.36 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:19:59 PM PDT 24
Peak memory 248260 kb
Host smart-b754c771-5083-449d-ad20-10536c585838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13473
77977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1347377977
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2032885066
Short name T229
Test name
Test status
Simulation time 136075968658 ps
CPU time 1518.78 seconds
Started Jun 28 05:19:37 PM PDT 24
Finished Jun 28 05:44:56 PM PDT 24
Peak memory 289756 kb
Host smart-90f07cad-4f7c-4cbd-853e-4edcd728ba40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032885066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2032885066
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2704762211
Short name T499
Test name
Test status
Simulation time 8819317621 ps
CPU time 179.61 seconds
Started Jun 28 05:19:43 PM PDT 24
Finished Jun 28 05:22:43 PM PDT 24
Peak memory 249384 kb
Host smart-1ef313db-b4e0-4d1d-a324-d6c3e3e5d7a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704762211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2704762211
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2805810221
Short name T615
Test name
Test status
Simulation time 605934298 ps
CPU time 18.36 seconds
Started Jun 28 05:19:41 PM PDT 24
Finished Jun 28 05:20:00 PM PDT 24
Peak memory 255800 kb
Host smart-9d65bf92-53a9-446b-84f5-25530f919825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
10221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2805810221
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3543043128
Short name T450
Test name
Test status
Simulation time 375233878 ps
CPU time 28.69 seconds
Started Jun 28 05:19:38 PM PDT 24
Finished Jun 28 05:20:08 PM PDT 24
Peak memory 249048 kb
Host smart-fc5e408a-db79-4b4d-a135-d8d5bdb8da9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
43128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3543043128
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1564320125
Short name T694
Test name
Test status
Simulation time 1150813213 ps
CPU time 31.57 seconds
Started Jun 28 05:19:39 PM PDT 24
Finished Jun 28 05:20:12 PM PDT 24
Peak memory 249228 kb
Host smart-0cbeb9a0-0f11-4086-91ad-2959aa43e6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
20125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1564320125
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3582431347
Short name T681
Test name
Test status
Simulation time 201685105 ps
CPU time 13.39 seconds
Started Jun 28 05:19:42 PM PDT 24
Finished Jun 28 05:19:56 PM PDT 24
Peak memory 249248 kb
Host smart-f07b97b4-6763-4f06-96b6-1e1a3c767879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35824
31347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3582431347
Directory /workspace/9.alert_handler_smoke/latest
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