Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61283134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29642605

1

T1

73583

T2

106417

T3

106436

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13739186	1			T1	29183		T2	41346		T3	42369
values[0x0]	37760004	1			T1	102045		T2	148105		T3	147212
values[0x1]	39426549	1			T1	102403		T2	147175		T3	146814

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52480089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38445650

1

T1

93025

T2

134538

T3

134853

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	281315	1			T2	1396		T3	1273		T5	38
valid_sources[0x01]	501925	1			T2	1447		T3	1330		T5	42
valid_sources[0x02]	272246	1			T2	1398		T3	1294		T5	36
valid_sources[0x03]	284382	1			T2	1350		T3	1348		T4	6
valid_sources[0x04]	289072	1			T2	1333		T3	1459		T4	1
valid_sources[0x05]	283612	1			T2	1381		T3	1354		T4	1
valid_sources[0x06]	1058525	1			T2	1070		T3	1305		T4	2
valid_sources[0x07]	283532	1			T2	1052		T3	1371		T4	2
valid_sources[0x08]	273961	1			T2	1254		T3	1337		T4	4
valid_sources[0x09]	273062	1			T2	1265		T3	1294		T5	31
valid_sources[0x0a]	278057	1			T2	1201		T3	1396		T5	34
valid_sources[0x0b]	710853	1			T2	1134		T3	1309		T4	1
valid_sources[0x0c]	280425	1			T2	1405		T3	1381		T4	4
valid_sources[0x0d]	288327	1			T2	1249		T3	1420		T4	2
valid_sources[0x0e]	272928	1			T2	761		T3	1282		T5	50
valid_sources[0x0f]	274118	1			T2	1303		T3	1349		T4	3
valid_sources[0x10]	287119	1			T2	1322		T3	1399		T4	1
valid_sources[0x11]	275490	1			T2	1443		T3	1363		T4	4
valid_sources[0x12]	278838	1			T2	1307		T3	1440		T5	43
valid_sources[0x13]	506742	1			T2	1543		T3	1266		T5	55
valid_sources[0x14]	285107	1			T2	1569		T3	1312		T5	38
valid_sources[0x15]	300486	1			T2	1032		T3	1147		T4	2
valid_sources[0x16]	289500	1			T2	1306		T3	1315		T5	39
valid_sources[0x17]	272769	1			T2	1329		T3	1360		T4	2
valid_sources[0x18]	285959	1			T2	1360		T3	1326		T4	1
valid_sources[0x19]	493761	1			T2	940		T3	1331		T4	1
valid_sources[0x1a]	276832	1			T2	1286		T3	1293		T4	3
valid_sources[0x1b]	278340	1			T2	1312		T3	1499		T5	46
valid_sources[0x1c]	280696	1			T2	1356		T3	1289		T4	3
valid_sources[0x1d]	285991	1			T2	1659		T3	1389		T5	41
valid_sources[0x1e]	277720	1			T2	1510		T3	1242		T5	44
valid_sources[0x1f]	1196333	1			T2	1219		T3	1395		T4	1
valid_sources[0x20]	273469	1			T2	964		T3	1294		T5	43
valid_sources[0x21]	287425	1			T2	1599		T3	1270		T4	2
valid_sources[0x22]	277865	1			T2	1436		T3	1266		T4	1
valid_sources[0x23]	670579	1			T2	1176		T3	1323		T4	1
valid_sources[0x24]	276654	1			T2	1256		T3	1271		T5	55
valid_sources[0x25]	322227	1			T2	1637		T3	1426		T5	61
valid_sources[0x26]	277235	1			T2	1280		T3	1229		T4	1
valid_sources[0x27]	283580	1			T2	1214		T3	1277		T4	4
valid_sources[0x28]	273398	1			T2	1607		T3	1239		T4	2
valid_sources[0x29]	496801	1			T2	1225		T3	1331		T4	1
valid_sources[0x2a]	277629	1			T2	1123		T3	1238		T5	35
valid_sources[0x2b]	280552	1			T2	1384		T3	1295		T4	1
valid_sources[0x2c]	295506	1			T2	1450		T3	1353		T4	1
valid_sources[0x2d]	286527	1			T2	1411		T3	1289		T5	43
valid_sources[0x2e]	289478	1			T2	1380		T3	1303		T4	2
valid_sources[0x2f]	279727	1			T2	1427		T3	1239		T4	2
valid_sources[0x30]	714702	1			T2	1334		T3	1356		T4	2
valid_sources[0x31]	758346	1			T2	1298		T3	1270		T4	1
valid_sources[0x32]	281653	1			T2	1234		T3	1352		T5	40
valid_sources[0x33]	284389	1			T2	1232		T3	1342		T4	3
valid_sources[0x34]	297483	1			T2	1703		T3	1363		T4	2
valid_sources[0x35]	271807	1			T2	1312		T3	1253		T4	4
valid_sources[0x36]	287448	1			T2	1376		T3	1268		T4	1
valid_sources[0x37]	740039	1			T2	1310		T3	1220		T4	1
valid_sources[0x38]	280177	1			T2	1263		T3	1364		T4	3
valid_sources[0x39]	297722	1			T2	1755		T3	1294		T4	2
valid_sources[0x3a]	282634	1			T2	1352		T3	1373		T4	1
valid_sources[0x3b]	272224	1			T2	1515		T3	1334		T4	1
valid_sources[0x3c]	275774	1			T2	1012		T3	1323		T4	8
valid_sources[0x3d]	281288	1			T2	1109		T3	1330		T4	4
valid_sources[0x3e]	272909	1			T2	1295		T3	1302		T5	39
valid_sources[0x3f]	307870	1			T2	1691		T3	1322		T4	4
valid_sources[0x40]	290494	1			T2	1178		T3	1386		T5	53
valid_sources[0x41]	281396	1			T2	1164		T3	1323		T4	1
valid_sources[0x42]	288096	1			T2	1285		T3	1349		T4	3
valid_sources[0x43]	282165	1			T2	1311		T3	1307		T4	1
valid_sources[0x44]	869886	1			T1	233631		T2	1118		T3	1352
valid_sources[0x45]	289798	1			T2	1413		T3	1256		T4	3
valid_sources[0x46]	281689	1			T2	1560		T3	1304		T4	7
valid_sources[0x47]	277402	1			T2	1385		T3	1276		T4	3
valid_sources[0x48]	271904	1			T2	1275		T3	1283		T4	3
valid_sources[0x49]	283897	1			T2	1340		T3	1288		T4	3
valid_sources[0x4a]	280657	1			T2	1285		T3	1315		T5	35
valid_sources[0x4b]	281235	1			T2	1395		T3	1333		T5	47
valid_sources[0x4c]	271148	1			T2	1382		T3	1337		T5	32
valid_sources[0x4d]	276616	1			T2	1295		T3	1255		T4	1
valid_sources[0x4e]	288812	1			T2	1274		T3	1348		T4	2
valid_sources[0x4f]	270447	1			T2	1203		T3	1327		T4	1
valid_sources[0x50]	268974	1			T2	1441		T3	1331		T4	7
valid_sources[0x51]	290306	1			T2	1438		T3	1368		T4	6
valid_sources[0x52]	276177	1			T2	1388		T3	1328		T4	3
valid_sources[0x53]	280845	1			T2	1293		T3	1343		T4	1
valid_sources[0x54]	278119	1			T2	1171		T3	1252		T4	1
valid_sources[0x55]	273471	1			T2	1763		T3	1242		T5	29
valid_sources[0x56]	276805	1			T2	1368		T3	1390		T4	8
valid_sources[0x57]	278277	1			T2	1326		T3	1390		T4	2
valid_sources[0x58]	282333	1			T2	1538		T3	1287		T4	2
valid_sources[0x59]	284613	1			T2	1296		T3	1276		T4	2
valid_sources[0x5a]	280700	1			T2	1391		T3	1280		T5	38
valid_sources[0x5b]	549648	1			T2	1051		T3	1385		T4	2
valid_sources[0x5c]	534370	1			T2	1274		T3	1380		T4	1
valid_sources[0x5d]	273188	1			T2	1400		T3	1402		T4	1
valid_sources[0x5e]	275615	1			T2	1753		T3	1310		T4	1
valid_sources[0x5f]	722081	1			T2	1565		T3	1362		T4	2
valid_sources[0x60]	279283	1			T2	1437		T3	1343		T5	40
valid_sources[0x61]	1020920	1			T2	1381		T3	1297		T4	4
valid_sources[0x62]	272320	1			T2	1075		T3	1298		T4	1
valid_sources[0x63]	616761	1			T2	1373		T3	1356		T4	6
valid_sources[0x64]	280491	1			T2	1225		T3	1289		T4	3
valid_sources[0x65]	561200	1			T2	1430		T3	1319		T5	30
valid_sources[0x66]	669671	1			T2	1590		T3	1351		T5	39
valid_sources[0x67]	700705	1			T2	1622		T3	1361		T4	1
valid_sources[0x68]	278698	1			T2	1190		T3	1364		T5	53
valid_sources[0x69]	289497	1			T2	1240		T3	1322		T4	1
valid_sources[0x6a]	271909	1			T2	946		T3	1348		T4	1
valid_sources[0x6b]	276699	1			T2	881		T3	1357		T4	3
valid_sources[0x6c]	591700	1			T2	1098		T3	1289		T4	5
valid_sources[0x6d]	279226	1			T2	1278		T3	1216		T5	29
valid_sources[0x6e]	700590	1			T2	1111		T3	1369		T5	50
valid_sources[0x6f]	584949	1			T2	1195		T3	1353		T4	1
valid_sources[0x70]	271496	1			T2	1289		T3	1315		T4	1
valid_sources[0x71]	282904	1			T2	1381		T3	1335		T4	1
valid_sources[0x72]	293366	1			T2	1586		T3	1312		T4	1
valid_sources[0x73]	281815	1			T2	1232		T3	1237		T5	40
valid_sources[0x74]	287007	1			T2	1587		T3	1375		T5	29
valid_sources[0x75]	274036	1			T2	1344		T3	1376		T5	43
valid_sources[0x76]	280031	1			T2	1224		T3	1368		T5	43
valid_sources[0x77]	273273	1			T2	1300		T3	1300		T4	1
valid_sources[0x78]	280911	1			T2	1399		T3	1300		T4	4
valid_sources[0x79]	275364	1			T2	938		T3	1322		T4	2
valid_sources[0x7a]	280398	1			T2	1399		T3	1319		T4	1
valid_sources[0x7b]	290011	1			T2	1411		T3	1255		T4	2
valid_sources[0x7c]	282549	1			T2	1506		T3	1196		T4	2
valid_sources[0x7d]	289363	1			T2	1215		T3	1392		T4	2
valid_sources[0x7e]	312206	1			T2	1266		T3	1284		T4	3
valid_sources[0x7f]	293808	1			T2	1311		T3	1370		T4	1
valid_sources[0x80]	273921	1			T2	981		T3	1232		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6820082

1

T1

14555

T2

20539

T3

21124

values[0x0]

all_enables

biggest_size

14425478

1

T1

37789

T2

55030

T3

54556

values[0x1]

all_enables

biggest_size

8397045

1

T1

21239

T2

30848

T3

30756