Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T61,T204
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11887	0	0
DisabledNoTrigBkwd_A	2147483647	798969	0	0
DisabledNoTrigFwd_A	2147483647	1400766832	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11887	0	0
T16	1107	336	0	0
T25	6157	0	0	0
T29	101917	0	0	0
T50	153234	0	0	0
T51	128801	0	0	0
T52	33392	0	0	0
T61	0	872	0	0
T87	431173	0	0	0
T88	43499	0	0	0
T89	638673	0	0	0
T90	31745	0	0	0
T119	125117	0	0	0
T120	130275	0	0	0
T204	0	616	0	0
T205	1403	670	0	0
T206	2813	442	0	0
T207	0	486	0	0
T208	0	780	0	0
T209	0	663	0	0
T210	0	156	0	0
T211	0	329	0	0
T212	0	1266	0	0
T213	0	699	0	0
T214	0	613	0	0
T215	0	504	0	0
T216	0	498	0	0
T217	0	1284	0	0
T218	0	926	0	0
T219	0	430	0	0
T220	0	163	0	0
T221	0	154	0	0
T222	200445	0	0	0
T223	30128	0	0	0
T224	322846	0	0	0
T225	560275	0	0	0
T226	7133	0	0	0
T227	104958	0	0	0
T228	32047	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	798969	0	0
T1	722500	698	0	0
T2	615768	2	0	0
T3	1553816	5354	0	0
T4	108388	0	0	0
T5	3464280	20	0	0
T9	62466	0	0	0
T12	1106212	1699	0	0
T13	390798	927	0	0
T14	0	5615	0	0
T15	0	3	0	0
T16	4428	4	0	0
T17	1233536	2368	0	0
T18	17340	0	0	0
T19	1379956	210	0	0
T33	0	10	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	83	0	0
T39	0	3	0	0
T40	0	3323	0	0
T41	0	17	0	0
T42	0	199	0	0
T43	0	51	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1400766832	0	0
T1	2890000	2178432	0	0
T2	1231536	928802	0	0
T3	1553816	1464213	0	0
T4	108388	29062	0	0
T5	3464280	1849844	0	0
T12	1106212	859003	0	0
T16	4428	2532	0	0
T17	1233536	1405795	0	0
T18	17340	10365	0	0
T19	1379956	1014006	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T208,T210
1	1	Covered	T3,T5,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	640540413	3502	0	0
DisabledNoTrigBkwd_A	640540413	283503	0	0
DisabledNoTrigFwd_A	640540413	308147987	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	3502	0	0
T25	6157	0	0	0
T29	101917	0	0	0
T50	153234	0	0	0
T87	431173	0	0	0
T119	125117	0	0	0
T205	1403	670	0	0
T208	0	780	0	0
T210	0	156	0	0
T213	0	699	0	0
T214	0	613	0	0
T219	0	430	0	0
T221	0	154	0	0
T222	200445	0	0	0
T223	30128	0	0	0
T224	322846	0	0	0
T225	560275	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	283503	0	0
T3	388454	17	0	0
T4	27097	0	0	0
T5	866070	19	0	0
T9	20822	0	0	0
T12	276553	1699	0	0
T13	195399	907	0	0
T14	0	379	0	0
T16	1107	0	0	0
T17	308384	1358	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T33	0	10	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	60	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	308147987	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	352222	0	0
T4	27097	704	0	0
T5	866070	143568	0	0
T12	276553	29749	0	0
T16	1107	627	0	0
T17	308384	371769	0	0
T18	4335	2010	0	0
T19	344989	338061	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T12
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T207,T211
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	640540413	3039	0	0
DisabledNoTrigBkwd_A	640540413	149471	0	0
DisabledNoTrigFwd_A	640540413	336873247	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	3039	0	0
T51	128801	0	0	0
T52	33392	0	0	0
T88	43499	0	0	0
T89	638673	0	0	0
T90	31745	0	0	0
T120	130275	0	0	0
T206	2813	442	0	0
T207	0	486	0	0
T211	0	329	0	0
T216	0	498	0	0
T217	0	1284	0	0
T226	7133	0	0	0
T227	104958	0	0	0
T228	32047	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	149471	0	0
T2	307884	2	0	0
T3	388454	4147	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	8	0	0
T14	0	4720	0	0
T16	1107	0	0	0
T17	308384	1010	0	0
T18	4335	0	0	0
T19	344989	210	0	0
T36	0	2	0	0
T38	0	23	0	0
T40	0	3323	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	336873247	0	0
T1	722500	722425	0	0
T2	307884	5973	0	0
T3	388454	230684	0	0
T4	27097	708	0	0
T5	866070	792652	0	0
T12	276553	276547	0	0
T16	1107	631	0	0
T17	308384	424197	0	0
T18	4335	2027	0	0
T19	344989	10178	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T209,T212
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	640540413	2932	0	0
DisabledNoTrigBkwd_A	640540413	173900	0	0
DisabledNoTrigFwd_A	640540413	396321337	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	2932	0	0
T6	215468	0	0	0
T9	20822	0	0	0
T13	195399	0	0	0
T16	1107	336	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	73386	0	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T209	0	663	0	0
T212	0	1266	0	0
T215	0	504	0	0
T220	0	163	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	173900	0	0
T1	722500	698	0	0
T2	307884	0	0	0
T3	388454	1190	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	12	0	0
T14	0	516	0	0
T15	0	3	0	0
T16	1107	4	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	3	0	0
T41	0	17	0	0
T42	0	199	0	0
T43	0	51	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	396321337	0	0
T1	722500	12213	0	0
T2	307884	307477	0	0
T3	388454	500302	0	0
T4	27097	712	0	0
T5	866070	866020	0	0
T12	276553	276160	0	0
T16	1107	635	0	0
T17	308384	306832	0	0
T18	4335	4272	0	0
T19	344989	324181	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T61,T204,T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	640540413	2414	0	0
DisabledNoTrigBkwd_A	640540413	192095	0	0
DisabledNoTrigFwd_A	640540413	359424261	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	2414	0	0
T7	119569	0	0	0
T8	504649	0	0	0
T26	6327	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T61	3337	872	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T204	0	616	0	0
T218	0	926	0	0
T229	65207	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	192095	0	0
T3	388454	1266	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	961	0	0
T14	0	1057	0	0
T15	0	5828	0	0
T16	1107	0	0	0
T17	308384	23	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1627	0	0
T43	0	81	0	0
T60	0	6156	0	0
T61	0	30	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	359424261	0	0
T1	722500	721369	0	0
T2	307884	307477	0	0
T3	388454	381005	0	0
T4	27097	26938	0	0
T5	866070	47604	0	0
T12	276553	276547	0	0
T16	1107	639	0	0
T17	308384	302997	0	0
T18	4335	2056	0	0
T19	344989	341586	0	0