Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T17
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T3,T12,T17
1	1	1	Covered	T3,T17,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T17,T20
0	1	Covered	T3,T20,T14
1	0	Covered	T15,T21,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T20
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T21,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Not Covered
1	1	Covered	T3,T20,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T3,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T17,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T2,T3,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T17,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T17,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T23,T24,T25
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T26,T27,T28
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T14,T27,T29
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T13,T20,T14
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T17,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T17,T20
TimeoutSt->Phase0St	172	Covered	T3,T20,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T23,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T27,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T20,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T13,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	800	0	0
CheckAccumTrig0_A	2147483647	2341	0	0
CheckAccumTrig1_A	2147483647	104	0	0
CheckClr_A	2147483647	1136	0	0
CheckEn_A	2147483647	1073865720	0	0
CheckPhase0_A	2147483647	2620	0	0
CheckPhase1_A	2147483647	2570	0	0
CheckPhase2_A	2147483647	2521	0	0
CheckPhase3_A	2147483647	2464	0	0
CheckTimeout0_A	2147483647	5240	0	0
CheckTimeoutSt1_A	2147483647	560213	0	0
CheckTimeoutSt2_A	2147483647	4896	0	0
CheckTimeoutStTrig_A	2147483647	232	0	0
ErrorStAllEscAsserted_A	2147483647	4362	0	0
ErrorStIsTerminal_A	2147483647	3642	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	800	0	0
T6	861872	0	0	0
T9	83288	137	0	0
T10	0	165	0	0
T11	0	121	0	0
T13	781596	0	0	0
T14	3950352	0	0	0
T20	293544	0	0	0
T30	0	291	0	0
T31	0	86	0	0
T32	37252	0	0	0
T33	118444	0	0	0
T34	132408	0	0	0
T35	20248	0	0	0
T36	46584	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T1	722500	1	0	0
T2	615768	1	0	0
T3	1553816	8	0	0
T4	108388	0	0	0
T5	3464280	2	0	0
T9	62466	0	0	0
T12	1106212	1	0	0
T13	390798	5	0	0
T14	0	9	0	0
T15	0	1	0	0
T16	4428	1	0	0
T17	1233536	6	0	0
T18	17340	0	0	0
T19	1379956	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	9	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104	0	0
T7	119569	0	0	0
T15	420122	2	0	0
T21	0	1	0	0
T22	800180	5	0	0
T24	0	2	0	0
T28	0	1	0	0
T40	441747	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T44	76566	1	0	0
T45	204793	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	167079	0	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T64	44530	0	0	0
T65	31008	0	0	0
T66	81296	0	0	0
T67	306676	0	0	0
T68	1102978	0	0	0
T69	327766	0	0	0
T70	74698	0	0	0
T71	68024	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1136	0	0
T3	776908	2	0	0
T4	54194	0	0	0
T5	1732140	0	0	0
T6	430936	0	0	0
T9	41644	0	0	0
T12	553106	0	0	0
T13	586197	2	0	0
T14	1975176	5	0	0
T15	0	8	0	0
T16	2214	0	0	0
T17	616768	0	0	0
T18	8670	0	0	0
T19	689978	0	0	0
T20	146772	4	0	0
T22	0	4	0	0
T23	0	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	18626	0	0	0
T33	59222	0	0	0
T34	66204	0	0	0
T35	10124	0	0	0
T36	23292	1	0	0
T37	199454	1	0	0
T38	25082	7	0	0
T41	0	1	0	0
T45	0	3	0	0
T60	0	2	0	0
T62	0	1	0	0
T68	0	1	0	0
T72	0	6	0	0
T73	0	7	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073865720	0	0
T1	2890000	2175590	0	0
T2	1231536	928802	0	0
T3	1553816	1385977	0	0
T4	108388	29057	0	0
T5	3464280	1098706	0	0
T12	1106212	846174	0	0
T16	4428	2532	0	0
T17	1233536	1404487	0	0
T18	17340	10364	0	0
T19	1379956	1014003	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T1	722500	1	0	0
T2	615768	1	0	0
T3	1553816	10	0	0
T4	108388	0	0	0
T5	3464280	2	0	0
T9	62466	0	0	0
T12	1106212	1	0	0
T13	390798	5	0	0
T14	0	11	0	0
T15	0	4	0	0
T16	4428	1	0	0
T17	1233536	6	0	0
T18	17340	0	0	0
T19	1379956	1	0	0
T20	0	6	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2570	0	0
T1	722500	1	0	0
T2	615768	1	0	0
T3	1553816	10	0	0
T4	108388	0	0	0
T5	3464280	2	0	0
T9	62466	0	0	0
T12	1106212	1	0	0
T13	390798	5	0	0
T14	0	11	0	0
T15	0	4	0	0
T16	4428	1	0	0
T17	1233536	6	0	0
T18	17340	0	0	0
T19	1379956	1	0	0
T20	0	6	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T1	722500	1	0	0
T2	615768	1	0	0
T3	1553816	10	0	0
T4	108388	0	0	0
T5	3464280	2	0	0
T9	62466	0	0	0
T12	1106212	1	0	0
T13	390798	5	0	0
T14	0	10	0	0
T15	0	4	0	0
T16	4428	1	0	0
T17	1233536	6	0	0
T18	17340	0	0	0
T19	1379956	1	0	0
T20	0	6	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2464	0	0
T1	722500	1	0	0
T2	615768	1	0	0
T3	1553816	10	0	0
T4	108388	0	0	0
T5	3464280	2	0	0
T9	62466	0	0	0
T12	1106212	1	0	0
T13	390798	4	0	0
T14	0	9	0	0
T15	0	3	0	0
T16	4428	1	0	0
T17	1233536	6	0	0
T18	17340	0	0	0
T19	1379956	1	0	0
T20	0	5	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5240	0	0
T3	1165362	23	0	0
T4	81291	0	0	0
T5	2598210	0	0	0
T7	119569	0	0	0
T9	62466	0	0	0
T12	829659	0	0	0
T13	586197	0	0	0
T14	0	7	0	0
T15	420122	5	0	0
T16	3321	0	0	0
T17	925152	3	0	0
T18	13005	0	0	0
T19	1034967	0	0	0
T20	0	8	0	0
T21	0	2	0	0
T22	0	5	0	0
T39	0	1	0	0
T40	441747	0	0	0
T41	64783	2	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T44	0	1	0	0
T45	0	11	0	0
T47	0	23	0	0
T60	167079	5	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T65	0	4	0	0
T70	0	5	0	0
T71	0	3	0	0
T76	0	2	0	0
T77	0	6	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	560213	0	0
T3	1165362	2727	0	0
T4	81291	0	0	0
T5	2598210	0	0	0
T7	119569	0	0	0
T9	62466	0	0	0
T12	829659	0	0	0
T13	586197	0	0	0
T14	0	773	0	0
T15	420122	355	0	0
T16	3321	0	0	0
T17	925152	408	0	0
T18	13005	0	0	0
T19	1034967	0	0	0
T20	0	1414	0	0
T21	0	58	0	0
T22	0	51	0	0
T39	0	182	0	0
T40	441747	0	0	0
T41	64783	191	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T44	0	1	0	0
T45	0	3586	0	0
T47	0	1743	0	0
T60	167079	583	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T65	0	420	0	0
T70	0	594	0	0
T71	0	896	0	0
T76	0	478	0	0
T77	0	382	0	0
T78	0	19	0	0
T79	0	122	0	0
T80	0	1059	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4896	0	0
T3	388454	20	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T6	215468	0	0	0
T9	41644	0	0	0
T12	276553	0	0	0
T13	390798	0	0	0
T14	0	5	0	0
T16	1107	0	0	0
T17	616768	3	0	0
T18	8670	0	0	0
T19	689978	0	0	0
T20	73386	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T28	0	3	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T39	0	1	0	0
T41	0	2	0	0
T45	0	14	0	0
T47	0	37	0	0
T48	0	17	0	0
T60	0	5	0	0
T65	0	7	0	0
T70	0	5	0	0
T75	235145	0	0	0
T76	0	2	0	0
T77	5963	6	0	0
T78	123049	0	0	0
T79	0	2	0	0
T80	0	8	0	0
T81	0	1	0	0
T82	0	8	0	0
T83	451768	0	0	0
T84	257093	0	0	0
T85	8202	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T6	215468	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T14	987588	2	0	0
T15	420122	3	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	73386	6	0	0
T28	0	1	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0
T37	99727	0	0	0
T38	25082	0	0	0
T45	0	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	2	0	0
T71	0	3	0	0
T78	0	1	0	0
T80	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	5	0	0
T91	0	1	0	0
T92	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4362	0	0
T6	861872	0	0	0
T9	83288	697	0	0
T10	0	716	0	0
T11	0	758	0	0
T13	781596	0	0	0
T14	3950352	0	0	0
T20	293544	0	0	0
T30	0	1493	0	0
T31	0	698	0	0
T32	37252	0	0	0
T33	118444	0	0	0
T34	132408	0	0	0
T35	20248	0	0	0
T36	46584	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3642	0	0
T6	861872	0	0	0
T9	83288	577	0	0
T10	0	596	0	0
T11	0	638	0	0
T13	781596	0	0	0
T14	3950352	0	0	0
T20	293544	0	0	0
T30	0	1253	0	0
T31	0	578	0	0
T32	37252	0	0	0
T33	118444	0	0	0
T34	132408	0	0	0
T35	20248	0	0	0
T36	46584	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2890000	2889700	0	0
T2	1231536	1231500	0	0
T3	1553816	1553628	0	0
T4	108388	107752	0	0
T5	3464280	3464080	0	0
T12	1106212	1106188	0	0
T16	4428	4176	0	0
T17	1233536	1233284	0	0
T18	17340	17088	0	0
T19	1379956	1379632	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2890000	2889700	0	0
T2	1231536	1231500	0	0
T3	1553816	1553628	0	0
T4	108388	107752	0	0
T5	3464280	3464080	0	0
T12	1106212	1106188	0	0
T16	4428	4176	0	0
T17	1233536	1233284	0	0
T18	17340	17088	0	0
T19	1379956	1379632	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T12,T17
1	0	1	Covered	T3,T5,T17
1	1	0	Covered	T3,T12,T17
1	1	1	Covered	T3,T17,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T17,T20
0	1	Covered	T20,T14,T78
1	0	Covered	T15,T21,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T17,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T21,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Not Covered
1	1	Covered	T20,T14,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T3,T13,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T5,T17,T72

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T17
1	Covered	T12,T14,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T3,T17,T33

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T17,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T12,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T5,T12
Phase1St	198	Covered	T3,T5,T12
Phase2St	215	Covered	T3,T5,T12
Phase3St	233	Covered	T3,T5,T12
TerminalSt	249	Covered	T3,T5,T12
TimeoutSt	159	Covered	T3,T17,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T5,T12
IdleSt->TimeoutSt	159	Covered	T3,T17,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T25,T93
Phase0St->Phase1St	198	Covered	T3,T5,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T27,T29
Phase1St->Phase2St	215	Covered	T3,T5,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T14,T27,T29
Phase2St->Phase3St	233	Covered	T3,T5,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T14,T38,T72
Phase3St->TerminalSt	249	Covered	T3,T5,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T17,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T17,T20
TimeoutSt->Phase0St	172	Covered	T20,T14,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T14,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T25,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T27,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T38,T72
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T14,T37
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	640540413	207	0	0
CheckAccumTrig0_A	640540413	908	0	0
CheckAccumTrig1_A	640540413	45	0	0
CheckClr_A	640540413	490	0	0
CheckEn_A	640359294	219557274	0	0
CheckPhase0_A	640540413	985	0	0
CheckPhase1_A	640540413	963	0	0
CheckPhase2_A	640540413	938	0	0
CheckPhase3_A	640540413	912	0	0
CheckTimeout0_A	640540413	1509	0	0
CheckTimeoutSt1_A	640540413	155697	0	0
CheckTimeoutSt2_A	640540413	1412	0	0
CheckTimeoutStTrig_A	640540413	51	0	0
ErrorStAllEscAsserted_A	640540413	1101	0	0
ErrorStIsTerminal_A	640540413	921	0	0
EscStateOut_A	640357743	640288734	0	0
u_state_regs_A	640540413	640394565	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	207	0	0
T6	215468	0	0	0
T9	20822	39	0	0
T10	0	50	0	0
T11	0	28	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	73	0	0
T31	0	17	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	908	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	1	0	0
T13	195399	1	0	0
T14	0	5	0	0
T16	1107	0	0	0
T17	308384	4	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	7	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	45	0	0
T7	119569	0	0	0
T15	420122	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T28	0	1	0	0
T40	441747	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T60	167079	0	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	490	0	0
T6	215468	0	0	0
T14	987588	5	0	0
T15	0	5	0	0
T20	73386	2	0	0
T23	0	1	0	0
T26	0	1	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0
T37	99727	1	0	0
T38	25082	6	0	0
T60	0	2	0	0
T62	0	1	0	0
T72	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640359294	219557274	0	0
T1	722500	722424	0	0
T2	307884	307875	0	0
T3	388454	317282	0	0
T4	27097	703	0	0
T5	866070	143568	0	0
T12	276553	16920	0	0
T16	1107	627	0	0
T17	308384	370467	0	0
T18	4335	2010	0	0
T19	344989	338060	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	985	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	1	0	0
T13	195399	1	0	0
T14	0	7	0	0
T16	1107	0	0	0
T17	308384	4	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	963	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	1	0	0
T13	195399	1	0	0
T14	0	7	0	0
T16	1107	0	0	0
T17	308384	4	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	938	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	1	0	0
T13	195399	1	0	0
T14	0	6	0	0
T16	1107	0	0	0
T17	308384	4	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	912	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	1	0	0
T13	195399	1	0	0
T14	0	5	0	0
T16	1107	0	0	0
T17	308384	4	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1509	0	0
T3	388454	20	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	5	0	0
T21	0	2	0	0
T39	0	1	0	0
T60	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	155697	0	0
T3	388454	2398	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T14	0	36	0	0
T15	0	4	0	0
T16	1107	0	0	0
T17	308384	110	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	985	0	0
T21	0	58	0	0
T39	0	182	0	0
T60	0	583	0	0
T77	0	67	0	0
T78	0	19	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1412	0	0
T3	388454	20	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T39	0	1	0	0
T45	0	7	0	0
T60	0	5	0	0
T65	0	3	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	51	0	0
T6	215468	0	0	0
T14	987588	2	0	0
T20	73386	3	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0
T37	99727	0	0	0
T38	25082	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T87	0	1	0	0
T90	0	2	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1101	0	0
T6	215468	0	0	0
T9	20822	189	0	0
T10	0	197	0	0
T11	0	188	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	356	0	0
T31	0	171	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	921	0	0
T6	215468	0	0	0
T9	20822	159	0	0
T10	0	167	0	0
T11	0	158	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	296	0	0
T31	0	141	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640357743	640288734	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	640394565	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T13
1	0	1	Covered	T3,T17,T19
1	1	0	Covered	T3,T17,T39
1	1	1	Covered	T3,T17,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T17,T20
0	1	Covered	T3,T20,T71
1	0	Covered	T22,T49,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T17,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T49,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Not Covered
1	1	Covered	T3,T20,T71

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T17,T38

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T14,T36,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T13,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T13
1	Covered	T2,T3,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T13,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T5
Phase1St	198	Covered	T2,T3,T5
Phase2St	215	Covered	T2,T3,T5
Phase3St	233	Covered	T2,T3,T5
TerminalSt	249	Covered	T2,T3,T5
TimeoutSt	159	Covered	T3,T17,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T5
IdleSt->TimeoutSt	159	Covered	T3,T17,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T87,T51,T94
Phase0St->Phase1St	198	Covered	T2,T3,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T95,T96,T97
Phase1St->Phase2St	215	Covered	T2,T3,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T98,T96,T99
Phase2St->Phase3St	233	Covered	T2,T3,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T75,T100
Phase3St->TerminalSt	249	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T17,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T41,T76
TimeoutSt->Phase0St	172	Covered	T3,T20,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T41,T76
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T87,T101,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T95,T96,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T98,T96,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T75,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T20,T36
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	640540413	202	0	0
CheckAccumTrig0_A	640540413	478	0	0
CheckAccumTrig1_A	640540413	13	0	0
CheckClr_A	640540413	197	0	0
CheckEn_A	640359294	260993499	0	0
CheckPhase0_A	640540413	537	0	0
CheckPhase1_A	640540413	527	0	0
CheckPhase2_A	640540413	524	0	0
CheckPhase3_A	640540413	515	0	0
CheckTimeout0_A	640540413	1563	0	0
CheckTimeoutSt1_A	640540413	167540	0	0
CheckTimeoutSt2_A	640540413	1488	0	0
CheckTimeoutStTrig_A	640540413	57	0	0
ErrorStAllEscAsserted_A	640540413	1085	0	0
ErrorStIsTerminal_A	640540413	905	0	0
EscStateOut_A	640357743	640288734	0	0
u_state_regs_A	640540413	640394565	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	202	0	0
T6	215468	0	0	0
T9	20822	21	0	0
T10	0	49	0	0
T11	0	34	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	70	0	0
T31	0	28	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	478	0	0
T2	307884	1	0	0
T3	388454	4	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	13	0	0
T22	400090	1	0	0
T44	38283	0	0	0
T49	0	2	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T64	22265	0	0	0
T65	15504	0	0	0
T66	40648	0	0	0
T67	153338	0	0	0
T68	551489	0	0	0
T69	163883	0	0	0
T70	37349	0	0	0
T71	34012	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	197	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	2	0	0
T28	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T68	0	1	0	0
T73	0	7	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640359294	260993499	0	0
T1	722500	722424	0	0
T2	307884	5973	0	0
T3	388454	190466	0	0
T4	27097	707	0	0
T5	866070	41515	0	0
T12	276553	276547	0	0
T16	1107	631	0	0
T17	308384	424193	0	0
T18	4335	2027	0	0
T19	344989	10178	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	537	0	0
T2	307884	1	0	0
T3	388454	6	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	1	0	0
T20	0	3	0	0
T36	0	2	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	527	0	0
T2	307884	1	0	0
T3	388454	6	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	1	0	0
T20	0	3	0	0
T36	0	2	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	524	0	0
T2	307884	1	0	0
T3	388454	6	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	1	0	0
T20	0	3	0	0
T36	0	2	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	515	0	0
T2	307884	1	0	0
T3	388454	6	0	0
T4	27097	0	0	0
T5	866070	1	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	1	0	0
T20	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1563	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T22	0	1	0	0
T41	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	167540	0	0
T3	388454	208	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	298	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	429	0	0
T41	0	191	0	0
T45	0	392	0	0
T70	0	236	0	0
T71	0	489	0	0
T76	0	239	0	0
T77	0	177	0	0
T80	0	124	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1488	0	0
T6	215468	0	0	0
T9	20822	0	0	0
T13	195399	0	0	0
T17	308384	2	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	73386	0	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T41	0	2	0	0
T45	0	1	0	0
T47	0	15	0	0
T48	0	5	0	0
T70	0	2	0	0
T76	0	1	0	0
T77	0	3	0	0
T80	0	1	0	0
T82	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	57	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T20	0	3	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T71	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1085	0	0
T6	215468	0	0	0
T9	20822	181	0	0
T10	0	184	0	0
T11	0	199	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	362	0	0
T31	0	159	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	905	0	0
T6	215468	0	0	0
T9	20822	151	0	0
T10	0	154	0	0
T11	0	169	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	302	0	0
T31	0	129	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640357743	640288734	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	640394565	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T13,T14
1	0	1	Covered	T3,T16,T17
1	1	0	Covered	T3,T17,T13
1	1	1	Covered	T15,T77,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T77,T22
0	1	Covered	T15,T71,T45
1	0	Covered	T22,T44,T70

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T77,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T44,T70

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T77,T22
1	0	Not Covered
1	1	Covered	T15,T71,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T1,T16,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T13,T39,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T13
1	Covered	T3,T74,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T14,T15,T69

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T16,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T16
Phase1St	198	Covered	T1,T3,T16
Phase2St	215	Covered	T1,T3,T16
Phase3St	233	Covered	T1,T3,T16
TerminalSt	249	Covered	T1,T3,T16
TimeoutSt	159	Covered	T15,T77,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T16
IdleSt->TimeoutSt	159	Covered	T15,T77,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T51,T103
Phase0St->Phase1St	198	Covered	T1,T3,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T104,T97
Phase1St->Phase2St	215	Covered	T1,T3,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T105,T104,T106
Phase2St->Phase3St	233	Covered	T1,T3,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T15,T107
Phase3St->TerminalSt	249	Covered	T1,T3,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T13,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T77,T22,T70
TimeoutSt->Phase0St	172	Covered	T15,T22,T44

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T77,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T22,T44
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T77,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T77,T22,T70
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T103,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T104,T97,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T105,T104,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T15,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T15,T74
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	640540413	157	0	0
CheckAccumTrig0_A	640540413	445	0	0
CheckAccumTrig1_A	640540413	29	0	0
CheckClr_A	640540413	199	0	0
CheckEn_A	640359294	317439193	0	0
CheckPhase0_A	640540413	533	0	0
CheckPhase1_A	640540413	525	0	0
CheckPhase2_A	640540413	512	0	0
CheckPhase3_A	640540413	505	0	0
CheckTimeout0_A	640540413	1154	0	0
CheckTimeoutSt1_A	640540413	126745	0	0
CheckTimeoutSt2_A	640540413	1059	0	0
CheckTimeoutStTrig_A	640540413	65	0	0
ErrorStAllEscAsserted_A	640540413	1089	0	0
ErrorStIsTerminal_A	640540413	909	0	0
EscStateOut_A	640357743	640288734	0	0
u_state_regs_A	640540413	640394565	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	157	0	0
T6	215468	0	0	0
T9	20822	36	0	0
T10	0	21	0	0
T11	0	14	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	66	0	0
T31	0	20	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	445	0	0
T1	722500	1	0	0
T2	307884	0	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	1107	1	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	29	0	0
T22	400090	3	0	0
T24	0	2	0	0
T44	38283	1	0	0
T48	0	1	0	0
T64	22265	0	0	0
T65	15504	0	0	0
T66	40648	0	0	0
T67	153338	0	0	0
T68	551489	0	0	0
T69	163883	0	0	0
T70	37349	0	0	0
T71	34012	0	0	0
T98	0	1	0	0
T105	0	2	0	0
T107	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	199	0	0
T6	215468	0	0	0
T13	195399	2	0	0
T14	987588	0	0	0
T15	0	3	0	0
T20	73386	0	0	0
T22	0	4	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0
T37	99727	0	0	0
T45	0	2	0	0
T47	0	3	0	0
T70	0	2	0	0
T71	0	2	0	0
T74	0	1	0	0
T81	0	3	0	0
T113	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640359294	317439193	0	0
T1	722500	9374	0	0
T2	307884	307477	0	0
T3	388454	500298	0	0
T4	27097	711	0	0
T5	866070	866019	0	0
T12	276553	276160	0	0
T16	1107	635	0	0
T17	308384	306831	0	0
T18	4335	4271	0	0
T19	344989	324180	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	533	0	0
T1	722500	1	0	0
T2	307884	0	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	0	4	0	0
T16	1107	1	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	525	0	0
T1	722500	1	0	0
T2	307884	0	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	0	4	0	0
T16	1107	1	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	512	0	0
T1	722500	1	0	0
T2	307884	0	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	0	4	0	0
T16	1107	1	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	505	0	0
T1	722500	1	0	0
T2	307884	0	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T12	276553	0	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	3	0	0
T16	1107	1	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1154	0	0
T7	119569	0	0	0
T15	420122	3	0	0
T22	0	4	0	0
T40	441747	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T44	0	1	0	0
T45	0	8	0	0
T47	0	13	0	0
T60	167079	0	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T70	0	3	0	0
T71	0	2	0	0
T77	0	2	0	0
T79	0	1	0	0
T80	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	126745	0	0
T7	119569	0	0	0
T15	420122	351	0	0
T22	0	51	0	0
T40	441747	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T44	0	1	0	0
T45	0	2306	0	0
T47	0	990	0	0
T60	167079	0	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T70	0	358	0	0
T71	0	407	0	0
T77	0	138	0	0
T79	0	122	0	0
T80	0	619	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1059	0	0
T21	10648	0	0	0
T22	400090	1	0	0
T28	0	3	0	0
T45	0	5	0	0
T47	0	13	0	0
T48	0	6	0	0
T64	22265	0	0	0
T70	0	3	0	0
T75	235145	0	0	0
T77	5963	2	0	0
T78	123049	0	0	0
T79	0	1	0	0
T80	0	5	0	0
T82	0	2	0	0
T83	451768	0	0	0
T84	257093	0	0	0
T85	8202	0	0	0
T114	8974	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	65	0	0
T7	119569	0	0	0
T15	420122	3	0	0
T28	0	1	0	0
T40	441747	0	0	0
T41	64783	0	0	0
T42	175248	0	0	0
T43	145315	0	0	0
T45	0	3	0	0
T60	167079	0	0	0
T61	3337	0	0	0
T62	57322	0	0	0
T63	97039	0	0	0
T71	0	2	0	0
T86	0	1	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T115	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1089	0	0
T6	215468	0	0	0
T9	20822	177	0	0
T10	0	168	0	0
T11	0	179	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	394	0	0
T31	0	171	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	909	0	0
T6	215468	0	0	0
T9	20822	147	0	0
T10	0	138	0	0
T11	0	149	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	334	0	0
T31	0	141	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640357743	640288734	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	640394565	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T17,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T34
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T3,T20,T14
1	1	1	Covered	T3,T14,T76

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T14,T76
0	1	Covered	T3,T45,T47
1	0	Covered	T45,T116,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T14,T76
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T45,T116,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T76
1	0	Not Covered
1	1	Covered	T3,T45,T47

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T13
1	Covered	T3,T14,T60

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T13,T14
1	Covered	T17,T15,T69

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T13
1	Covered	T3,T13,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T13
1	Covered	T3,T13,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T17,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T17,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T17,T13
Phase1St	198	Covered	T3,T17,T13
Phase2St	215	Covered	T3,T17,T13
Phase3St	233	Covered	T3,T17,T13
TerminalSt	249	Covered	T3,T17,T13
TimeoutSt	159	Covered	T3,T14,T76

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T3,T17,T13
IdleSt->TimeoutSt	159	Covered	T3,T14,T76
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T3,T27,T87
Phase0St->Phase1St	198	Covered	T3,T17,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T117,T49,T118
Phase1St->Phase2St	215	Covered	T3,T17,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T119,T120,T94
Phase2St->Phase3St	233	Covered	T3,T17,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T27,T121
Phase3St->TerminalSt	249	Covered	T3,T17,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T17,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T76,T65
TimeoutSt->Phase0St	172	Covered	T3,T45,T116

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T76
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T45,T116
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T14,T76
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T76,T65
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T27,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T17,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T17,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T117,T49,T118
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T17,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T17,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T119,T120,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T17,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T17,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T27,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T17,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T17,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T13,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T17,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	640540413	234	0	0
CheckAccumTrig0_A	640540413	510	0	0
CheckAccumTrig1_A	640540413	17	0	0
CheckClr_A	640540413	250	0	0
CheckEn_A	640359294	275875754	0	0
CheckPhase0_A	640540413	565	0	0
CheckPhase1_A	640540413	555	0	0
CheckPhase2_A	640540413	547	0	0
CheckPhase3_A	640540413	532	0	0
CheckTimeout0_A	640540413	1014	0	0
CheckTimeoutSt1_A	640540413	110231	0	0
CheckTimeoutSt2_A	640540413	937	0	0
CheckTimeoutStTrig_A	640540413	59	0	0
ErrorStAllEscAsserted_A	640540413	1087	0	0
ErrorStIsTerminal_A	640540413	907	0	0
EscStateOut_A	640357743	640288734	0	0
u_state_regs_A	640540413	640394565	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	234	0	0
T6	215468	0	0	0
T9	20822	41	0	0
T10	0	45	0	0
T11	0	45	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	82	0	0
T31	0	21	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	510	0	0
T3	388454	3	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	2	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	17	0	0
T27	47830	0	0	0
T45	204793	1	0	0
T46	15309	0	0	0
T47	133517	0	0	0
T49	0	1	0	0
T57	0	1	0	0
T81	34787	0	0	0
T92	0	1	0	0
T101	0	1	0	0
T116	286901	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	26214	0	0	0
T127	7044	0	0	0
T128	32682	0	0	0
T129	452703	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	250	0	0
T3	388454	2	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T45	0	3	0	0
T47	0	1	0	0
T60	0	1	0	0
T79	0	1	0	0
T129	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640359294	275875754	0	0
T1	722500	721368	0	0
T2	307884	307477	0	0
T3	388454	377931	0	0
T4	27097	26936	0	0
T5	866070	47604	0	0
T12	276553	276547	0	0
T16	1107	639	0	0
T17	308384	302996	0	0
T18	4335	2056	0	0
T19	344989	341585	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	565	0	0
T3	388454	3	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	2	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	555	0	0
T3	388454	3	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	2	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	547	0	0
T3	388454	3	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	2	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	532	0	0
T3	388454	3	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	2	0	0
T14	0	7	0	0
T15	0	2	0	0
T16	1107	0	0	0
T17	308384	1	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1014	0	0
T3	388454	1	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T14	0	5	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T45	0	3	0	0
T47	0	10	0	0
T65	0	4	0	0
T76	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	3	0	0
T116	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	110231	0	0
T3	388454	121	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T14	0	737	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T45	0	888	0	0
T47	0	753	0	0
T65	0	420	0	0
T76	0	239	0	0
T80	0	316	0	0
T81	0	153	0	0
T82	0	352	0	0
T116	0	2	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	937	0	0
T10	82367	0	0	0
T14	987588	5	0	0
T24	0	5	0	0
T35	5062	0	0	0
T36	11646	0	0	0
T37	99727	0	0	0
T38	25082	0	0	0
T39	26239	0	0	0
T45	0	1	0	0
T47	0	9	0	0
T48	0	6	0	0
T65	0	4	0	0
T72	55005	0	0	0
T76	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	3	0	0
T130	63608	0	0	0
T131	9161	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	59	0	0
T3	388454	1	0	0
T4	27097	0	0	0
T5	866070	0	0	0
T9	20822	0	0	0
T12	276553	0	0	0
T13	195399	0	0	0
T16	1107	0	0	0
T17	308384	0	0	0
T18	4335	0	0	0
T19	344989	0	0	0
T24	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T132	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	1087	0	0
T6	215468	0	0	0
T9	20822	150	0	0
T10	0	167	0	0
T11	0	192	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	381	0	0
T31	0	197	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	907	0	0
T6	215468	0	0	0
T9	20822	120	0	0
T10	0	137	0	0
T11	0	162	0	0
T13	195399	0	0	0
T14	987588	0	0	0
T20	73386	0	0	0
T30	0	321	0	0
T31	0	167	0	0
T32	9313	0	0	0
T33	29611	0	0	0
T34	33102	0	0	0
T35	5062	0	0	0
T36	11646	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640357743	640288734	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640540413	640394565	0	0
T1	722500	722425	0	0
T2	307884	307875	0	0
T3	388454	388407	0	0
T4	27097	26938	0	0
T5	866070	866020	0	0
T12	276553	276547	0	0
T16	1107	1044	0	0
T17	308384	308321	0	0
T18	4335	4272	0	0
T19	344989	344908	0	0