Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	74324	1			T28	5		T23	652		T14	28
class_i[0x1]	75511	1			T4	13		T23	156		T14	1
class_i[0x2]	70702	1			T4	127		T23	1335		T14	3
class_i[0x3]	77960	1			T4	6		T23	635		T14	38

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	76193	1			T4	21		T28	3		T23	185
alert[0x1]	77830	1			T4	33		T28	1		T23	1534
alert[0x2]	76082	1			T4	34		T28	1		T23	814
alert[0x3]	68392	1			T4	58		T23	245		T14	13

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

298231

1

T4

146

T28

5

T23

2778

esc_ping_fail

266

1

T8

4

T9

6

T85

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	76119	1			T4	21		T28	3		T23	185
esc_integrity_fail	alert[0x1]	77755	1			T4	33		T28	1		T23	1534
esc_integrity_fail	alert[0x2]	76021	1			T4	34		T28	1		T23	814
esc_integrity_fail	alert[0x3]	68336	1			T4	58		T23	245		T14	13
esc_ping_fail	alert[0x0]	74	1			T8	1		T9	3		T85	1
esc_ping_fail	alert[0x1]	75	1			T8	1		T9	2		T85	1
esc_ping_fail	alert[0x2]	61	1			T8	1		T295	2		T103	1
esc_ping_fail	alert[0x3]	56	1			T8	1		T9	1		T84	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	74277	1			T28	5		T23	652		T14	28
esc_integrity_fail	class_i[0x1]	75423	1			T4	13		T23	156		T14	1
esc_integrity_fail	class_i[0x2]	70624	1			T4	127		T23	1335		T14	3
esc_integrity_fail	class_i[0x3]	77907	1			T4	6		T23	635		T14	38
esc_ping_fail	class_i[0x0]	47	1			T9	5		T296	3		T287	2
esc_ping_fail	class_i[0x1]	88	1			T8	4		T85	2		T290	11
esc_ping_fail	class_i[0x2]	78	1			T295	4		T84	4		T300	1
esc_ping_fail	class_i[0x3]	53	1			T9	1		T103	1		T286	4