Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	667945598	0	0	629
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	667945598	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	667945598	667755110	0	0
tb.dut.CheckAccuCntDw	0	0	629	629	0	0
tb.dut.CheckEscCntDw	0	0	629	629	0	0
tb.dut.CheckNAlerts	0	0	629	629	0	0
tb.dut.CheckNClasses	0	0	629	629	0	0
tb.dut.CheckNEscSev	0	0	629	629	0	0
tb.dut.CrashdumpKnownO_A	0	0	667945598	667755110	0	0
tb.dut.EdnKnownO_A	0	0	667945598	667755110	0	0
tb.dut.EscPKnownO_A	0	0	667945598	667755110	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	667945598	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	667945598	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	667945598	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	667945598	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	667945598	90	0	0
tb.dut.IrqAKnownO_A	0	0	667945598	667755110	0	0
tb.dut.IrqBKnownO_A	0	0	667945598	667755110	0	0
tb.dut.IrqCKnownO_A	0	0	667945598	667755110	0	0
tb.dut.IrqDKnownO_A	0	0	667945598	667755110	0	0
tb.dut.TlAReadyKnownO_A	0	0	667945598	667755110	0	0
tb.dut.TlDValidKnownO_A	0	0	667945598	667755110	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	694610983	3550896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	694610983	16848	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	694610983	20819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	694610983	18037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	694610983	17980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	694610983	19345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	694610983	20538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	694610983	19268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	694610983	18369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	694610983	16898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	694610983	19429	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	694610983	17989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	694610983	17832	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	694610983	20290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	694610983	18160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	694610983	16864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	694610983	17091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	694610983	18392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	694610983	16893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	694610983	19554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	694610983	17972	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	694610983	17683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	694610983	19329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	694610983	18320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	694610983	18487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	694610983	19147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	694610983	18363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	694610983	19249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	694610983	18867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	694610983	18774	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	694610983	19558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	694610983	18149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	694610983	18334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	694610983	16950	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	694610983	18219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	694610983	17233	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	694610983	19284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	694610983	18271	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	694610983	18305	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	694610983	18995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	694610983	17822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	694610983	18161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	694610983	16827	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	694610983	19278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	694610983	17898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	694610983	17117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	694610983	18121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	694610983	16901	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	694610983	17026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	694610983	19482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	694610983	19402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	694610983	18030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	694610983	16771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	694610983	17939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	694610983	17882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	694610983	19202	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	694610983	18052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	694610983	18388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	694610983	18085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	694610983	17980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	694610983	17113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	694610983	18268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	694610983	17291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	694610983	18970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	694610983	18114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	694610983	19274	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	694610983	17731	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	694610983	16866	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	694610983	18117	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	694610983	17078	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	694610983	37323	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	694610983	19939	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	694610983	16760	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	694610983	19094	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	694610983	19046	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	694610983	17228	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	694610983	18035	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	694610983	16789	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	694610983	21334	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	667945598	3084	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	667945598	275576	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	667945598	302214448	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	667945598	317	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	667945598	906	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	667945598	60	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	667945598	462	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	667757859	222013629	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	667945598	1048	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	667945598	1029	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	667945598	1006	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	667945598	980	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	667945598	1784	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	667945598	177219	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	667945598	1626	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	667945598	95	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667945598	1622	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	667945598	1352	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	667756087	667680786	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	667945598	667755110	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	667945598	3455	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	667945598	171406	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	667945598	391326474	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	667945598	283	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	667945598	536	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	667945598	31	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	667945598	265	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	667757859	303604885	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	667945598	628	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	667945598	618	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	667945598	612	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	667945598	600	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	667945598	1153	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	667945598	108104	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	667945598	1042	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	667945598	78	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667945598	1654	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	667945598	1384	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	667756087	667680786	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	667945598	667755110	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	667945598	2651	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	667945598	183515	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	667945598	387678785	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	667945598	285	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	667945598	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	667945598	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	667945598	224	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	667757859	314714708	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	667945598	579	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	667945598	571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	667945598	566	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	667945598	559	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	667945598	1505	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	667945598	155872	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	667945598	1418	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	667945598	64	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667945598	1656	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	667945598	1386	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	667756087	667680786	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	667945598	667755110	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	667945598	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	667945598	5411	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	667945598	199599	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	667945598	383990517	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	667945598	302	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	667945598	541	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	667945598	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	667945598	264	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	667757859	298626797	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	667945598	628	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	667945598	616	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	667945598	599	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	667945598	588	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	667945598	1193	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	667945598	123217	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	667945598	1088	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	667945598	81	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667945598	1608	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	667945598	1338	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	667756087	667680786	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	667945598	667755110	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	694610983	146501803	0	0
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