Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	173	1			T23	4		T26	1		T67	1
index[0x1]	170	1			T27	1		T23	3		T64	1
index[0x2]	165	1			T7	1		T23	3		T25	1
index[0x3]	195	1			T35	2		T19	1		T51	3

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	237	1			T27	1		T23	3		T8	2
lens_less_than_1000[1]	139	1			T7	1		T23	1		T26	1
lens_less_than_1000[2]	97	1			T23	5		T104	1		T39	1
lens_less_than_1000[3]	65	1			T14	1		T39	1		T38	2
lens_less_than_1000[4]	49	1			T35	1		T69	2		T72	1
lens_less_than_1000[5]	33	1			T23	1		T25	1		T67	1
lens_less_than_1000[6]	33	1			T26	1		T39	1		T260	1
lens_less_than_1000[7]	20	1			T33	1		T95	2		T261	1
lens_less_than_1000[8]	16	1			T32	1		T33	1		T59	2
lens_less_than_1000[9]	3	1			T103	2		T109	1		-	-
len_2	11	1			T67	1		T10	1		T262	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T73	1		T69	2		T187	1
index[0x0]	lens_less_than_1000[1]	24	1			T69	1		T59	2		T88	1
index[0x0]	lens_less_than_1000[2]	35	1			T23	4		T39	1		T233	1
index[0x0]	lens_less_than_1000[3]	15	1			T39	1		T38	1		T263	1
index[0x0]	lens_less_than_1000[4]	13	1			T69	1		T10	1		T75	1
index[0x0]	lens_less_than_1000[5]	10	1			T67	1		T10	1		T264	1
index[0x0]	lens_less_than_1000[6]	8	1			T26	1		T39	1		T37	1
index[0x0]	lens_less_than_1000[7]	5	1			T95	1		T258	1		T245	1
index[0x0]	lens_less_than_1000[8]	4	1			T33	1		T59	2		T265	1
index[0x0]	lens_less_than_1000[9]	2	1			T103	1		T109	1		-	-
index[0x0]	len_2	2	1			T10	1		T82	1		-	-
index[0x1]	lens_less_than_1000[0]	70	1			T27	1		T23	1		T64	1
index[0x1]	lens_less_than_1000[1]	26	1			T23	1		T33	1		T40	1
index[0x1]	lens_less_than_1000[2]	17	1			T23	1		T186	1		T44	1
index[0x1]	lens_less_than_1000[3]	10	1			T77	2		T95	1		T90	1
index[0x1]	lens_less_than_1000[4]	17	1			T69	1		T72	1		T266	1
index[0x1]	lens_less_than_1000[5]	6	1			T34	1		T88	1		T90	1
index[0x1]	lens_less_than_1000[6]	14	1			T54	1		T57	1		T267	1
index[0x1]	lens_less_than_1000[7]	6	1			T95	1		T61	1		T268	1
index[0x1]	lens_less_than_1000[8]	2	1			T265	1		T269	1		-	-
index[0x1]	len_2	2	1			T67	1		T262	1		-	-
index[0x2]	lens_less_than_1000[0]	48	1			T23	2		T8	2		T69	1
index[0x2]	lens_less_than_1000[1]	37	1			T7	1		T26	1		T67	2
index[0x2]	lens_less_than_1000[2]	22	1			T103	2		T234	1		T270	1
index[0x2]	lens_less_than_1000[3]	14	1			T14	1		T38	1		T10	1
index[0x2]	lens_less_than_1000[4]	11	1			T35	1		T77	1		T108	1
index[0x2]	lens_less_than_1000[5]	12	1			T23	1		T25	1		T77	1
index[0x2]	lens_less_than_1000[6]	5	1			T75	1		T271	1		T272	1
index[0x2]	lens_less_than_1000[7]	6	1			T261	1		T192	1		T273	1
index[0x2]	lens_less_than_1000[8]	8	1			T272	7		T82	1		-	-
index[0x2]	len_2	2	1			T270	1		T268	1		-	-
index[0x3]	lens_less_than_1000[0]	64	1			T35	2		T19	1		T51	2
index[0x3]	lens_less_than_1000[1]	52	1			T51	1		T36	2		T33	11
index[0x3]	lens_less_than_1000[2]	23	1			T104	1		T69	2		T44	1
index[0x3]	lens_less_than_1000[3]	26	1			T179	1		T174	1		T30	1
index[0x3]	lens_less_than_1000[4]	8	1			T10	1		T106	1		T258	2
index[0x3]	lens_less_than_1000[5]	5	1			T106	1		T193	1		T274	1
index[0x3]	lens_less_than_1000[6]	6	1			T260	1		T106	1		T275	1
index[0x3]	lens_less_than_1000[7]	3	1			T33	1		T242	1		T276	1
index[0x3]	lens_less_than_1000[8]	2	1			T32	1		T277	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T103	1		-	-		-	-
index[0x3]	len_2	5	1			T93	1		T252	1		T249	1