Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	95	1			T23	2		T35	1		T52	9
class_index[0x1]	78	1			T2	1		T28	3		T23	8
class_index[0x2]	64	1			T2	2		T28	1		T23	1
class_index[0x3]	81	1			T23	2		T14	1		T16	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	128	1			T23	5		T16	1		T35	1
intr_timeout_cnt[1]	74	1			T2	2		T28	3		T23	5
intr_timeout_cnt[2]	40	1			T23	1		T14	1		T64	1
intr_timeout_cnt[3]	22	1			T28	1		T52	9		T56	1
intr_timeout_cnt[4]	17	1			T10	1		T237	1		T95	5
intr_timeout_cnt[5]	9	1			T74	1		T103	2		T238	1
intr_timeout_cnt[6]	10	1			T44	1		T75	1		T239	1
intr_timeout_cnt[7]	11	1			T2	1		T23	1		T75	1
intr_timeout_cnt[8]	4	1			T172	1		T240	1		T241	1
intr_timeout_cnt[9]	3	1			T23	1		T242	1		T31	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	40	1			T23	1		T35	1		T10	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T53	1		T38	1		T239	1
class_index[0x0]	intr_timeout_cnt[2]	15	1			T23	1		T243	1		T244	1
class_index[0x0]	intr_timeout_cnt[3]	10	1			T52	9		T96	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	5	1			T10	1		T31	1		T245	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T74	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	5	1			T44	1		T88	1		T193	1
class_index[0x0]	intr_timeout_cnt[7]	5	1			T103	1		T90	1		T246	3
class_index[0x1]	intr_timeout_cnt[0]	27	1			T23	3		T39	1		T38	1
class_index[0x1]	intr_timeout_cnt[1]	24	1			T28	3		T23	5		T10	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T64	1		T56	3		T247	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T248	1		T249	1		T250	1
class_index[0x1]	intr_timeout_cnt[4]	6	1			T95	5		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T238	1		T252	1		T253	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T254	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T2	1		T255	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T240	1		T256	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T242	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	23	1			T23	1		T69	2		T10	2
class_index[0x2]	intr_timeout_cnt[1]	19	1			T2	2		T14	1		T67	2
class_index[0x2]	intr_timeout_cnt[2]	6	1			T171	1		T234	1		T227	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T28	1		T257	1		T258	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T237	1		T92	1		T252	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T103	2		T245	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T75	1		T250	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T241	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T31	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	38	1			T16	1		T67	1		T102	1
class_index[0x3]	intr_timeout_cnt[1]	17	1			T95	1		T172	7		T248	2
class_index[0x3]	intr_timeout_cnt[2]	10	1			T14	1		T67	1		T258	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T56	1		T103	1		T95	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T245	1		T82	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T192	1		T259	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T239	1		T173	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	4	1			T23	1		T75	1		T88	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T172	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T23	1		-	-		-	-